EXPRESS specification:

*)
ENTITY absorbed_dose_measure_with_unit
 SUBTYPE OF (measure_with_unit);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\measure_with_unit ||
       SELF\absorbed_dose_measure_with_unit))) = 0;
  WR2: SELF\measure_with_unit.unit_component\si_unit.name = gray;
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SI_UNIT' IN 
       TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY; -- absorbed_dose_measure_with_unit
(*

EXPRESS specification:

*)
ENTITY activity_measure_with_unit
 SUBTYPE OF (measure_with_unit);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\measure_with_unit ||
       SELF\activity_measure_with_unit))) = 0;
  WR2: SELF\measure_with_unit.unit_component\si_unit.name = becquerel;
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SI_UNIT' IN 
       TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY; -- activity_measure_with_unit
(*

EXPRESS specification:

*)
ENTITY add_design_object_assignment
   SUBTYPE OF (action_assignment);
     items : SET [1:?] OF managed_design_object;
WHERE
   WR1: SIZEOF(QUERY(it <* SELF.items |
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'PRODUCT_DEFINITION_RELATIONSHIP' IN TYPEOF(it))
        AND (it\product_definition_relationship.name = 
                       'design object addition'))) = 1;
END_ENTITY; -- add_design_object_assignment
(*

EXPRESS specification:

*)
ENTITY add_design_object_request_assignment
   SUBTYPE OF (action_request_assignment);
     items : SET [1:?] OF managed_design_object;
WHERE
   WR1: SIZEOF(QUERY(it <* SELF.items |
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'PRODUCT_DEFINITION_RELATIONSHIP' IN TYPEOF(it))
        AND (it\product_definition_relationship.name = 
                         'design object addition'))) = 1;
END_ENTITY; -- add_design_object_request_assignment
(*

EXPRESS specification:

*)
ENTITY altered_package_terminal
  ABSTRACT SUPERTYPE OF ((shape_formed_terminal ANDOR
      surface_prepped_terminal) ANDOR length_trimmed_terminal)
   SUBTYPE OF (package_terminal);
WHERE
 WR1: SIZEOF(QUERY ( sar <* USEDIN (SELF,
      'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
      'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'terminal to be altered' ))
       = 1;
 WR2: (SELF.of_shape.definition\product_definition.description =
       'altered package');
END_ENTITY; -- altered_package_terminal
(*

EXPRESS specification:

*)
ENTITY analytical_model
  SUBTYPE OF (representation);
UNIQUE
  UR1: SELF\representation.name;
WHERE
  WR1: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_DOCUMENT_REFERENCE.ITEMS')) = 2;
  WR2: SIZEOF (QUERY (dr <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_DOCUMENT_REFERENCE.ITEMS') |
       dr.assigned_document.kind\document_type.product_data_type = 
       'language reference manual')) = 1;
  WR3: SIZEOF (QUERY (it <* SELF.items |
       NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MODEL_PARAMETER' IN 
       TYPEOF (it)))) = 0;
  WR4: SIZEOF (QUERY (rr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION_RELATIONSHIP.REP_1') |
       (rr\representation_relationship.name = 'access mechanism') AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ANALYTICAL_MODEL_PORT' IN
       TYPEOF (rr.rep_2)))) >= 1;
END_ENTITY; -- analytical_model
(*

EXPRESS specification:

*)
ENTITY analytical_model_definition
 SUBTYPE OF (product_definition);
WHERE
  WR1: (NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_WITH_ASSOCIATED_DOCUMENTS' IN 
       TYPEOF (SELF))) OR
       (SIZEOF (QUERY (docs <* 
       SELF\product_definition_with_associated_documents.
        documentation_ids |
       docs.kind\document_type.product_data_type = 'CAD filename')) <= 1);
  WR2: SIZEOF (QUERY (adta <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'APPLIED_DATE_AND_TIME_ASSIGNMENT.ITEMS') |
       adta.role\date_time_role.name = 'creation date')) + 
       SIZEOF (QUERY (ada <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'APPLIED_DATE_ASSIGNMENT.ITEMS') |
       ada.role\date_role.name = 'creation date')) = 1;
  WR3: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_APPROVAL_ASSIGNMENT.ITEMS')) = 1;
  WR4: SIZEOF (QUERY (apoa <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_PERSON_AND_ORGANIZATION_ASSIGNMENT.ITEMS') |
       apoa.role\person_and_organization_role.name = 'creator')) +
       SIZEOF (QUERY (apoa <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_ORGANIZATION_ASSIGNMENT.ITEMS') |
       apoa.role\organization_role.name = 'creator')) >= 1;
  WR5: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_SECURITY_CLASSIFICATION_ASSIGNMENT.ITEMS')) = 1;
  WR6: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\product_definition ||
       SELF\analytical_model_definition))) = 0;
  WR7: SIZEOF (QUERY (prpc <* USEDIN (SELF.formation.of_product,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_RELATED_PRODUCT_CATEGORY.' +
       'PRODUCTS') |
       prpc\product_category.name = 'simulation model')) >= 1;
END_ENTITY; -- analytical_model_definition
(*

EXPRESS specification:

*)
ENTITY analytical_model_make_from_relationship
  SUBTYPE OF (representation, representation_relationship);
UNIQUE
  UR1: SELF\representation_relationship.rep_1, SELF\representation_relationship.rep_2;
WHERE
  WR1: SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ANALYTICAL_MODEL'] *
       TYPEOF (SELF.rep_1)) = 1;
  WR2: SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ANALYTICAL_MODEL'] *
       TYPEOF (SELF.rep_2)) = 1;
  WR3: SIZEOF( QUERY(rr <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION_RELATIONSHIP.REP_1') |NOT(
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MAKE_FROM_MODEL_PORT_RELATIONSHIP' IN TYPEOF(rr.rep_2))))) = 0;
  WR4: SIZEOF( QUERY(rr <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION_RELATIONSHIP.REP_1') |NOT(
       (rr\representation_relationship.name = 'associated make from') AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MAKE_FROM_MODEL_PORT_RELATIONSHIP' IN TYPEOF(rr.rep_2))))) = 0;
  WR5: SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ANALYTICAL_MODEL'] *
       TYPEOF (SELF)) = 0;
  WR6: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\representation ||
       SELF\representation_relationship || 
       SELF\analytical_model_make_from_relationship))) = 0;
END_ENTITY; -- analytical_model_make_from_relationship 
(* 

EXPRESS specification:

*)
ENTITY analytical_model_port
  SUBTYPE OF (representation);
WHERE
  WR1: SIZEOF (QUERY (it <* SELF.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESCRIPTIVE_REPRESENTATION_ITEM'
       IN TYPEOF (it)) AND
       (it\representation_item.name = 'distributed property') AND
       (it\descriptive_representation_item.description IN 
       ['true', 'false']))) = 1;
  WR2: SIZEOF (QUERY (it <* SELF.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESCRIPTIVE_REPRESENTATION_ITEM'
       IN TYPEOF (it)) AND
       (it\representation_item.name = 'nominal signal flow direction') AND
       (it\descriptive_representation_item.description IN 
       ['input direction',
       'output direction', 'bidirectional', 'unknown direction',
       'not applicable']))) <= 1;
  WR3: SIZEOF (QUERY (it <* SELF.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESCRIPTIVE_REPRESENTATION_ITEM'
       IN TYPEOF (it)) AND
       (it\representation_item.name = 'port type') AND
       (it\descriptive_representation_item.description IN 
       ['string property type',
       'logical property type', 'physical property type',
       'boolean property type']))) = 1;
  WR4: SIZEOF (QUERY (am <* QUERY (rr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'REPRESENTATION_RELATIONSHIP.REP_2') |
       rr\representation_relationship.name = 'access mechanism') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ANALYTICAL_MODEL' IN 
       TYPEOF (am.rep_1))) = 1;
  WR5: SIZEOF (QUERY (aga <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_GROUP_ASSIGNMENT.ITEMS') |
       aga.assigned_group\group.name IN ['scalar port', 'digital scalar port', 
       'vector port', 'digital vector port', 
       'digital analytical model port'])) <= 1;
  WR6: (NOT (SIZEOF (QUERY (aga <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_GROUP_ASSIGNMENT.ITEMS') |
       aga.assigned_group\group.name IN ['vector port', 'digital vector port'])) 
       = 1)) OR
       (SIZEOF (QUERY (it <* SELF.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM'
       IN TYPEOF (it)) AND
       (it\representation_item.name = 'size') AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COUNT_MEASURE' IN
       TYPEOF (it\measure_with_unit.value_component)) AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'CONTEXT_DEPENDENT_UNIT' IN
       TYPEOF (it\measure_with_unit.unit_component)))) = 1);
  WR7: (NOT (SIZEOF (QUERY (aga <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_GROUP_ASSIGNMENT.ITEMS') |
       aga.assigned_group\group.name IN ['digital scalar port', 
       'digital vector port', 'digital analytical model port'])) = 1)) OR
       (SIZEOF (QUERY (it <* SELF.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESCRIPTIVE_REPRESENTATION_ITEM'
       IN TYPEOF (it)) AND
       (it\representation_item.name = 'nominal signal flow direction') AND
    (it\descriptive_representation_item.description IN ['input direction',
       'output direction', 'bidirectional', 'unknown direction']))) = 1);
END_ENTITY; -- analytical_model_port
(*

EXPRESS specification:

*)
ENTITY analytical_representation
  SUBTYPE OF (representation);
UNIQUE
  UR1: SELF\representation.name;
WHERE
  WR1: SIZEOF (QUERY (rr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION_RELATIONSHIP.REP_1') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PARAMETER_ASSIGNMENT_REPRESENTATION' IN
       TYPEOF (rr.rep_2))) >= 1;
  WR2: SIZEOF (QUERY (rr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'REPRESENTATION_RELATIONSHIP.REP_2') | 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ANALYTICAL_MODEL' IN TYPEOF (rr.rep_1))) = 1;
END_ENTITY; -- analytical_representation
(*

EXPRESS specification:

*)
ENTITY angular_dimension_with_orientation
  SUBTYPE OF (dimensional_location);
WHERE
    wr1: SELF\shape_aspect_relationship.description = 'angular';
END_ENTITY; -- angular_dimension_with_orientation
(*

EXPRESS specification:

*)
ENTITY angularity_tolerance
  SUBTYPE OF (geometric_tolerance_with_specified_datum_system);
WHERE
  WR1: SELF\geometric_tolerance.name = 'angularity';
END_ENTITY; -- angularity_tolerance
(*

EXPRESS specification:

*)
ENTITY applied_action_assignment
  SUBTYPE OF (action_assignment);
    items : SET [1:?] OF action_assigned_item;
END_ENTITY; -- applied_action_assignment
(*

EXPRESS specification:

*)
ENTITY applied_approval_assignment 
 SUBTYPE OF (approval_assignment); 
 items : SET [1:?] OF approval_assigned_item; 
END_ENTITY; -- applied_approval_assignment
(*

EXPRESS specification:

*)
ENTITY applied_certification_assignment
  SUBTYPE OF (certification_assignment);
  items : SET [1:?] OF certification_assigned_item;
END_ENTITY; -- applied_certification_assignment
(*

EXPRESS specification:

*)
ENTITY applied_classification_assignment
   SUBTYPE OF (group_assignment);
     items : SET [1:?] OF classification_assigned_item;
END_ENTITY; -- applied_classification_assignment
(*

EXPRESS specification:

*)
ENTITY applied_contract_assignment
  SUBTYPE OF (contract_assignment);
  items : SET [1:?] OF contract_assigned_item;
END_ENTITY; -- applied_contract_assignment
(*

EXPRESS specification:

*)
ENTITY applied_date_and_time_assignment
  SUBTYPE OF (date_and_time_assignment);
  items : SET [1:?] OF date_and_time_assigned_item;
WHERE
  WR1: applied_date_time_correlation
       (SELF,'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN');
  WR2: (NOT (SELF.role\date_time_role.name = 'participant date and time')) OR
       (SIZEOF (QUERY (ra <* QUERY (it <* SELF.items |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'RULE_ACTION' IN
       TYPEOF (it)) |
       NOT (SIZEOF (USEDIN (ra,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_PERSON_AND_ORGANIZATION_ASSIGNMENT.ITEMS')) = 1))) = 0);
END_ENTITY; -- applied_date_and_time_assignment
(*

EXPRESS specification:

*)
ENTITY applied_date_assignment
  SUBTYPE OF (date_assignment);
  items : SET [1:?] OF date_assigned_item;
WHERE
  WR1: applied_date_correlation (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN');
END_ENTITY; -- applied_date_assignment
(*

EXPRESS specification:

*)
ENTITY applied_document_reference
  SUBTYPE OF (document_reference);
  items : SET [1:?] OF document_assigned_item;
END_ENTITY; -- applied_document_reference
(*

EXPRESS specification:

*)
ENTITY applied_group_assignment
 SUBTYPE OF (group_assignment);
     items : SET [1:?] OF group_assigned_item;
END_ENTITY; -- applied_group_assignment
(*

EXPRESS specification:

*)
ENTITY applied_organization_assignment
  SUBTYPE OF (organization_assignment);
  items : SET [1:?] OF organization_assigned_item;
END_ENTITY; -- applied_organization_assignment
(*

EXPRESS specification:

*)
ENTITY applied_person_and_organization_assignment
  SUBTYPE OF (person_and_organization_assignment);
  items : SET [1:?] OF person_and_organization_assigned_item;
END_ENTITY; -- applied_person_and_organization_assignment
(*

EXPRESS specification:

*)
ENTITY applied_person_assignment
 SUBTYPE OF (person_assignment);
     items : SET [1:?] OF person_assigned_item;
END_ENTITY; -- applied_person_assignment
(*

EXPRESS specification:

*)
ENTITY applied_promissory_usage_in_product_model_assignment
 SUBTYPE OF (group_assignment);
     items : SET [1:?] OF promissory_usage_in_product_model_assigned_item;
WHERE
 WR1: SIZEOF(QUERY(pm <* items |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_CONCEPT' IN TYPEOF(pm)
        )) = 1;
 WR2: SIZEOF(QUERY(pd <* items |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION' IN TYPEOF(pd)
        )) = 1;
 WR3: SIZEOF(items) = 2;
 WR4: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROMISSORY_USAGE_IN_PRODUCT_MODEL' IN TYPEOF(SELF\group_assignment.assigned_group);
 WR5: SIZEOF(USEDIN(SELF,
      'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_SECURITY_CLASSIFICATION_ASSIGNMENT.ITEMS')) <= 1;
END_ENTITY; -- applied_promissory_usage_in_product_model_assignment
(*

EXPRESS specification:

*)
ENTITY applied_security_classification_assignment
  SUBTYPE OF (security_classification_assignment);
  items : SET [1:?] OF security_classification_assigned_item;
END_ENTITY; -- applied_security_classification_assignment
(*

EXPRESS specification:

*)
ENTITY array_placement_group_component_definition
  SUPERTYPE OF (ONEOF(linear_array_placement_group_component_definition,
                      rectangular_array_placement_group_component_definition))
  SUBTYPE OF (assembly_group_component_definition);
END_ENTITY; -- array_placement_group_component_definition
(*

EXPRESS specification:

*)
ENTITY array_placement_group_component_shape_aspect
  SUPERTYPE OF (ONEOF(linear_array_placement_group_component_shape_aspect,
                      rectangular_array_placement_group_component_shape_aspect))
  SUBTYPE OF (assembly_group_component_shape_aspect);
END_ENTITY; -- array_placement_group_component_shape_aspect
(*

EXPRESS specification:

*)
ENTITY assembly_bond_definition
  SUBTYPE OF (shape_aspect);
UNIQUE
  UR1: SELF\shape_aspect.name;
WHERE
  WR1: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MATERIAL_DESIGNATION.DEFINITIONS')) = 1;
  WR2: SIZEOF (QUERY (aga <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_GROUP_ASSIGNMENT.ITEMS') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'BOND_CATEGORY' IN
       TYPEOF (aga.assigned_group))) = 1;
  WR3: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name  = 'bonded feature 1' ))  = 1;
  WR4: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name  = 'bonded feature 2' ))  = 1;
  WR5: (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PRODUCT_DEFINITION' IN TYPEOF (SELF.of_shape.definition))
       AND
       (SIZEOF (QUERY (prpc <* USEDIN (SELF.of_shape.definition.formation.of_product,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_RELATED_PRODUCT_CATEGORY.' +
       'PRODUCTS') |
       prpc\product_category.name = 'technology specific model')) >= 1));
END_ENTITY; -- assembly_bond_definition
(*

EXPRESS specification:

*)
ENTITY assembly_definition
 SUBTYPE OF (physical_unit);
WHERE
  WR1: EXISTS(SELF\product_definition.name);
  WR2: NOT EXISTS(SELF\product_definition.name) OR 
        (SELF\product_definition.name = 'assembly module');
  WR3: (NOT (SELF.frame_of_reference.name = 'physical design')) OR
       (SIZEOF (QUERY (du <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.' +
       'RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'design usage') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_DEFINITION', 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_ASSEMBLY_DEFINITION', 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_ASSEMBLY_DEFINITION'] *
       TYPEOF (du.relating_product_definition)) = 1) AND
       (du.relating_product_definition.frame_of_reference.name = 
       'physical design usage') AND
       (du.relating_product_definition\product_definition.name = 'assembly module')
        )) = 1);
  WR4: (NOT (SELF.frame_of_reference.name = 'physical design usage')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_MODULE_TERMINAL' IN
       TYPEOF (sa)) AND
       (sa\shape_aspect.description = 'pca terminal'))) >= 2))) = 0);
END_ENTITY; -- assembly_definition
(*

EXPRESS specification:

*)
ENTITY assembly_group_component_definition
  SUBTYPE OF (component_definition);
WHERE
  WR1: (SIZEOF (QUERY (gc <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'group component') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN
       TYPEOF (gc.related_product_definition)))) >= 1)  OR
       (SIZEOF (QUERY(agcsa <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_GROUP_COMPONENT_SHAPE_ASPECT' IN TYPEOF (agcsa)))) = 0);
  WR2: (SIZEOF (QUERY(aj <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_JOINT' IN TYPEOF (aj)))) = 0) OR
       (SIZEOF (QUERY(aj <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_JOINT' IN TYPEOF (aj)) AND
       (SIZEOF (QUERY( acu <* USEDIN (aj\shape_aspect_relationship.relating_shape_aspect,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_COMPONENT_USAGE' IN TYPEOF (acu))
       AND (acu\product_definition_relationship.relating_product_definition = SELF)
       )) >= 1))) >= 1);
  WR3: (SIZEOF (QUERY(aj <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_JOINT' IN TYPEOF (aj)))) = 0) OR
       (SIZEOF (QUERY(aj <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_JOINT' IN TYPEOF (aj))AND
       (SIZEOF (QUERY( acu <* USEDIN (aj\
        shape_aspect_relationship.related_shape_aspect,
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_COMPONENT_USAGE' IN TYPEOF (acu))
        AND (acu\product_definition_relationship.relating_product_definition = SELF)
        )) = 0))) = 0);
  WR4: (SIZEOF (QUERY(aj <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_JOINT' IN TYPEOF (aj)))) = 0) OR
       (SIZEOF (QUERY(aj <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_JOINT' IN TYPEOF (aj)) AND
       (SIZEOF (QUERY( cl <* USEDIN (aj\
        shape_aspect_relationship.related_shape_aspect.of_shape.definition,
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'REPRESENTATION.ITEMS') |
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'COMPONENT_LOCATION' IN TYPEOF (cl))
        AND (aj IN cl\representation.items))) = 0))) = 0);
END_ENTITY; -- assembly_group_component_definition
(*

EXPRESS specification:

*)
ENTITY assembly_group_component_definition_placement_link
  SUBTYPE OF (product_definition,product_definition_relationship);
WHERE
  WR1: SELF\product_definition_relationship.related_product_definition :<>:
       SELF\product_definition_relationship.relating_product_definition;
  WR2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN
       TYPEOF (SELF\product_definition_relationship.related_product_definition);
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN
       TYPEOF (SELF\product_definition_relationship.relating_product_definition);
  WR4: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\product_definition ||
       SELF\product_definition_relationship ||
       SELF\assembly_group_component_definition_placement_link)) = 0;
  WR5: SELF\product_definition.name = '';
  WR6: SELF\product_definition_relationship.name = '';
  WR7: SIZEOF(USEDIN(SELF, 
             'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
             'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')) = 1;
END_ENTITY; -- assembly_group_component_definition_placement_link 
(* 

EXPRESS specification:

*)
ENTITY assembly_group_component_shape_aspect
  SUBTYPE OF (component_shape_aspect);
WHERE
  WR1: (SIZEOF (QUERY (gc <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'group component') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_SHAPE_ASPECT' IN
       TYPEOF (gc.related_shape_aspect))))
       >= 1);
END_ENTITY; -- assembly_group_component_shape_aspect
(*

EXPRESS specification:

*)
ENTITY assembly_group_component_shape_aspect_placement_link
  SUBTYPE OF (shape_aspect,shape_aspect_relationship);
WHERE
  WR1: SELF\shape_aspect_relationship.related_shape_aspect :<>:
       SELF\shape_aspect_relationship.relating_shape_aspect;
  WR2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_SHAPE_ASPECT' IN
       TYPEOF (SELF\shape_aspect_relationship.related_shape_aspect);
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_SHAPE_ASPECT' IN
       TYPEOF (SELF\shape_aspect_relationship.relating_shape_aspect);
  WR4: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\shape_aspect_relationship ||
       SELF\assembly_group_component_shape_aspect_placement_link)) = 0;
  WR5: SELF\shape_aspect.name = '';
  WR6: SELF\shape_aspect_relationship.name = '';
  WR7: SIZEOF(USEDIN(SELF, 
             'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
             'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')) = 1;
END_ENTITY; -- assembly_group_component_shape_aspect_placement_link 
(* 

EXPRESS specification:

*)
ENTITY assembly_joint
  SUBTYPE OF (shape_aspect_relationship, shape_aspect);
WHERE
  WR1: (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL' IN
       TYPEOF (SELF.relating_shape_aspect)) AND
       (SELF.relating_shape_aspect\shape_aspect.description IN 
       ['assembly module component terminal', 
       'bare die component terminal',
       'interconnect component join terminal', 
       'interconnect module component terminal',  
       'package terminal occurrence', 
       'packaged component join terminal'])) OR
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTERCONNECT_MODULE_COMPONENT_SURFACE_FEATURE' IN
       TYPEOF (SELF.relating_shape_aspect)) OR
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_INTERFACE_TERMINAL' IN
       TYPEOF (SELF.relating_shape_aspect)) OR
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_MOUNTING_FEATURE' IN
       TYPEOF (SELF.relating_shape_aspect));
  WR2: (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL' IN
       TYPEOF (SELF.related_shape_aspect)) AND
       (SELF.related_shape_aspect\shape_aspect.description IN 
       ['assembly module component terminal', 
       'bare die component terminal', 
       'interconnect component join terminal', 
       'interconnect module component terminal',  
       'package terminal occurrence', 
       'packaged component join terminal'])) OR
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTERCONNECT_MODULE_COMPONENT_SURFACE_FEATURE' IN
       TYPEOF (SELF.relating_shape_aspect)) OR
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_INTERFACE_TERMINAL' IN
       TYPEOF (SELF.related_shape_aspect)) OR
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_MOUNTING_FEATURE' IN
       TYPEOF (SELF.relating_shape_aspect));
  WR3: (NOT (SELF\shape_aspect_relationship.name = 
       'assembled with bonding')) OR
       (SIZEOF (QUERY (ddu <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'default definition usage') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_BOND_DEFINITION' IN
       TYPEOF (ddu.relating_shape_aspect))) = 1);
  WR4: (NOT (SELF\shape_aspect_relationship.name = 
       'assembled with bonding')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       (pdr.used_representation\representation.name = 'bond assembly position') AND
       (SIZEOF (QUERY (it <* pdr.used_representation.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MAPPED_ITEM' IN TYPEOF (it)) AND
       (it\representation_item.name = 'assembly position'))) = 1))) = 1)) <= 1);
  WR5: (NOT (SELF\shape_aspect_relationship.name = 
       'assembled with fasteners')) OR
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_GROUP_COMPONENT_DEFINITION' IN
       TYPEOF (SELF.of_shape.definition));
  WR6: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_GROUP_COMPONENT_DEFINITION' IN
       TYPEOF (SELF.of_shape.definition)) OR
       is_assembly_module_design(SELF.of_shape.definition); 
  WR7: (NOT (SELF\shape_aspect_relationship.name =
       'assembled with bonding')) OR
       (SIZEOF (QUERY (ddu <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'default definition usage') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_BOND_DEFINITION' IN
       TYPEOF (ddu.relating_shape_aspect)) AND
       (SIZEOF (QUERY (sar <* USEDIN (ddu.relating_shape_aspect,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name  = 'bonded feature 1' ))  = 1)
       AND (SIZEOF (QUERY (sar <* USEDIN (ddu.relating_shape_aspect,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name  = 'bonded feature 1' ))  = 1)
       )) = 1);
  WR8: acyclic_shape_aspect_relationship(SELF,
       [SELF\shape_aspect_relationship.related_shape_aspect],
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.'+
       'ASSEMBLY_JOINT');
END_ENTITY; -- assembly_joint
(*

EXPRESS specification:

*)
ENTITY assembly_module_interface_terminal
  SUBTYPE OF (assembly_module_terminal);
END_ENTITY; -- assembly_module_interface_terminal
(*

EXPRESS specification:

*)
ENTITY assembly_module_join_terminal
  SUBTYPE OF (assembly_module_terminal);
END_ENTITY; -- assembly_module_join_terminal
(*

EXPRESS specification:

*)
ENTITY assembly_module_macro_component_join_terminal
  SUBTYPE OF (component_terminal);
WHERE
  WR1: NOT (SELF\shape_aspect.description IN 
      ['bare die component terminal', 
       'component termination passage join terminal', 
       'conductive interconnect element terminal', 
       'interconnect component join terminal', 
       'interconnect module component terminal', 'land join terminal', 
       'minimally defined component terminal',
       'non functional land join terminal', 
       'packaged component join terminal', 
       'printed component join terminal', 'package terminal occurrence',
       'via terminal']);
END_ENTITY; -- assembly_module_macro_component_join_terminal
(*

EXPRESS specification:

*)
ENTITY assembly_module_terminal
  SUPERTYPE OF (ONEOF(
           assembly_module_interface_terminal, 
           assembly_module_join_terminal))
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: EXISTS(SELF.of_shape.definition\product_definition.name);
  WR2: NOT EXISTS(SELF.of_shape.definition\product_definition.name) OR
      (SELF.of_shape.definition\product_definition.name = 'assembly module');
  WR3: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_REPRESENTATION' IN
       TYPEOF (pdr.used_representation))) >= 1))) = 0;
  WR4: SIZEOF (QUERY (mct <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'member connected terminal') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PART_CONNECTED_TERMINALS_DEFINITION'
       IN TYPEOF (mct.relating_shape_aspect))) <= 1;
  WR5: (NOT (SELF\shape_aspect.description = 'pca terminal')) OR
       ((SIZEOF(TYPEOF (SELF.of_shape.definition) *
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_DEFINITION',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_ASSEMBLY_DEFINITION',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_ASSEMBLY_DEFINITION']) >=1)
       AND (SELF.of_shape.definition\product_definition.
       frame_of_reference.name = 'physical design usage'));
  WR6: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar.related_shape_aspect\shape_aspect.description = 'connection zone')) = 1;
  WR7: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar.related_shape_aspect\shape_aspect.description = 'interface terminal')) <= 1;
END_ENTITY; -- assembly_module_terminal
(*

EXPRESS specification:

*)
ENTITY assembly_module_usage_view_connector_relationship
  SUBTYPE OF (mapped_item);
WHERE
  WR1: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'AXIS2_PLACEMENT_3D' IN TYPEOF (SELF\mapped_item.mapping_target);
  wr2: SELF\mapped_item.mapping_source.mapped_representation\representation.name =
       '3d bound volume shape';
  wr3:  SIZEOF (QUERY (pdr <* USEDIN 
       ( SELF\mapped_item.mapping_source.mapped_representation,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_CONNECTOR',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PACKAGED_CONNECTOR',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_PACKAGED_CONNECTOR'] * 
        TYPEOF (pdr.definition.definition) ) = 1) )) = 1;
  wr4:  SIZEOF (QUERY (r <* USEDIN ( SELF\representation_item,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION.ITEMS') |
        SIZEOF (QUERY (pdr <* USEDIN (r,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION' IN TYPEOF(pdr.definition.definition))
         AND
        (pdr.definition.definition.
          frame_of_reference\application_context_element.name = 
          'physical design usage')
          AND
          (pdr.definition.definition\product_definition.
          name = 'assembly module')
           )) = 1 )) = 1;
END_ENTITY; -- assembly_module_usage_view_connector_relationship
(*

EXPRESS specification:

*)
ENTITY auxiliary_characteristic_dimension_representation
 SUBTYPE OF (dimensional_characteristic_representation);
END_ENTITY; -- auxiliary_characteristic_dimension_representation
(*

EXPRESS specification:

*)
ENTITY bare_die
 SUBTYPE OF (physical_unit);
WHERE
  WR1: SIZEOF (QUERY (ifdu <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.' +
       'RELATED_PRODUCT_DEFINITION') |
       pdr\property_definition_relationship.name = 'implemented function') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FUNCTIONAL_UNIT' IN 
       TYPEOF (ifdu.relating_product_definition)) AND
       (ifdu.relating_product_definition.frame_of_reference.name = 
       'functional design usage'))) = 1;
  WR2: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (dut <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION') |
       pdr\property_definition_relationship.name = 'device unit technology') |
       dut.relating_property_definition\property_definition.name = 
       'unit technology')) = 1)) = 1;
  WR3: SIZEOF (QUERY (pd <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'BARE_DIE_TERMINAL' IN 
       TYPEOF (sa))) >= 2))) = 0;
END_ENTITY; -- bare_die
(*

EXPRESS specification:

*)
ENTITY bare_die_bottom_surface
 SUBTYPE OF (bare_die_surface);
WHERE
  WR1: SIZEOF (TYPEOF (SELF.of_shape.definition) *
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'BARE_DIE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_BARE_DIE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_BARE_DIE']) = 1;
  WR2: SELF\shape_aspect.product_definitional;
  WR3: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\bare_die_bottom_surface ||
       SELF\part_mounting_feature ||
       SELF\bare_die_surface)) = 0;
END_ENTITY; -- bare_die_bottom_surface
(*

EXPRESS specification:

*)
ENTITY bare_die_edge_segment_surface
  SUBTYPE OF (shape_aspect, shape_aspect_relationship);
WHERE
  wr1: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_SEGMENT_VERTEX' IN
       TYPEOF (SELF\shape_aspect_relationship.related_shape_aspect);
  wr2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_SEGMENT_VERTEX' IN
       TYPEOF (SELF\shape_aspect_relationship.relating_shape_aspect);
  wr3: SELF\shape_aspect_relationship.relating_shape_aspect :<>:
       SELF\shape_aspect_relationship.related_shape_aspect;
  WR4: SIZEOF (QUERY (ce <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'composed surface') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'BARE_DIE_EDGE_SURFACE' IN TYPEOF
       (ce.relating_shape_aspect) ))) = 1;
  WR5: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\shape_aspect_relationship ||
       SELF\bare_die_edge_segment_surface)) = 0;
END_ENTITY; -- bare_die_edge_segment_surface
(*

EXPRESS specification:

*)
ENTITY bare_die_edge_surface
 SUBTYPE OF (bare_die_surface);
WHERE
  WR1: SIZEOF (TYPEOF (SELF.of_shape.definition) *
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'BARE_DIE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_BARE_DIE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_BARE_DIE']) = 1;
  WR2: SELF\shape_aspect.product_definitional;
  WR3: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\part_mounting_feature ||
       SELF\bare_die_edge_surface ||
       SELF\bare_die_surface)) = 0;
END_ENTITY; -- bare_die_edge_surface
(*

EXPRESS specification:

*)
ENTITY bare_die_surface
 ABSTRACT SUPERTYPE OF (ONEOF( bare_die_bottom_surface, 
                         bare_die_top_surface, 
                        bare_die_edge_surface))
 SUBTYPE OF (part_mounting_feature);
WHERE
  WR1: SIZEOF (TYPEOF (SELF.of_shape.definition) *
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'BARE_DIE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_BARE_DIE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_BARE_DIE']) = 1;
  WR2: SELF\shape_aspect.product_definitional;
END_ENTITY; -- bare_die_surface
(*

EXPRESS specification:

*)
ENTITY bare_die_terminal
  SUBTYPE OF (minimally_defined_bare_die_terminal);
WHERE
  WR1: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'BARE_DIE' IN 
       TYPEOF (SELF.of_shape.definition);
  WR2: SIZEOF (QUERY (eca <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'external connection area') |
       eca.related_shape_aspect\shape_aspect.description = 'connection zone')) = 1;
  WR3: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MATERIAL_DESIGNATION.DEFINITIONS')) = 1;
  WR4: SIZEOF (QUERY (eca <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'seating plane zone') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'CONNECTION_ZONE_INTERFACE_PLANE_RELATIONSHIP' IN 
       TYPEOF (eca.related_shape_aspect))) <= 1;
END_ENTITY; -- bare_die_terminal
(*

EXPRESS specification:

*)
ENTITY bare_die_top_surface
 SUBTYPE OF (bare_die_surface);
WHERE
  WR1: SIZEOF (TYPEOF (SELF.of_shape.definition) *
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'BARE_DIE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_BARE_DIE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_BARE_DIE']) = 1;
  WR2: SELF\shape_aspect.product_definitional;
  WR3: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\part_mounting_feature ||
       SELF\bare_die_top_surface ||
       SELF\bare_die_surface)) = 0;
END_ENTITY; -- bare_die_top_surface
(*

EXPRESS specification:

*)
ENTITY bond_category
  SUBTYPE OF (group, external_definition);
WHERE
  WR1: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_DOCUMENT_REFERENCE.ITEMS')) = 1;
END_ENTITY; -- bond_category
(*

EXPRESS specification:

*)
ENTITY bus_element_link
  SUBTYPE OF (product_definition,product_definition_relationship);
UNIQUE
  UR1: SELF\product_definition_relationship.related_product_definition,
       SELF\product_definition_relationship.relating_product_definition;
WHERE
  WR1: SELF\product_definition_relationship.related_product_definition :<>:
       SELF\product_definition_relationship.relating_product_definition;
  WR2: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'BUS_STRUCTURAL_DEFINITION' IN
       TYPEOF (SELF\product_definition_relationship.related_product_definition)) OR
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'NETWORK_NODE_DEFINITION' IN
       TYPEOF (SELF\product_definition_relationship.related_product_definition));
  WR3: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'BUS_STRUCTURAL_DEFINITION' IN
       TYPEOF (SELF\product_definition_relationship.relating_product_definition)) OR
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'NETWORK_NODE_DEFINITION' IN
       TYPEOF (SELF\product_definition_relationship.relating_product_definition));
  WR4: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\product_definition ||
       SELF\product_definition_relationship ||
       SELF\bus_element_link)) = 0;
  WR5: NOT EXISTS(SELF\product_definition.name) OR 
        (SELF\product_definition.name = '');
  WR6: SELF\product_definition_relationship.name = '';
  WR7: SIZEOF(USEDIN(SELF, 
             'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
             'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')) >= 1;
END_ENTITY; -- bus_element_link 
(* 

EXPRESS specification:

*)
ENTITY bus_structural_definition
 SUBTYPE OF (product_definition);
WHERE
  WR1: SIZEOF (QUERY (bce <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'bus composition') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'BUS_ELEMENT_LINK' IN
       TYPEOF (bce.related_product_definition))) >= 1;
  WR2: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (pdr <* USEDIN (pd, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATING_PROPERTY_DEFINITION') |
       pdr\property_definition_relationship.name = 
       'functional unit network terminal definition bus assignment')) 
       <= 1)) <= 1;
  WR3: consistent_bus_structural_definition(bag_to_set(QUERY( pdr <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'BUS_ELEMENT_LINK' IN TYPEOF(pdr.related_product_definition))));
END_ENTITY; -- bus_structural_definition
(*

EXPRESS specification:

*)
ENTITY cable_component
  SUBTYPE OF (component_definition);
WHERE
  WR1: SIZEOF (QUERY (ip <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'instantiated part') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_UNIT'] *
       TYPEOF (ip.relating_product_definition)) = 1) AND
       (ip.relating_product_definition.frame_of_reference.name =
       'physical design usage'))) = 1;
  WR2: SELF\product_definition.description :<>: 'laminate component';
END_ENTITY; -- cable_component
(*

EXPRESS specification:

*)
ENTITY capacitance_measure_with_unit
 SUBTYPE OF (measure_with_unit);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\measure_with_unit ||
       SELF\capacitance_measure_with_unit))) = 0;
  WR2: SELF\measure_with_unit.unit_component\si_unit.name = farad;
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SI_UNIT' IN 
       TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY; -- capacitance_measure_with_unit
(*

EXPRESS specification:

*)
ENTITY change
 SUBTYPE OF (action_assignment);
     items : SET [1:?] OF work_item;
WHERE
  WR1: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DIRECTED_ACTION' 
       IN TYPEOF (SELF.assigned_action);
  WR2: unique_version_change_order (SELF.assigned_action, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN');

END_ENTITY; -- change
(*

EXPRESS specification:

*)
ENTITY change_from_design_object_assignment
   SUBTYPE OF (action_assignment);
     items : SET [1:?] OF managed_design_object;
WHERE
   WR1: SIZEOF(QUERY(aa <* USEDIN(SELF\action_assignment.assigned_action,
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ACTION_ASSIGNMENT.ASSIGNED_ACTION')
        |'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
         'CHANGE_TO_DESIGN_OBJECT_ASSIGNMENT' IN TYPEOF(aa))) >= 1;
    END_ENTITY; -- change_from_design_object_assignment
(*

EXPRESS specification:

*)
ENTITY change_from_design_object_request_assignment
   SUBTYPE OF (action_request_assignment);
     items : SET [1:?] OF managed_design_object;
WHERE
   WR1: SIZEOF(QUERY(aa <*
        USEDIN(SELF\action_request_assignment.assigned_action_request,
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ACTION_REQUEST_ASSIGNMENT.ASSIGNED_ACTION_REQUEST')
        |'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
         'CHANGE_TO_DESIGN_OBJECT_REQUEST_ASSIGNMENT' IN TYPEOF(aa))) >= 1;

END_ENTITY; -- change_from_design_object_request_assignment
(*

EXPRESS specification:

*)
ENTITY change_request
  SUBTYPE OF (action_request_assignment);
  items : SET [1:?] OF change_request_item;
END_ENTITY; -- change_request
(*

EXPRESS specification:

*)
ENTITY change_to_design_object_assignment
   SUBTYPE OF (action_assignment);
     items : SET [1:?] OF managed_design_object;
WHERE
   WR1: SIZEOF(QUERY(aa <* USEDIN(SELF\action_assignment.assigned_action,
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ACTION_ASSIGNMENT.ASSIGNED_ACTION')
        |'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
         'CHANGE_FROM_DESIGN_OBJECT_ASSIGNMENT' IN TYPEOF(aa))) >= 1;
   WR2: SIZEOF(QUERY ( pdr <* SELF.items | 
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'PRODUCT_DEFINITION_RELATIONSHIP' IN TYPEOF(pdr)) AND
        (pdr\product_definition_relationship.name = 'design object change'))) = 1;
    
END_ENTITY; -- change_to_design_object_assignment
(*

EXPRESS specification:

*)
ENTITY change_to_design_object_request_assignment
   SUBTYPE OF (action_request_assignment);
     items : SET [1:?] OF managed_design_object;
WHERE
   WR1: SIZEOF(QUERY(aa <* 
        USEDIN(SELF\action_request_assignment.assigned_action_request,
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ACTION_REQUEST_ASSIGNMENT.ASSIGNED_ACTION_REQUEST')
        |'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
         'CHANGE_FROM_DESIGN_OBJECT_REQUEST_ASSIGNMENT' 
         IN TYPEOF(aa))) >= 1;
   WR2: SIZEOF(QUERY ( pdr <* SELF.items | 
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'PRODUCT_DEFINITION_RELATIONSHIP' IN TYPEOF(pdr)) AND
        (pdr\product_definition_relationship.name = 'design object change'))) = 1;
END_ENTITY; -- change_to_design_object_request_assignment
(*

EXPRESS specification:

*)
ENTITY characteristic_type
  SUBTYPE OF (group);
WHERE
  WR1: SELF\group.name IN [
       'string property',
       'logical property',
       'boolean property',
       'numeric property',
       'externally defined property',
       'compound characteristic'
        ];
END_ENTITY; -- characteristic_type
(*

EXPRESS specification:

*)
ENTITY characterized_product_category
  SUBTYPE OF (characterized_object,product_category);
WHERE
  WR1:  SIZEOF (QUERY (pd <* USEDIN (SELF,
   'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
   'PROPERTY_DEFINITION.DEFINITION') | 
   (pd\property_definition.description = 'product category values') AND
   (SIZEOF (QUERY (pdr <* USEDIN (pd,
   'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
   'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
   ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
   'PARAMETER_ASSIGNMENT_REPRESENTATION'
   IN TYPEOF (pdr.used_representation)))) >= 1 ))) <= 1;

  WR2:  SIZEOF (QUERY (pd <* USEDIN (SELF,
   'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
   'PROPERTY_DEFINITION.DEFINITION') | 
   ((pd\property_definition.description = 'product category parameters') AND
   (SIZEOF (QUERY (pdr <* USEDIN (pd,
   'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
   'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
   (SIZEOF (QUERY (ri <* pdr.used_representation.items
   | (NOT (SIZEOF (TYPEOF (ri) *
   ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MODEL_PARAMETER']) =1)) )) =0))) >= 1 )))) <= 1;

  WR3: SELF\characterized_object.name = SELF\product_category.name;

  WR4:  SIZEOF (USEDIN (SELF,
   'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
   'APPLIED_DOCUMENT_REFERENCE.ITEMS')) = 1; 

END_ENTITY; -- characterized_product_category
(*

EXPRESS specification:

*)
ENTITY circular_runout_tolerance
  SUBTYPE OF (geometric_tolerance_with_specified_datum_system);
WHERE
  WR1: SELF\geometric_tolerance.name = 'circular runout';
  WR2: NOT('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
           'MODIFIED_GEOMETRIC_TOLERANCE' IN TYPEOF(SELF));
  WR3: SIZEOF (QUERY (pdr <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATING_PROPERTY_DEFINITION') |
       (pdr\property_definition_relationship.name = 'referenced datum system definition')  AND  
       (pdr.related_property_definition\property_definition.description =
       'datum system property without material conditions'))) = 1;
END_ENTITY; -- circular_runout_tolerance
(*

EXPRESS specification:

*)
ENTITY component_definition
  SUPERTYPE OF (ONEOF (printed_component, packaged_component, routed_physical_component)
                ANDOR (thermal_component) ANDOR (cable_component))
  SUBTYPE OF (product_definition);
WHERE
  WR1: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sr_pdr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_REPRESENTATION'
       IN TYPEOF (pdr.used_representation)) |
       sr_pdr.used_representation\representation.name = 'planar projected shape')) 
       <= 1))) = 0;
  WR2: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sr_pdr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_REPRESENTATION'
       IN TYPEOF (pdr.used_representation)) |
       sr_pdr.used_representation\representation.name = '3d bound volume shape')) 
       <= 1))) = 0;
  WR3: (NOT (SELF\product_definition.description = 
                                         'bare die component')) OR
       (SIZEOF (QUERY (ip <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'instantiated part') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'BARE_DIE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_BARE_DIE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_BARE_DIE'] *
       TYPEOF (ip.relating_product_definition)) = 1) AND
       (ip.relating_product_definition.frame_of_reference.name =
       'physical design usage'))) = 1);
  WR4: NOT(is_assembly_module_occurrence(SELF))
       OR
       (SIZEOF (QUERY (ip <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'instantiated part') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_UNIT' IN
       TYPEOF (ip.relating_product_definition)) AND
       (ip.relating_product_definition.frame_of_reference.name =
       'physical design usage') AND
       (ip.relating_product_definition\product_definition.name = 
          'assembly module')
       )) = 1);
  WR5: NOT(is_assembly_module_occurrence(SELF))
       OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL' IN 
       TYPEOF (sa)) AND
       (sa\shape_aspect.description = 'assembly module component terminal'))) 
       >= 2)) >= 1);
  WR6: NOT(is_interconnect_module_occurrence(SELF))
       OR
       (SIZEOF (QUERY (ip <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'instantiated part') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_UNIT' IN
       TYPEOF (ip.relating_product_definition)) AND
       (ip.relating_product_definition.frame_of_reference.name =
       'physical design usage') AND
        (SELF\product_definition.name = 'interconnect module')
       )) = 1);
  WR7: (NOT (SELF\product_definition.description = 'mating connector')) OR
       ((('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'PRODUCT_DEFINITION_WITH_ASSOCIATED_DOCUMENTS' IN 
       TYPEOF (SELF)) AND
       (SIZEOF (QUERY (doc <* 
   SELF\product_definition_with_associated_documents.documentation_ids |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EE_SPECIFICATION' IN 
       TYPEOF (doc))) = 1)) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pt_occ <* QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       sa\shape_aspect.description = 'part template occurrence') |
       SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (pt_occ,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |  
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PART_TEMPLATE_DEFINITION' IN
       TYPEOF (it.relating_shape_aspect)) AND
       (it.relating_shape_aspect\shape_aspect.description = 
       'printed connector template'))) = 1)) = 1))) = 0) OR
       (SIZEOF (QUERY (ip <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'instantiated part') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_PART',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PACKAGED_PART',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_PACKAGED_PART'] *
       TYPEOF (ip.relating_product_definition)) = 1) AND
       (ip.relating_product_definition\product_definition.description =
       'packaged connector'))) = 1));
  WR8: (NOT (SELF\product_definition.description = 'mating connector')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       pdr.used_representation\representation.name  = 
       'mating connector placement')) = 1)) = 1);
 WR9: (NOT (SELF\product_definition.description = 'mating connector')) OR
       ((SIZEOF (QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION') | 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'NEXT_ASSEMBLY_USAGE_OCCURRENCE' IN TYPEOF(pdr))) = 0) AND
       (SIZEOF (QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') | 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'NEXT_ASSEMBLY_USAGE_OCCURRENCE' IN TYPEOF(pdr))) = 0));
 WR10: SIZEOF(QUERY(pdr <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
        NOT(NOT(pdr\product_definition_relationship.name = 'instantiated part')
        OR 
        (SELF.formation :=: 
        pdr.relating_product_definition.formation))))
        = 0;
 WR11: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sr_pdr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_REPRESENTATION'
       IN TYPEOF (pdr.used_representation)) |
       (sr_pdr.used_representation\representation.name = 
        'part template non planar 2d shape')
       OR
       (sr_pdr.used_representation\representation.name = 'non planar 2d shape')
       OR
       (sr_pdr.used_representation\representation.name = 
        'open shell based surface'))) 
       <= 1))) = 0;
 WR12: NOT(SELF.frame_of_reference.name = 'layout occurrence') OR
       ((SIZEOF (QUERY (prpc <* USEDIN (SELF.formation.of_product,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS') |
       prpc\product_category.name = 'template model')) >= 1) OR
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_GROUP_COMPONENT_DEFINITION' IN TYPEOF(SELF)));
 WR13: NOT((SELF.frame_of_reference.name = 'layout occurrence') 
          AND
       NOT('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_COMPONENT' IN TYPEOF(SELF))) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ((SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_SHAPE_ASPECT'] *
       TYPEOF (sa)) >= 1)) 
        )) = 1))) = 0);

 WR14: NOT(is_assembly_module_macro_occurrence(SELF))
       OR
       (SIZEOF (QUERY (ip <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'design definition') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_UNIT' IN
       TYPEOF (ip.relating_product_definition)) AND
       (ip.relating_product_definition.frame_of_reference.name =
       'physical design') AND
       (ip.relating_product_definition\product_definition.name = 
           'assembly module')
       )) = 1);
 WR15: NOT(is_interconnect_module_macro_occurrence(SELF))
        OR
       (SIZEOF (QUERY (ip <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'design definition') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_UNIT' IN
       TYPEOF (ip.relating_product_definition)) AND
       (ip.relating_product_definition.frame_of_reference.name =
       'physical design') AND
       (ip.relating_product_definition\product_definition.name = 
             'interconnect module')
        )) = 1);
 WR16: SIZEOF(QUERY(pdr <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
        ((pdr\product_definition_relationship.name = 'instantiated definition')
        AND
        (NOT(SELF.formation :=:
        pdr.relating_product_definition.formation)))))
        = 0;
 WR17: (NOT (SELF\product_definition.description =
                                         'routed interconnect component')) OR
       ((SIZEOF (QUERY (ip <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'instantiated part') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_UNIT'] *
       TYPEOF (ip.relating_product_definition)) = 1) AND
       (ip.relating_product_definition.frame_of_reference.name =
       'physical design usage'))) = 1) AND
       (SELF.frame_of_reference.name = 'physical occurrence'));
END_ENTITY; -- component_definition
(*

EXPRESS specification:

*)
ENTITY component_feature
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN
       TYPEOF (SELF.of_shape.definition);
  WR2: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated feature')) <= 1;
END_ENTITY; -- component_feature
(*

EXPRESS specification:

*)
ENTITY component_feature_relationship
  SUBTYPE OF (shape_aspect,shape_aspect_relationship);
WHERE
  WR1: SELF\shape_aspect_relationship.related_shape_aspect :<>:
       SELF\shape_aspect_relationship.relating_shape_aspect;
  WR4: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\shape_aspect_relationship ||
       SELF\component_feature_relationship)) = 0;
  WR5: SELF\shape_aspect.name = '';
  WR6: SELF\shape_aspect_relationship.name = '';
END_ENTITY; -- component_feature_relationship 
(* 

EXPRESS specification:

*)
ENTITY component_functional_terminal
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_FUNCTIONAL_UNIT' IN
       TYPEOF (SELF.of_shape.definition);
  WR2: SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated terminal') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FUNCTIONAL_UNIT_TERMINAL_DEFINITION'
       IN TYPEOF (it.relating_shape_aspect))) = 1;
  WR3: SIZEOF (QUERY (futba <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION') |
       pdr\property_definition_relationship.name = 'functional unit terminal bus assignment') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'BUS_STRUCTURAL_DEFINITION' IN 
       TYPEOF (futba.relating_property_definition.definition))) <= 1;
  WR4: SIZEOF (QUERY (futna <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION') |
       pdr\property_definition_relationship.name = 'functional unit terminal node assignment') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'NETWORK_NODE_DEFINITION' IN 
       TYPEOF (futna.relating_property_definition.definition))) <= 1;
END_ENTITY; -- component_functional_terminal
(*

EXPRESS specification:

*)
ENTITY component_functional_unit
  SUBTYPE OF (product_definition);
WHERE
  WR1: SELF.frame_of_reference.name = 'functional occurrence';
  WR2: SIZEOF (QUERY (pd <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_FUNCTIONAL_TERMINAL' IN
       TYPEOF (sa))) >= 1)) >= 1;
  WR3: SIZEOF (QUERY (ifu <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'instantiated functional unit') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FUNCTIONAL_UNIT' IN 
       TYPEOF (ifu.relating_product_definition))) = 1;
  WR4: SIZEOF (QUERY (nc <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'network composition') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FUNCTIONAL_UNIT' IN 
       TYPEOF (nc.relating_product_definition)) AND
       (nc.relating_product_definition.frame_of_reference.name =
       'functional network design'))) = 1;
END_ENTITY; -- component_functional_unit
(*

EXPRESS specification:

*)
ENTITY component_interface_terminal
 SUBTYPE OF (shape_aspect);
WHERE
  WR1: SELF\shape_aspect.description IN [
       'interconnect component interface terminal',
       'packaged connector component interface terminal'];
  WR2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN 
       TYPEOF (SELF.of_shape.definition);
  WR3: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated feature')) <= 1;
  WR4: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'design usage')) <= 1;
  WR5: (NOT (SELF\shape_aspect.description = 
       'packaged connector component interface terminal')) OR
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTERFACE_COMPONENT_DEFINITION' IN 
       TYPEOF (SELF.of_shape.definition));
  WR6: (NOT (SELF\shape_aspect.description = 
       'packaged connector component interface terminal')) OR
       (SELF.of_shape.definition\product_definition.
        frame_of_reference.name = 
       'physical occurrence');
  WR7: (NOT (SELF\shape_aspect.description = 
       'interconnect component interface terminal')) OR
       ((SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       (sar.related_shape_aspect\shape_aspect.description = 'connection zone'))) = 1)
       AND 
       NOT(SELF.of_shape.definition\product_definition.description 
       IN ['assembly module component', 'bare die component',
       'interconnect module component', 'laminate component',
       'packaged component']));
  WR8: (NOT (SELF\shape_aspect.description = 
       'packaged connector component interface terminal')) OR
       (SELF.product_definitional);
  WR9: (NOT (SELF\shape_aspect.description = 
       'packaged connector component interface terminal')) OR
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_COMPONENT' IN
       TYPEOF (SELF.of_shape.definition)) AND
       (SELF.of_shape.definition\product_definition.description = 
       'packaged connector component') AND
       (SELF.of_shape.definition\product_definition.
       frame_of_reference.name = 
       'physical occurrence'));
 WR10: (NOT (SELF\shape_aspect.description = 
       'packaged connector component interface terminal')) OR
       (SIZEOF (QUERY (i_f <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated feature') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_PART_TERMINAL' IN
       TYPEOF (i_f.relating_shape_aspect)) AND
       (i_f.relating_shape_aspect\shape_aspect.description =
       'interface terminal'))) = 1);
END_ENTITY; -- component_interface_terminal
(*

EXPRESS specification:

*)
ENTITY component_location
  SUBTYPE OF (representation);
WHERE
  WR1: SIZEOF (QUERY (it <* SELF.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESCRIPTIVE_REPRESENTATION_ITEM'
       IN TYPEOF (it)) AND
       (it\representation_item.name = 'placement fixed') AND 
       ((it\descriptive_representation_item.description = 'true') OR
       (it\descriptive_representation_item.description = 'false')))) = 1;
  WR2: SIZEOF (QUERY (it <* SELF.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESCRIPTIVE_REPRESENTATION_ITEM'
       IN TYPEOF (it)))) = 1;
  WR3: (NOT 
       (SELF.context_of_items\geometric_representation_context.
       coordinate_space_dimension
       = 2)) OR (SIZEOF (QUERY (it <* SELF.items |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'CARTESIAN_TRANSFORMATION_OPERATOR_2D' IN TYPEOF (it))) = 1);
  WR4: (NOT 
       (SELF.context_of_items\geometric_representation_context.
       coordinate_space_dimension
        = 3)) OR (SIZEOF (QUERY (it <* SELF.items |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'AXIS2_PLACEMENT_3D' IN TYPEOF (it))) = 1);
  WR5: SIZEOF (QUERY (it <* SELF.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MAPPED_ITEM'
       IN TYPEOF (it)) 
       )) = 1;
  WR6: NOT (SIZEOF (QUERY (it <* SELF.items |
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'CARTESIAN_TRANSFORMATION_OPERATOR_2D' IN TYPEOF (it))) = 1)
        OR
        (SIZEOF (QUERY (cto2d <* SELF.items |
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'CARTESIAN_TRANSFORMATION_OPERATOR_2D'
        IN TYPEOF (cto2d)) AND
        (SIZEOF (QUERY (mi <* USEDIN (cto2d,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MAPPED_ITEM.MAPPING_TARGET') | (
       (SIZEOF (QUERY (cl <* USEDIN (mi,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION.ITEMS') |(cl = SELF))) = 1)))) >= 1)
        )) = 1);
  WR7: NOT (SIZEOF (QUERY (it <* SELF.items |
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'AXIS2_PLACEMENT_3D' IN TYPEOF (it))) = 1)
      OR
       (SIZEOF (QUERY (cto2d <* SELF.items |
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'AXIS2_PLACEMENT_3D'
        IN TYPEOF (cto2d)) AND
        (SIZEOF (QUERY (mi <* USEDIN (cto2d,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MAPPED_ITEM.MAPPING_TARGET') | (
       (SIZEOF (QUERY (cl <* USEDIN (mi,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION.ITEMS') |(cl = SELF))) = 1)))) = 1)
        )) = 1);
  WR8:NOT((SELF.context_of_items\geometric_representation_context.coordinate_space_dimension
         = 2) AND 
          (SELF.context_of_items.context_type = 'component surface') AND
        (( SIZEOF (QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION') |
       (
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_JOINT' IN TYPEOF (pdr.definition.definition)) AND
       (pdr.name = 'mounting surface assembly joint') AND
       (pdr.definition.definition.relating_shape_aspect\shape_aspect.description =
         'interconnect module component surface feature') AND
       (SIZEOF(QUERY ( sar <* USEDIN (pdr.definition.definition.relating_shape_aspect,
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
        ((sar.relating_shape_aspect\shape_aspect.description =
         'interconnect module primary surface') OR
        (sar.relating_shape_aspect\shape_aspect.description =
         'interconnect module edge surface') OR
        (sar.relating_shape_aspect\shape_aspect.description =
         'interconnect module edge segment surface')))) = 1)
       )
       )) = 1)))
       OR
       (SIZEOF(QUERY (cto2d <* SELF.items |
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'CARTESIAN_TRANSFORMATION_OPERATOR_2D' IN TYPEOF (cto2d)) AND
      (cto2d_determinant_test(cto2d,1.0,0.001 )))) = 1);
  WR9:NOT((SELF.context_of_items\geometric_representation_context.coordinate_space_dimension
         = 2) AND 
          (SELF.context_of_items.context_type = 'component surface') AND
         (( SIZEOF (QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION') |
       (
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_JOINT' IN TYPEOF (pdr.definition.definition)) AND
       (pdr.name = 'mounting surface assembly joint') AND
       (pdr.definition.definition.relating_shape_aspect\shape_aspect.description =
         'interconnect module component surface feature') AND
       (SIZEOF(QUERY ( sar <* USEDIN (pdr.definition.definition.relating_shape_aspect,
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
        sar.relating_shape_aspect\shape_aspect.description =
         'interconnect module secondary surface')) = 1)
       ))) = 1)))
       OR
    (SIZEOF(QUERY( cto2d <* SELF.items |
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'CARTESIAN_TRANSFORMATION_OPERATOR_2D' IN TYPEOF (cto2d)) AND
      (cto2d_determinant_test(cto2d,-1.0,0.001 )))) = 1);
  WR10: (NOT(is_laminate_component_location(SELF))) OR
      (SIZEOF(QUERY( pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_JOINT' IN TYPEOF (pdr.definition.definition)) AND
      (pdr.definition.definition.relating_shape_aspect\shape_aspect.description =
        'interconnect module component surface feature'))) = 0);
  WR11: (NOT(is_laminate_component_location(SELF) AND
         (SELF.context_of_items\geometric_representation_context.coordinate_space_dimension
         = 2)))
         OR
         (SIZEOF(QUERY (cto2d <* SELF.items |
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'CARTESIAN_TRANSFORMATION_OPERATOR_2D' IN TYPEOF (cto2d)) AND
      (cto2d_determinant_test(cto2d,1.0,0.001 )))) = 1);
  WR12: SIZEOF(QUERY( pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'SHAPE_ASPECT' IN TYPEOF (pdr.definition.definition)) AND
       (pdr.definition.definition\shape_aspect.description =
        'interconnect module component surface feature'))) = 0;
  WR13: (NOT((SELF.context_of_items\geometric_representation_context.
        coordinate_space_dimension = 2) AND
        (SELF.context_of_items.context_type = 'component stacked')))
        OR 
      (SIZEOF(QUERY( pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_JOINT' IN TYPEOF (pdr.definition.definition)) AND
      (pdr.definition.definition.relating_shape_aspect\shape_aspect.description =
        'interconnect module component surface feature'))) = 0);
 WR14: NOT((SELF.context_of_items\geometric_representation_context.coordinate_space_dimension
         = 2)
          AND
         (SELF.context_of_items.context_type = 'component edge'))
       OR
        ((NOT(is_laminate_component_location(SELF)))
          AND
       (( SIZEOF (QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION') |
       (
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_JOINT' IN TYPEOF (pdr.definition.definition)) AND
       (pdr.name = 'reference terminal assembly joint') AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'COMPONENT_TERMINAL' IN 
                      TYPEOF (pdr.definition.definition.related_shape_aspect)) 
         AND
       (pdr.definition.definition.related_shape_aspect\shape_aspect.description IN
       ['packaged component join terminal',
       'package terminal occurrence'])
         AND
       (SIZEOF(QUERY ( sar <* USEDIN 
                          (pdr.definition.definition.related_shape_aspect,
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
        (sar\shape_aspect_relationship.name = 'instantiated feature')
           AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'PRIMARY_REFERENCE_TERMINAL' IN TYPEOF (sar.relating_shape_aspect))
         )) = 1)
         AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'COMPONENT_DEFINITION' IN
         TYPEOF (pdr.definition.definition.related_shape_aspect.of_shape.definition))
         AND
       (component_definition_located_by_component_location(SELF) =
                 pdr.definition.definition.related_shape_aspect.of_shape.definition) 
       ))) = 1))
         AND
       (( SIZEOF (QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION') |
       (
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_JOINT' IN TYPEOF (pdr.definition.definition)) AND
       (pdr.name = 'mounting surface assembly joint') AND
       (pdr.definition.definition.relating_shape_aspect\shape_aspect.description =
         'interconnect module component surface feature') AND
       (SIZEOF(QUERY ( sar <* USEDIN (pdr.definition.definition.relating_shape_aspect,
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
        (sar.relating_shape_aspect\shape_aspect.description =
         'interconnect module edge surface') OR
        (sar.relating_shape_aspect\shape_aspect.description =
         'interconnect module edge segment surface'))) = 1)
         AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'COMPONENT_MOUNTING_FEATURE' IN 
                      TYPEOF (pdr.definition.definition.related_shape_aspect)) 
         AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'COMPONENT_DEFINITION' IN
         TYPEOF (pdr.definition.definition.related_shape_aspect.of_shape.definition))
         AND
       (component_definition_located_by_component_location(SELF) =
                 pdr.definition.definition.related_shape_aspect.of_shape.definition) 
       ))) = 1))
      );
 WR15: NOT((SELF.context_of_items\geometric_representation_context.coordinate_space_dimension
         = 2)
          AND
         (SELF.context_of_items.context_type = 'component stacked'))
       OR
        ((NOT(is_laminate_component_location(SELF)))
          AND
       (( SIZEOF (QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION') |
       (
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_JOINT' IN TYPEOF (pdr.definition.definition))
         AND
       ('mounting joint' = pdr.name)
         AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'COMPONENT_MOUNTING_FEATURE' IN
                      TYPEOF (pdr.definition.definition.related_shape_aspect))
         AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'COMPONENT_DEFINITION' IN
         TYPEOF (pdr.definition.definition.related_shape_aspect.of_shape.definition))
         AND
       (component_definition_located_by_component_location(SELF) :=:
                 pdr.definition.definition.related_shape_aspect.of_shape.definition)    
         AND
       (component_definition_located_by_component_location(SELF) :<>: 
                 pdr.definition.definition.relating_shape_aspect.of_shape.definition)    
       )
      )) = 1))
        );
 WR16: (NOT(is_interconnect_module_component_location(SELF))) OR
      (SIZEOF(QUERY( pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_JOINT' IN TYPEOF (pdr.definition.definition)) AND
      (pdr.definition.definition.relating_shape_aspect\shape_aspect.description =
        'interconnect module component surface feature'))) = 0);
 WR17: NOT((SELF.context_of_items\geometric_representation_context.coordinate_space_dimension
         = 2)
          AND
         (SELF.context_of_items.context_type = 'component stacked'))
       OR
       (SIZEOF(QUERY (cto2d <* SELF.items |
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'CARTESIAN_TRANSFORMATION_OPERATOR_2D' IN TYPEOF (cto2d)) AND
      ((cto2d_determinant_test(cto2d,1.0,0.001 )) OR
      (cto2d_determinant_test(cto2d,-1.0,0.001 )))
      )) = 1);
 WR18 : SIZEOF (QUERY (it <* SELF\representation.items| NOT
     (SIZEOF(
    ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
     'CARTESIAN_TRANSFORMATION_OPERATOR_2D', 
     'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
     'MAPPED_ITEM', 
     'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
     'DESCRIPTIVE_REPRESENTATION_ITEM', 
     'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
     'AXIS2_PLACEMENT_3D'] 
     * TYPEOF(it)) = 1 ))) = 0;
 WR19: SIZEOF (QUERY (it <* SELF.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'AXIS2_PLACEMENT_3D'
       IN TYPEOF (it)) AND
       (it\representation_item.name = 'origin') 
       )) = 0;
 WR20: SIZEOF (QUERY (it <* SELF.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MAPPED_ITEM'
       IN TYPEOF (it))
       AND NOT
       (((it\representation_item.name = 'component assembly 2d position')
        OR
       (it\representation_item.name = 'component assembly 3d position'))
       AND
       (it.mapping_source.mapping_origin\representation_item.name = 'origin')
       AND
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'AXIS2_PLACEMENT_2D' IN TYPEOF (it.mapping_source.mapping_origin))
        OR
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'AXIS2_PLACEMENT_3D' IN TYPEOF (it.mapping_source.mapping_origin))))
       )) = 0;
 WR21: SIZEOF(QUERY(pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.'
       + 'PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION') |
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.'
       + 'NEXT_ASSEMBLY_USAGE_OCCURRENCE' IN 
            TYPEOF(pdr.definition.definition))
       )) = 1;
END_ENTITY; -- component_location
(*

EXPRESS specification:

*)
ENTITY component_mating_constraint_condition
  SUBTYPE OF (shape_aspect);
UNIQUE
  UR1: SELF\shape_aspect.name, SELF\shape_aspect.of_shape;
END_ENTITY; -- component_mating_constraint_condition
(*

EXPRESS specification:

*)
ENTITY component_mounting_feature
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN
       TYPEOF (SELF.of_shape.definition);
  WR2: (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTER_STRATUM_FEATURE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROBE_ACCESS_AREA',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND'] * 
       TYPEOF (SELF)) = 0);
  WR3: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sr_pdr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_REPRESENTATION'
       IN TYPEOF (pdr.used_representation)) |
       sr_pdr.used_representation\representation.name = 
       'planar projected shape')) 
       <= 1))) = 0;
  WR4: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sr_pdr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_REPRESENTATION'
       IN TYPEOF (pdr.used_representation)) |
       sr_pdr.used_representation\representation.name = '3d bound volume shape')) 
       <= 1))) = 0;
  WR5: (NOT (SELF\shape_aspect.description IN ['component feature'])) OR
       (SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'design usage')) <= 1);
  WR6: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated feature')) <= 1;
END_ENTITY; -- component_mounting_feature
(*

EXPRESS specification:

*)
ENTITY component_shape_aspect
  SUPERTYPE OF (ONEOF (land, connected_area_component, inter_stratum_feature)
                ANDOR (thermal_component_shape_aspect))
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN
       TYPEOF (SELF.of_shape.definition);
  WR2: (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTER_STRATUM_FEATURE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FIDUCIAL',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'CONNECTED_AREA_COMPONENT',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_GROUP_COMPONENT_SHAPE_ASPECT',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'THERMAL_COMPONENT_SHAPE_ASPECT',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MATERIAL_REMOVAL_COMPONENT_SHAPE_ASPECT',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTEGRAL_SHIELD',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROBE_ACCESS_AREA',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND'] * 
       TYPEOF (SELF)) >= 1) OR
       (SELF\shape_aspect.description IN [
       'part template occurrence', 
       'laminate component', 
       'laminate text component', 
       'laminate text string component', 
       'conductive interconnect element with pre defined transitions', 
       'join 2 physical connectivity definition supporting',
     'conductive interconnect element with user defined single transition',
      'special symbol laminate component', 
       'primary stratum indicator symbol', 
       'stratum feature template component']);
  WR3: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sr_pdr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_REPRESENTATION'
       IN TYPEOF (pdr.used_representation)) |
       sr_pdr.used_representation\representation.name = 'planar projected shape')) 
       <= 1))) = 0;
  WR4: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sr_pdr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_REPRESENTATION'
       IN TYPEOF (pdr.used_representation)) |
       sr_pdr.used_representation\representation.name = '3d bound volume shape')) 
       <= 1))) = 0;
  WR5: NOT(EXISTS(SELF\shape_aspect.description)) OR 
       (NOT (SELF\shape_aspect.description IN ['laminate text component', 
       'laminate text string component', 
       'special symbol laminate component', 
       'primary stratum indicator symbol',  
       'stratum feature template component']) OR
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN
       TYPEOF (SELF.of_shape.definition)) AND
       (SELF.of_shape.definition\product_definition.description = 
                  'laminate component')
       ));
  WR6: NOT(EXISTS(SELF\shape_aspect.description)) OR 
       (NOT (SELF\shape_aspect.description = 
       'laminate text component') OR
       (SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PART_TEXT_TEMPLATE_DEFINITION' IN
       TYPEOF (it.relating_shape_aspect)))) = 1));
  WR7: NOT(EXISTS(SELF\shape_aspect.description)) OR 
       (NOT (SELF\shape_aspect.description IN
       ['stratum feature template component']) OR
       (SIZEOF (QUERY (sfi <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'stratum feature implementation') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'STRATUM_FEATURE' IN
       TYPEOF (sfi.relating_shape_aspect)))) = 1));
  WR8: NOT(EXISTS(SELF\shape_aspect.description)) OR 
       (NOT (SELF\shape_aspect.description IN
       ['conductive interconnect element with pre defined transitions', 
       'join 2 physical connectivity definition supporting',
       'conductive interconnect element with ' +
       'user defined single transition']) OR
       (SIZEOF (QUERY (cc <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'composed conductor') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'STRATUM_FEATURE' IN
       TYPEOF (cc.related_shape_aspect)))) = 1));
(*
  WR9: NOT(EXISTS(SELF\shape_aspect.description)) OR 
       (NOT (SELF\shape_aspect.description IN
       ['conductive interconnect element with pre defined transitions', 
       'join 2 physical connectivity definition supporting',
       'conductive interconnect element with user ' +
       'defined single transition']) OR
       (SIZEOF (QUERY (at <* associated_terminals(SELF)|
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL' IN
       TYPEOF (at)) AND
       (at\shape_aspect.description =
       'conductive interconnect element terminal')))) >= 2));
*)
 WR10: NOT(EXISTS(SELF\shape_aspect.description)) OR 
       (NOT (SELF\shape_aspect.description IN
       ['special symbol laminate component',
       'primary stratum indicator symbol']) OR
       (SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PART_TEMPLATE_DEFINITION' IN
       TYPEOF (it.relating_shape_aspect)) AND
       (it.related_shape_aspect\shape_aspect.description =
       'special symbol part template')))) = 1));
 WR11: NOT(EXISTS(SELF\shape_aspect.description)) OR 
       (NOT (SELF\shape_aspect.description = 
       'stratum feature template component') OR
       (SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PART_TEMPLATE_DEFINITION' IN
       TYPEOF (it.relating_shape_aspect)) AND
       (it.relating_shape_aspect\shape_aspect.description =
       'stratum feature template')) OR
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND_PHYSICAL_TEMPLATE' IN
       TYPEOF (it.relating_shape_aspect)))) <= 1));
 WR12: NOT(EXISTS(SELF\shape_aspect.description)) OR 
       (NOT (SELF\shape_aspect.description IN
       ['laminate text component']) OR
       (SIZEOF (QUERY (sfi <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'stratum feature implementation') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'STRATUM_FEATURE' IN
       TYPEOF (sfi.relating_shape_aspect)))) >= 1));
 WR13: NOT ((SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTER_STRATUM_FEATURE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FIDUCIAL',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'CONNECTED_AREA_COMPONENT',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_GROUP_COMPONENT_SHAPE_ASPECT',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'THERMAL_COMPONENT_SHAPE_ASPECT',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MATERIAL_REMOVAL_COMPONENT_SHAPE_ASPECT',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTEGRAL_SHIELD',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROBE_ACCESS_AREA',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND'] *
       TYPEOF (SELF)) >= 1) OR
       (SELF\shape_aspect.description IN [
       'laminate component',
       'laminate text component',
       'laminate text string component',
       'conductive interconnect element with pre defined transitions', 
       'join 2 physical connectivity definition supporting',
     'conductive interconnect element with user defined single transition',
      'special symbol laminate component',
       'primary stratum indicator symbol',
       'stratum feature template component'])) OR
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN
       TYPEOF (SELF.of_shape.definition)) AND
       (SELF.of_shape.definition\
        product_definition.frame_of_reference\
        application_context_element.name = 'layout occurrence'));
 WR14: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template')) <= 1;
 WR15: NOT(EXISTS(SELF\shape_aspect.description)) OR 
       (NOT (SELF\shape_aspect.description =
       'join 2 physical connectivity definition supporting') OR
       (SIZEOF ( QUERY (propd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (ri <* QUERY (propdr <* USEDIN (propd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION') |
       propdr\property_definition_relationship.name = 'requirement implementation') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP' IN
       TYPEOF (ri.relating_property_definition.definition)) AND
       (ri.relating_property_definition.definition\shape_aspect_relationship.name =
       'ordered physical connectivity definition') AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_CONNECTIVITY_DEFINITION'
       IN TYPEOF (ri.relating_property_definition.definition.
       related_shape_aspect)) AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_CONNECTIVITY_DEFINITION' IN TYPEOF
       (ri.relating_property_definition.definition.
       relating_shape_aspect)))) = 1))) = 1));
END_ENTITY; -- component_shape_aspect
(*

EXPRESS specification:

*)
ENTITY component_terminal
  SUPERTYPE OF (ONEOF(assembly_module_macro_component_join_terminal,
        interconnect_module_macro_component_join_terminal))
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: (SELF\shape_aspect.description IN 
      ['assembly module component terminal', 
       'bare die component terminal', 
       'component termination passage join terminal', 
       'conductive interconnect element terminal', 
       'interconnect component join terminal', 
       'interconnect module component terminal', 'land join terminal', 
       'minimally defined component terminal',
       'non functional land join terminal', 
       'packaged component join terminal', 
       'printed component join terminal', 'package terminal occurrence',
       'via terminal']) OR
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_MODULE_MACRO_COMPONENT_JOIN_TERMINAL' IN
       TYPEOF  (SELF)) OR
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTERCONNECT_MODULE_MACRO_COMPONENT_JOIN_TERMINAL' IN
       TYPEOF  (SELF));
  WR2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN
       TYPEOF  (SELF.of_shape.definition);
  WR3: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated feature')) <= 1;
  WR4: SIZEOF (QUERY (at <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'associated terminals') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_CONNECTIVITY_DEFINITION' IN
       TYPEOF (at.relating_shape_aspect))) <= 1;
  WR5: SIZEOF (QUERY (cr <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'connectivity requirement') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_NETWORK' IN
       TYPEOF (cr.relating_shape_aspect))) <= 1;
  WR6: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'design usage')) <= 1;
  WR7: (NOT (SELF\shape_aspect.description IN 
       ['assembly module component terminal', 
       'bare die component terminal', 'package terminal occurrence', 
       'packaged component join terminal', 
       'printed component join terminal'])) OR
       (SELF.product_definitional);
  WR8: (NOT (SELF\shape_aspect.description = 
       'assembly module component terminal')) OR
       ((SELF.of_shape.definition.frame_of_reference.name =
       'physical occurrence') AND
       (EXISTS(SELF.of_shape.definition\product_definition.name)) AND
       (NOT(EXISTS(SELF.of_shape.definition\product_definition.name)) OR
       (SELF.of_shape.definition\product_definition.name =
       'assembly module'))
       );
  WR9: (NOT (SELF\shape_aspect.description = 
       'assembly module component terminal')) OR
       (SIZEOF (QUERY (i_f <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated feature') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_MODULE_TERMINAL' IN
       TYPEOF (i_f.relating_shape_aspect)))) = 1);
 WR10: (NOT (SELF\shape_aspect.description = 
       'bare die component terminal')) OR
       (SELF.of_shape.definition\product_definition.description = 
       'bare die component');
 WR11: (NOT (SELF\shape_aspect.description = 
       'bare die component terminal')) OR
       (SIZEOF (QUERY (i_f <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated feature') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'BARE_DIE_TERMINAL' IN
       TYPEOF (i_f.relating_shape_aspect)))) = 1);
(*
 WR12: (NOT (SELF\shape_aspect.description = 
       'component termination passage join terminal')) OR
       (
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PLATED_PASSAGE' IN
       TYPEOF (associated_component(SELF))) AND
       (associated_component(SELF).description =
       'component termination passage'));
*)
 WR13: (NOT (SELF\shape_aspect.description = 
       'component termination passage join terminal')) OR
       (SIZEOF (QUERY (i_f <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated feature') |
       i_f.relating_shape_aspect\shape_aspect.description =
       'component termination passage template join terminal')) = 1);
(*
  WR14: (NOT (SELF\shape_aspect.description = 
        'conductive interconnect element terminal')) OR
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_SHAPE_ASPECT' IN
       TYPEOF (associated_component(SELF)) AND
       ((associated_component(SELF).description =
       'conductive interconnect element with pre defined transitions') OR
       (associated_component(SELF).description =
   'conductive interconnect element with user defined single transition')
       ));
*)
 WR15: (NOT (SELF\shape_aspect.description IN
       ['conductive interconnect element terminal',
       'interconnect component join terminal',
       'printed component join terminal'])) OR
       (SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar.related_shape_aspect\shape_aspect.description =
       'connection zone')) <= 1);
 WR16: (NOT (SELF\shape_aspect.description =
       'interconnect module component terminal')) OR
   ((SELF.of_shape.definition\product_definition.frame_of_reference.name =
       'physical occurrence') AND
       (EXISTS(SELF.of_shape.definition\product_definition.name)) AND
       (NOT(EXISTS(SELF.of_shape.definition\product_definition.name)) OR
       (SELF.of_shape.definition\product_definition.name =
       'interconnect module'))
       );

 WR17: (NOT (SELF\shape_aspect.description =
       'interconnect module component terminal')) OR
       (SIZEOF (QUERY (i_f <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated feature') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTERCONNECT_MODULE_TERMINAL' IN
       TYPEOF (i_f.relating_shape_aspect)
       )) = 1);
 WR18: (NOT (SELF\shape_aspect.description IN
       ['land join terminal', 'non functional land join terminal'])) OR
       (SIZEOF (QUERY (i_f <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated feature') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND_TEMPLATE_TERMINAL' IN
       TYPEOF (i_f.relating_shape_aspect)) AND
       (TRUE)))) = 1);
(*
 WR19: (NOT (SELF\shape_aspect.description = 'land join terminal')) OR
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND' IN
       TYPEOF (associated_component(SELF)));
*)
 WR20: (NOT (SELF\shape_aspect.description = 
       'minimally defined terminal')) OR
       (SIZEOF (QUERY (pdr<* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       pdr.used_representation\representation.name = 
       'part terminal external reference')) = 1);
(*
 WR21: (NOT (SELF\shape_aspect.description = 
       'non functional land join terminal')) OR
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND' IN
       TYPEOF (associated_component(SELF))) AND
       (associated_component(SELF).description IN
       ['non functional land',
       'via dependent non functional land',
       'via and contact size dependent non functional land',
       'component termination passage dependent non functional land',
       'contact size dependent non functional land',
       'component termination passage and contact size ' +
       'dependent non functional land',
       'unsupported passage dependent non functional land'])))) = 1);
*)
 WR22: (NOT (SELF\shape_aspect.description = 
       'package terminal occurrence')) OR
       (SIZEOF (QUERY (ud <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'usage definition') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE_TERMINAL' IN
       TYPEOF (ud.relating_shape_aspect)))) = 1);
 WR23: (NOT (SELF\shape_aspect.description IN 
       ['package terminal occurrence',
       'packaged component join terminal'])) OR
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_COMPONENT' IN
       TYPEOF (SELF.of_shape.definition)) AND
       (SELF.of_shape.definition\product_definition.
        frame_of_reference.name = 
       'physical occurrence'));
 WR24: (NOT (SELF\shape_aspect.description = 
       'packaged component join terminal')) OR
       (SIZEOF (QUERY (i_f <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated feature') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_PART_TERMINAL' IN
       TYPEOF (i_f.relating_shape_aspect)) AND
       (i_f.relating_shape_aspect\shape_aspect.description =
       'join terminal'))) = 1);
 WR25: (NOT (SELF\shape_aspect.description = 
       'packaged component join terminal')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] *
       TYPEOF (it)) = 2)) <= 2)) <= 1)) <= 1); 
 WR26: (NOT (SELF\shape_aspect.description = 
       'packaged component join terminal')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (lmwu <* QUERY (it <* pdr.used_representation.items |
       SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] *
       TYPEOF (it)) = 2) |
       lmwu\representation_item.name = 'maximum wire length')) <= 1)) <= 1)) <= 1);
 WR27: (NOT (SELF\shape_aspect.description = 
       'packaged component join terminal')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (lmwu <* QUERY (it <* pdr.used_representation.items |
       SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] *
       TYPEOF (it)) = 2) |
       lmwu\representation_item.name = 'minimum wire length')) <= 1)) <= 1)) <= 1); 
 WR28: (NOT (SELF\shape_aspect.description = 
       'printed component join terminal')) OR
       ((SELF.of_shape.definition\product_definition.
       frame_of_reference.name =
       'layout occurrence') AND
       (SELF.of_shape.definition\product_definition.
       name = 'interconnect module')
       );
 WR29: (NOT (SELF\shape_aspect.description = 
       'printed component join terminal')) OR
       (SIZEOF (QUERY (i_f <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated feature') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_TERMINAL' IN
       TYPEOF (i_f.relating_shape_aspect)) AND
       (i_f.relating_shape_aspect\shape_aspect.description =
       'join terminal'))) = 1);
 WR30: (NOT (SELF\shape_aspect.description = 
       'printed component join terminal')) OR
       (SIZEOF (QUERY (i <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       pdr\shape_aspect_relationship.name = 'implementation') |
       ((SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_SHAPE_ASPECT'] *
       TYPEOF (i.relating_shape_aspect)) >= 1) AND
       (i.relating_shape_aspect\shape_aspect.description = 
                        'stratum feature template component'))
       )) = 1);
(*
 WR31: (NOT (SELF\shape_aspect.description = 'via terminal')) OR
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PLATED_PASSAGE' IN
       TYPEOF (associated_component(SELF))) AND
       (associated_component(SELF).description IN
       ['buried via', 'interfacial connection',
       'bonded conductive base blind via',
       'non conductive base blind via',
       'plated conductive base blind via'])))) = 1);
*)
 WR32: (NOT (SELF\shape_aspect.description = 'via terminal')) OR
       (SIZEOF (QUERY (i_f <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated feature') |
       i_f.relating_shape_aspect\shape_aspect.description =
       'via template terminal')) = 1);
 WR33: (NOT (SELF\shape_aspect.description =
       'interconnect component join terminal')) OR
       ((SELF.of_shape.definition\product_definition.
       frame_of_reference.name =
       'physical occurrence') AND
       NOT(SELF.of_shape.definition\product_definition.description 
       IN ['assembly module component', 'bare die component', 
       'interconnect module component', 'laminate component',
       'packaged component']));
 WR34: SIZEOF(QUERY(pd <* USEDIN(SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') | SIZEOF(QUERY(pdr <* USEDIN(pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') | 
       SIZEOF(QUERY(dri <* pdr.used_representation.items |
       (dri\representation_item.name = 'global swappable') AND 
       (dri\descriptive_representation_item.description IN ['true', 'false']))) = 1)) = 1)) <= 1;
 WR35: SIZEOF(QUERY(pd <* USEDIN(SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') | SIZEOF(QUERY(pdr <* USEDIN(pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') | 
       SIZEOF(QUERY(dri <* pdr.used_representation.items |
       (dri\representation_item.name = 'local swappable') AND 
       (dri\descriptive_representation_item.description IN ['true', 'false']))) = 1)) = 1)) <= 1;
 WR36: SIZEOF(QUERY(pd <* USEDIN(SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') | SIZEOF(QUERY(pdr <* USEDIN(pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') | 
       SIZEOF(QUERY(dri <* pdr.used_representation.items | dri\representation_item.name = 
       'swap code'
       )) = 1)) = 1)) <= 1;
END_ENTITY; -- component_terminal
(*

EXPRESS specification:

*)
ENTITY composite_array_shape_aspect
  SUPERTYPE OF (ONEOF( linear_composite_array_shape_aspect,
                 rectangular_composite_array_shape_aspect))
  SUBTYPE OF (composite_shape_aspect);
END_ENTITY; -- composite_array_shape_aspect
(*

EXPRESS specification:

*)
ENTITY composite_array_shape_aspect_link
  SUBTYPE OF (shape_aspect,shape_aspect_relationship);
WHERE
  WR1: SELF\shape_aspect_relationship.related_shape_aspect :<>:
       SELF\shape_aspect_relationship.relating_shape_aspect;
  WR2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT' IN
       TYPEOF (SELF\shape_aspect_relationship.related_shape_aspect);
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT' IN
       TYPEOF (SELF\shape_aspect_relationship.relating_shape_aspect);
  WR4: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\shape_aspect_relationship ||
       SELF\composite_array_shape_aspect_link)) = 0;
  WR5: SELF\shape_aspect.name = '';
  WR6: SELF\shape_aspect_relationship.name = '';
  WR7: SIZEOF(USEDIN(SELF, 
             'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
             'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')) = 1;
END_ENTITY; -- composite_array_shape_aspect_link 
(* 

EXPRESS specification:

*)
ENTITY composite_group_shape_aspect
  SUBTYPE OF (composite_shape_aspect);
END_ENTITY; -- composite_group_shape_aspect
(*

EXPRESS specification:

*)
ENTITY composite_signal_property_relationship
  SUBTYPE OF (property_definition, property_definition_relationship);
WHERE
  WR1: SELF\property_definition_relationship.related_property_definition.definition :<>:
       SELF\property_definition_relationship.relating_property_definition.definition;
  WR2: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\property_definition_relationship ||
       SELF\composite_signal_property_relationship || SELF\property_definition)) = 0;
  WR3: SELF\property_definition_relationship.related_property_definition.name =
       'signal property';
  WR4: SELF\property_definition_relationship.relating_property_definition.name =
       'composite signal property';
  WR5: SELF\property_definition.name = '';
  WR6: SELF\property_definition.description = '';
  WR7: SELF\property_definition_relationship.name = '';
  WR8: SELF\property_definition_relationship.description = '';
  WR9: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'CHARACTERIZED_OBJECT' IN TYPEOF(SELF\property_definition.definition)) AND
       (SELF\property_definition.definition.description = 'aggregate operation');
 WR10: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNAL_DEFINITION' IN TYPEOF(SELF\property_definition.definition);
END_ENTITY; -- composite_signal_property_relationship
(*

EXPRESS specification:

*)
ENTITY composite_unit_shape_aspect
  SUBTYPE OF (composite_shape_aspect);
END_ENTITY; -- composite_unit_shape_aspect
(*

EXPRESS specification:

*)
ENTITY concentricity_tolerance
  SUBTYPE OF (geometric_tolerance_with_specified_datum_system);
WHERE
  WR1: SELF\geometric_tolerance.name = 'concentricity';
END_ENTITY; -- concentricity_tolerance
(*

EXPRESS specification:

*)
ENTITY conductance_measure_with_unit
 SUBTYPE OF (measure_with_unit);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\measure_with_unit ||
       SELF\conductance_measure_with_unit))) = 0;
  WR2: SELF\measure_with_unit.unit_component\si_unit.name = siemens;
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SI_UNIT' IN 
       TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY; -- conductance_measure_with_unit
(*

EXPRESS specification:

*)
ENTITY conductive_interconnect_element_terminal_link
  SUBTYPE OF (shape_aspect,shape_aspect_relationship);
WHERE
  WR1: SELF\shape_aspect_relationship.related_shape_aspect :<>:
       SELF\shape_aspect_relationship.relating_shape_aspect;
  WR2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL' IN
       TYPEOF (SELF\shape_aspect_relationship.related_shape_aspect);
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL' IN
       TYPEOF (SELF\shape_aspect_relationship.relating_shape_aspect);
  WR4: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\shape_aspect_relationship ||
       SELF\conductive_interconnect_element_terminal_link)) = 0;
  WR5: SELF\shape_aspect.name = '';
  WR6: SELF\shape_aspect_relationship.name = '';
  WR7: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN
       TYPEOF (SELF\shape_aspect.of_shape.definition);
  WR8: SELF\shape_aspect_relationship.related_shape_aspect.description = 'conductive interconnect element terminal';
  WR9: SELF\shape_aspect_relationship.relating_shape_aspect.description = 'conductive interconnect element terminal';
  WR10: SELF\shape_aspect.of_shape.definition\product_definition.description = 'laminate component';
END_ENTITY; -- conductive_interconnect_element_terminal_link 
(* 

EXPRESS specification:

*)
ENTITY connected_area_component
 SUBTYPE OF (component_shape_aspect);
WHERE
  WR1: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN  
       TYPEOF (SELF.of_shape.definition)) AND 
       (SIZEOF (QUERY (prpc <* 
       USEDIN (SELF.of_shape.definition.formation.of_product,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS') |
       prpc\product_category.name = 'template model')) >= 1);
  WR2: SIZEOF (QUERY (sfi <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'stratum feature implementation') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'STRATUM_FEATURE' IN
       TYPEOF (sfi.relating_shape_aspect))) = 1;
 WR3: SIZEOF (QUERY (sfi <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'associated layer connection point') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAYER_CONNECTION_POINT' IN
       TYPEOF (sfi.relating_shape_aspect))) >= 1;
 WR4: SELF\shape_aspect.description = 'stratum feature template component';
 WR5: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\component_shape_aspect||
       SELF\connected_area_component)) = 0;
END_ENTITY; -- connected_area_component
(*

EXPRESS specification:

*)
ENTITY connection_zone_based_assembly_joint
  SUBTYPE OF (assembly_joint);
WHERE
  WR1: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'zone 1')) = 1;
  WR2: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'zone 2')) = 1;
  WR3: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar.relating_shape_aspect\shape_aspect.description = 'connection zone')) = 2;

END_ENTITY; -- connection_zone_based_assembly_joint
(*

EXPRESS specification:

*)
ENTITY connection_zone_based_fabrication_joint
  SUBTYPE OF (fabrication_joint);
WHERE
  WR1: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'zone 1')) = 1;
  WR2: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'zone 2')) = 1;
  WR3: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar.relating_shape_aspect\shape_aspect.description = 'connection zone')) = 2;

END_ENTITY; -- connection_zone_based_fabrication_joint
(*

EXPRESS specification:

*)
ENTITY connection_zone_interface_plane_relationship
  SUBTYPE OF (shape_aspect, shape_aspect_relationship);
UNIQUE
  UR1: SELF\shape_aspect_relationship.name;
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect_relationship ||
       SELF\connection_zone_interface_plane_relationship ||
       SELF\shape_aspect)) = 0;
  WR2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SEATING_PLANE' IN 
       TYPEOF(SELF\shape_aspect_relationship.relating_shape_aspect);
  WR3: SELF\shape_aspect_relationship.relating_shape_aspect\shape_aspect.description = 
      'plane';
  WR4: SELF\shape_aspect_relationship.related_shape_aspect\shape_aspect.description = 
      'connection zone';
  WR5: SELF\shape_aspect_relationship.description IN ['area', 'edge']; 
  WR6: SELF\shape_aspect.of_shape = SELF\shape_aspect_relationship.related_shape_aspect.of_shape;
  WR7: SELF\shape_aspect.of_shape = SELF\shape_aspect_relationship.relating_shape_aspect.of_shape;
  WR8: SIZEOF (QUERY (dz <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'derived zone') |
       dz.related_shape_aspect\shape_aspect.description = 'connection zone')) = 1;
END_ENTITY; -- connection_zone_interface_plane_relationship
(*

EXPRESS specification:

*)
ENTITY connection_zone_map_identification
  SUBTYPE OF (shape_aspect,representation_relationship);
WHERE
  WR1: SELF\representation_relationship.rep_2 :<>:
       SELF\representation_relationship.rep_1;
  WR2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'USAGE_VIEW_CONNECTION_ZONE_TERMINAL_SHAPE_RELATIONSHIP' IN 
	TYPEOF(SELF\representation_relationship.rep_1);
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'USAGE_VIEW_CONNECTION_ZONE_TERMINAL_SHAPE_RELATIONSHIP' IN 
	TYPEOF(SELF\representation_relationship.rep_2);
  WR4: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\representation_relationship ||
       SELF\connection_zone_map_identification)) = 0;
  WR5: SELF\shape_aspect.name = '';
  WR6: SELF\representation_relationship.name = '';
  WR7: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FOOTPRINT_DEFINITION' IN TYPEOF(SELF.of_shape.definition);
END_ENTITY; -- connection_zone_map_identification 
(* 

EXPRESS specification:

*)
ENTITY coordinated_representation_item
  SUBTYPE OF (representation, representation_item);
WHERE
  WR1: SIZEOF (QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION') |
       SIZEOF (USEDIN (pdr, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DATA_ENVIRONMENT.ELEMENTS')) <= 1)) <= 1;
  WR2: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'APPLIED_DOCUMENT_REFERENCE.ITEMS')) = 1;
  WR3: (NOT (SELF\representation_item.name = 'tolerance')) OR
       (SIZEOF (QUERY (it <* SELF.items |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM' IN 
       TYPEOF (it))) >= 1); 
  WR4: (NOT (SELF\representation_item.name = 'plus minus tolerance')) OR
       (SIZEOF (QUERY (it <* SELF.items |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM' IN 
       TYPEOF (it))) = 3); 
  WR5: (NOT (SELF\representation_item.name = 'symmetrical tolerance')) OR
       (SIZEOF (QUERY (it <* SELF.items |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM' IN 
       TYPEOF (it))) = 2); 
  WR6: (NOT (SELF\representation_item.name = 'plus minus tolerance'))
       OR
       (
        (SIZEOF (QUERY (it <* SELF.items
         | ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
            'MEASURE_REPRESENTATION_ITEM' IN TYPEOF (it)) 
           AND 
            (it\representation_item.name = 'basic value'))
        ) = 1)
       AND
        (SIZEOF (QUERY (it <* SELF.items
         | ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
            'MEASURE_REPRESENTATION_ITEM' IN TYPEOF (it)) 
           AND 
            (it\representation_item.name = 'plus value'))
        ) = 1)
       AND
        (SIZEOF (QUERY (it <* SELF.items 
         | ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
            'MEASURE_REPRESENTATION_ITEM' IN TYPEOF (it)) 
           AND 
            (it\representation_item.name = 'minus value'))
        ) = 1)
       );

  WR7: (NOT (SELF\representation_item.name = 'symmetrical tolerance')) OR
       ((SIZEOF (QUERY (it <* SELF.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM' IN 
       TYPEOF (it)) AND (it\representation_item.name = 'basic value'))
                        ) = 1)
       AND
       (SIZEOF (QUERY (it <* SELF.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM' IN 
       TYPEOF (it)) AND ( it\representation_item.name = 'deviation value'))
                        ) = 1)
       ); 
END_ENTITY; -- coordinated_representation_item
(*

EXPRESS specification:

*)
ENTITY csg_2d_shape_representation
  SUBTYPE OF (shape_representation);
   WHERE 
 WR1: SELF.context_of_items\
  geometric_representation_context.coordinate_space_dimension = 2;

 WR2 : SIZEOF (QUERY (it <* SELF.items| NOT
     (SIZEOF(['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CSG_SOLID', 
     'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM', 
     'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AXIS2_PLACEMENT_2D'] 
     * TYPEOF(it)) = 1 ))) = 0;

 WR3: SIZEOF(QUERY ( it <* SELF.items | 
    (SIZEOF(['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CSG_SOLID']
	* TYPEOF(it)) = 1) 
	OR 
	(('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' 
	IN TYPEOF(it)) AND
	('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
	'CSG_2D_SHAPE_REPRESENTATION' 
	  IN TYPEOF(it\mapped_item.mapping_source.mapped_representation))) 
       )) >= 1;

 WR4: SIZEOF(QUERY ( it <* SELF.items | 
     (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' 
     IN TYPEOF(it)) AND (NOT (( 
      'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
      'CSG_2D_SHAPE_REPRESENTATION') 
      IN TYPEOF(it\mapped_item.mapping_source.mapped_representation)))) )) = 0;
 WR5: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_representation ||
      SELF\csg_2d_shape_representation || SELF\representation)) = 0;
END_ENTITY; -- csg_2d_shape_representation 
(*

EXPRESS specification:

*)
ENTITY curve_dimension
  SUBTYPE OF (dimensional_size);
WHERE
  WR1: SELF\dimensional_size.name <> 'angular' ;
END_ENTITY; -- curve_dimension
(*

EXPRESS specification:

*)
ENTITY cutout_edge_segment
  SUPERTYPE OF (plated_cutout_edge_segment)
  SUBTYPE OF (inter_stratum_feature,shape_aspect_relationship);
WHERE
  WR1: SELF\shape_aspect.description IN [
       'plated cutout edge segment',
       'cutout edge segment'];
  WR2: SIZEOF (QUERY (cc <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'composed cutout') |(
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTER_STRATUM_FEATURE' IN
       TYPEOF (cc.relating_shape_aspect)) AND 
	(cc.relating_shape_aspect\shape_aspect.description  IN ['cutout',
         'physical connectivity interrupting cutout', 'plated cutout']))
       )) = 1;
  WR3: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_SEGMENT_VERTEX' IN
       TYPEOF (SELF\shape_aspect_relationship.relating_shape_aspect));
  WR4: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_SEGMENT_VERTEX' IN
       TYPEOF (SELF\shape_aspect_relationship.related_shape_aspect));
  WR5: SELF\shape_aspect_relationship.related_shape_aspect :<>:
       SELF\shape_aspect_relationship.relating_shape_aspect;
END_ENTITY; -- cutout_edge_segment
(*

EXPRESS specification:

*)
ENTITY data_set_representation_item
  SUBTYPE OF (compound_representation_item);
WHERE
  WR1: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_GROUP_ASSIGNMENT.ITEMS')) > 0;
  WR2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SET_REPRESENTATION_ITEM'
       IN TYPEOF(SELF\compound_representation_item.item_element);
END_ENTITY; -- data_set_representation_item
(*

EXPRESS specification:

*)
ENTITY datum_difference
  SUBTYPE OF (shape_aspect,shape_aspect_relationship);
WHERE
  WR1: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_UNIT_DATUM' IN TYPEOF
       (SELF\shape_aspect_relationship.relating_shape_aspect)) AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_UNIT_DATUM' IN TYPEOF
       (SELF\shape_aspect_relationship.related_shape_aspect));
  WR2: SELF\shape_aspect.name = SELF\shape_aspect_relationship.name;
  WR3: SELF\shape_aspect.description = SELF\shape_aspect_relationship.
       description;
  WR4: SELF\shape_aspect_relationship.relating_shape_aspect :<>:
       SELF\shape_aspect_relationship.related_shape_aspect;
  WR5: SIZEOF (TYPEOF(SELF) - (TYPEOF(SELF\shape_aspect || 
       SELF\shape_aspect_relationship || SELF\datum_difference))) = 0;
END_ENTITY; -- datum_difference
(*

EXPRESS specification:

*)
ENTITY datum_difference_analytical_model_port_assignment
  SUBTYPE OF (property_definition_representation);
WHERE
  WR1: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ANALYTICAL_MODEL_PORT' IN TYPEOF
       (SELF\property_definition_representation.used_representation)) AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DATUM_DIFFERENCE' IN TYPEOF
       (SELF\property_definition_representation.definition));
  WR2: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\property_definition_representation ||
       SELF\datum_difference_analytical_model_port_assignment)) = 0;
END_ENTITY; -- datum_difference_analytical_model_port_assignment
(*

EXPRESS specification:

*)
ENTITY datum_difference_based_characteristic
  SUBTYPE OF (representation_item);
WHERE
  WR1: SIZEOF(QUERY ( r <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'REPRESENTATION.ITEMS') | (SIZEOF(QUERY (prd2 <*
        QUERY ( prd <* USEDIN(r,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION') | 
       ((('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' 
       + 'PROPERTY_DEFINITION_REPRESENTATION') IN TYPEOF(prd)) AND 
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'PROPERTY_DEFINITION') IN TYPEOF(prd\
       property_definition_representation.definition))) ) |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DATUM_DIFFERENCE' IN
      TYPEOF(prd2\property_definition_representation.definition\
                               property_definition.definition))))
            = 1) )) 
               = 1;
END_ENTITY; -- datum_difference_based_characteristic
(*

EXPRESS specification:

*)
ENTITY datum_difference_based_model_parameter
  SUBTYPE OF (model_parameter);
WHERE
      wr1: SIZEOF(QUERY ( r <* USEDIN(SELF,
               'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
               'REPRESENTATION.ITEMS') | (SIZEOF(QUERY (prd2 <*
                QUERY ( prd <* USEDIN(r,
               'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
               'PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION') | 
               ((('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' 
               + 'PROPERTY_DEFINITION_REPRESENTATION') IN TYPEOF(prd)) AND 
               (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
                'PROPERTY_DEFINITION') IN TYPEOF(prd\
               property_definition_representation.definition))) ) |
               ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
                'DATUM_DIFFERENCE' IN
               TYPEOF(prd2\property_definition_representation.definition\
                                        property_definition.definition))))
                = 1) )) 
               = 1;
END_ENTITY; -- datum_difference_based_model_parameter
(*

EXPRESS specification:

*)
ENTITY datum_difference_functional_unit_usage_view_terminal_assignment
  SUBTYPE OF (shape_aspect_relationship);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect_relationship ||
SELF\datum_difference_functional_unit_usage_view_terminal_assignment)) 
                                                              = 0;
  WR2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FUNCTIONAL_UNIT_TERMINAL_DEFINITION' IN TYPEOF 
        (SELF\shape_aspect_relationship.related_shape_aspect);
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DATUM_DIFFERENCE' IN TYPEOF 
        (SELF\shape_aspect_relationship.relating_shape_aspect);
END_ENTITY; -- datum_difference_functional_unit_-
--             usage_view_terminal_assignment
(*

EXPRESS specification:

*)
ENTITY datum_reference_frame
  SUBTYPE OF (shape_aspect);
WHERE
 WR1: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
      SELF\datum_reference_frame)) = 0;
 WR2: SELF\shape_aspect.product_definitional = False;
 WR3: (SIZEOF (QUERY (pud <* QUERY ( sar <* USEDIN(SELF,
      'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
      'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
      sar\shape_aspect_relationship.name = 'reference axis') | 
      (pud.related_shape_aspect\shape_aspect.description = 'axis') AND
      ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
      'PHYSICAL_UNIT_DATUM' IN TYPEOF (pud.related_shape_aspect)))) <= 3);
 WR4: (SIZEOF (QUERY (pud <* QUERY ( sar <* USEDIN(SELF,
      'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
      'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
      sar\shape_aspect_relationship.name = 'reference plane') | 
      (pud.related_shape_aspect\shape_aspect.description = 'plane') AND
      ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
      'PHYSICAL_UNIT_DATUM' IN TYPEOF (pud.related_shape_aspect)))) <= 3);
 WR5: (SIZEOF (QUERY (pud <* QUERY ( sar <* USEDIN(SELF,
      'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
      'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
      sar\shape_aspect_relationship.name = 'reference origin') | 
      (pud.related_shape_aspect\shape_aspect.description = 'point') AND
      ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
      'PHYSICAL_UNIT_DATUM' IN TYPEOF (pud.related_shape_aspect)))) <= 1);
 WR6: (SIZEOF (QUERY (ds <* QUERY ( sar <* USEDIN(SELF,
      'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
      'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'established datum reference frame') | 
      'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
      'DATUM_SYSTEM' IN TYPEOF (ds.related_shape_aspect))) >= 1);

 WR7: (SIZEOF (QUERY (pud <* QUERY ( sar <* USEDIN(SELF,
      'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
      'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
      sar\shape_aspect_relationship.name = 'reference axis') | 
      (pud.related_shape_aspect\shape_aspect.description = 'axis') AND
      ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
      'PHYSICAL_UNIT_DATUM' IN TYPEOF (pud.related_shape_aspect))))
      + SIZEOF (QUERY (pud <* QUERY ( sar <* USEDIN(SELF,
      'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
      'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
      sar\shape_aspect_relationship.name = 'reference plane') | 
      (pud.related_shape_aspect\shape_aspect.description = 'plane') AND
      ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
      'PHYSICAL_UNIT_DATUM' IN TYPEOF (pud.related_shape_aspect))))
      + SIZEOF (QUERY (pud <* QUERY ( sar <* USEDIN(SELF,
      'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
      'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
      sar\shape_aspect_relationship.name = 'reference origin') | 
      (pud.related_shape_aspect\shape_aspect.description = 'point') AND
      ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
      'PHYSICAL_UNIT_DATUM' IN TYPEOF (pud.related_shape_aspect)))) >= 1);
 WR8: (SIZEOF (QUERY (pud <* QUERY ( sar <* USEDIN(SELF,
      'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
      'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
      sar\shape_aspect_relationship.name = 'reference origin') | 
      (pud.related_shape_aspect\shape_aspect.description <> 'point') OR 
      (NOT('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
      'DERIVED_SHAPE_ASPECT' IN TYPEOF (pud.related_shape_aspect)))
       )) = 0);
END_ENTITY; -- datum_reference_frame
(*

EXPRESS specification:

*)
ENTITY datum_system
  SUBTYPE OF (shape_aspect);
WHERE
 WR1: SELF\shape_aspect.product_definitional = False;
 WR2: (SIZEOF (QUERY (sar <* USEDIN(SELF,
      'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
      'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
      sar\shape_aspect_relationship.name = 
                  'established datum reference frame')) = 1);
 WR3: (SIZEOF (QUERY (sar <* USEDIN(SELF,
      'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
      'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
      sar\shape_aspect_relationship.name = 
                       'datum usage in datum system')) >= 1);
 WR4: (SIZEOF (QUERY (pd <* USEDIN(SELF,
      'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
      'PROPERTY_DEFINITION.DEFINITION') |
      (pd\property_definition.description = 
               'datum system property with material conditions')
      OR (pd\property_definition.description = 
      'datum system property without material conditions'))) = 1);
END_ENTITY; -- datum_system
(*

EXPRESS specification:

*)
ENTITY datum_system_based_dimensional_location
  SUBTYPE OF (dimensional_location);
END_ENTITY; -- datum_system_based_dimensional_location
(*

EXPRESS specification:

*)
ENTITY delete_design_object_assignment
   SUBTYPE OF (action_assignment);
     items : SET [1:?] OF managed_design_object;
WHERE
   WR1: SIZEOF(QUERY(it <* SELF.items |
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'PRODUCT_DEFINITION_RELATIONSHIP' IN TYPEOF(it))
        AND (it\product_definition_relationship.name = 'design object deletion'))) = 1;
END_ENTITY; -- delete_design_object_assignment
(*

EXPRESS specification:

*)
ENTITY delete_design_object_request_assignment
   SUBTYPE OF (action_request_assignment);
     items : SET [1:?] OF managed_design_object;
WHERE
   WR1: SIZEOF(QUERY(it <* SELF.items |
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'PRODUCT_DEFINITION_RELATIONSHIP' IN TYPEOF(it))
        AND (it\product_definition_relationship.name = 'design object deletion'))) = 1;
END_ENTITY; -- delete_design_object_request_assignment
(*

EXPRESS specification:

*)
ENTITY dependent_material_removal_feature_template
  SUBTYPE OF (part_template_definition);
WHERE
  WR1: SELF\shape_aspect.description = 'material removal feature template';
  WR2: SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'associated template') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND_PHYSICAL_TEMPLATE' IN
       TYPEOF (am.relating_shape_aspect)) AND
       (am.relating_shape_aspect.description IN
       ['default attachment size and component termination passage based',
       'default attachment size based',
       'default attachment size and via based',
       'default component termination passage based',
       'default via based',
       'default unsupported passage based']))
        )) = 1;
END_ENTITY; -- dependent_material_removal_feature_template
(*

EXPRESS specification:

*)
ENTITY design_layer_type_specific_padstack_definition 
 SUBTYPE OF (padstack_definition);
END_ENTITY; -- design_layer_type_specific_padstack_definition 
(*

EXPRESS specification:

*)
ENTITY design_make_from_relationship
  SUBTYPE OF (product_definition_relationship);
WHERE
  WR1: SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_UNIT',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FUNCTIONAL_UNIT'] *
       TYPEOF (SELF.relating_product_definition)) = 1;
  WR2: SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_UNIT',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FUNCTIONAL_UNIT'] *
       TYPEOF (SELF.related_product_definition)) = 1;
  WR3: SIZEOF( QUERY(pds <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_SHAPE' IN TYPEOF(pds)))) = 0;
END_ENTITY; -- design_make_from_relationship
(*

EXPRESS specification:

*)
ENTITY design_object
  SUBTYPE OF (characterized_object);
END_ENTITY; -- design_object
(*

EXPRESS specification:

*)
ENTITY device_terminal_map
 SUBTYPE OF (shape_aspect, shape_aspect_relationship);
UNIQUE
  UR1: SELF\shape_aspect_relationship.related_shape_aspect,
       SELF\shape_aspect_relationship.relating_shape_aspect;
WHERE
  WR1: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_PART_TERMINAL'
       IN TYPEOF (SELF.relating_shape_aspect);
END_ENTITY; -- device_terminal_map
(*

EXPRESS specification:

*)
ENTITY dimensional_location_with_direction
  SUBTYPE OF (dimensional_location);
WHERE
    wr1: SELF\shape_aspect_relationship.description = 'linear';
END_ENTITY; -- dimensional_location_with_direction
(*

EXPRESS specification:

*)
ENTITY dimensional_size_property
  SUBTYPE OF (dimensional_size, property_definition);
END_ENTITY; -- dimensional_size_property
(*

EXPRESS specification:

*)
ENTITY directed_dimensional_location
  SUBTYPE OF (dimensional_location);
END_ENTITY; -- directed_dimensional_location
(*

EXPRESS specification:

*)
ENTITY discrete_shield
  SUBTYPE OF (component_definition);
WHERE
  WR1: SELF.frame_of_reference.name = 'physical occurrence';
  WR2: SIZEOF (QUERY (si <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'shielded item') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN
       TYPEOF (si.relating_product_definition))) >= 1;
END_ENTITY; -- discrete_shield
(*

EXPRESS specification:

*)
ENTITY document_identifier
  SUBTYPE OF (group);
UNIQUE
  UR1: SELF\group.name, SELF\group.description;
WHERE
  WR1: SIZEOF (USEDIN(SELF,'')) = 1;
END_ENTITY; -- document_identifier
(*

EXPRESS specification:

*)
ENTITY document_identifier_assignment
 SUBTYPE OF (group_assignment);
   SELF\group_assignment.assigned_group : document_identifier;
     items : SET [1:?] OF document_identifier_assigned_item;
END_ENTITY; -- document_identifier_assignment
(*

EXPRESS specification:

*)
ENTITY dose_equivalent_measure_with_unit
 SUBTYPE OF (measure_with_unit);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\measure_with_unit ||
       SELF\dose_equivalent_measure_with_unit))) = 0;
  WR2: SELF\measure_with_unit.unit_component\si_unit.name = sievert;
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SI_UNIT' IN 
       TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY; -- dose_equivalent_measure_with_unit
(*

EXPRESS specification:

*)
ENTITY edge_based_2d_wireframe_shape_representation
  SUBTYPE OF (shape_representation);
WHERE
  WR1: SIZEOF (QUERY (it <* SELF\representation.items |
       NOT (SIZEOF (   
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_BASED_WIREFRAME_MODEL',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MAPPED_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'AXIS2_PLACEMENT_2D'] *
       TYPEOF (it)) = 1))) = 0;
  WR2: SIZEOF (QUERY (it <* SELF\representation.items |
       SIZEOF(['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_BASED_WIREFRAME_MODEL',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MAPPED_ITEM'] * 
       TYPEOF (it)) = 1)) >= 1;
  WR3: SIZEOF (QUERY (ebwm <* QUERY (it <* SELF\representation.items |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_BASED_WIREFRAME_MODEL' IN 
       TYPEOF (it)) |
       NOT (SIZEOF (QUERY (eb <* 
       ebwm\edge_based_wireframe_model.ebwm_boundary |
       NOT (SIZEOF (QUERY (edges <* eb.ces_edges |
       NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_CURVE'
       IN TYPEOF (edges)))) = 0))) = 0))) = 0;
  WR4: SIZEOF (QUERY (ebwm <* QUERY (it <* SELF\representation.items |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_BASED_WIREFRAME_MODEL' IN 
       TYPEOF (it)) |
       NOT (SIZEOF (QUERY (eb <* 
       ebwm\edge_based_wireframe_model.ebwm_boundary |
       NOT (SIZEOF (QUERY (pline_edges <* QUERY (edges <* eb.ces_edges |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'POLYLINE' IN
       TYPEOF (edges\edge_curve.edge_geometry)) |
       NOT (SIZEOF (pline_edges\edge_curve.edge_geometry\polyline.points) 
       > 2))) = 0))) = 0))) = 0;
  WR5: SIZEOF (QUERY (ebwm <* QUERY (it <* SELF\representation.items |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_BASED_WIREFRAME_MODEL' IN 
       TYPEOF (it)) |
       NOT (SIZEOF (QUERY (eb <* 
       ebwm\edge_based_wireframe_model.ebwm_boundary |
       NOT (SIZEOF (QUERY (edges <* eb.ces_edges |
       NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'VERTEX_POINT' IN 
       TYPEOF (edges.edge_start)) AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'VERTEX_POINT' IN 
       TYPEOF (edges.edge_end))))) = 0))) = 0))) = 0;
  WR6: SIZEOF (QUERY (ebwm <* QUERY (it <* SELF\representation.items |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_BASED_WIREFRAME_MODEL' IN 
       TYPEOF (it)) |
       NOT (SIZEOF (QUERY (eb <*
       ebwm\edge_based_wireframe_model.ebwm_boundary |
       NOT (SIZEOF (QUERY (edges <* eb.ces_edges |
       NOT (valid_2d_wireframe_edge_curve
       (edges\edge_curve.edge_geometry,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN')))) 
       = 0))) = 0))) = 0;
  WR7: SIZEOF (QUERY (ebwm <* QUERY (it <* SELF\representation.items|
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_BASED_WIREFRAME_MODEL' IN 
       TYPEOF (it)) |
       NOT (SIZEOF (QUERY (eb <* 
       ebwm\edge_based_wireframe_model.ebwm_boundary |
       NOT (SIZEOF (QUERY (edges <* eb.ces_edges |
       NOT ((valid_wireframe_vertex_point
       (edges.edge_start\vertex_point.vertex_geometry)) AND
       (valid_wireframe_vertex_point
       (edges.edge_end\vertex_point.vertex_geometry))))) = 0))) = 0))) = 0;
  WR8: SIZEOF (QUERY (ebwm <* QUERY (it <* SELF\representation.items |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_BASED_WIREFRAME_MODEL' IN 
       TYPEOF (it)) |
       NOT (SIZEOF (QUERY (eb <* 
       ebwm\edge_based_wireframe_model.ebwm_boundary |
       NOT (SIZEOF (QUERY (con_edges <* QUERY (edges <* eb.ces_edges |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'CONIC'
       IN TYPEOF (edges\edge_curve.edge_geometry)) |
       NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'AXIS2_PLACEMENT_2D' IN
       TYPEOF (con_edges\edge_curve.edge_geometry\conic.position)))) 
       = 0))) = 0))) = 0;
  WR9: SIZEOF (QUERY (mi <* QUERY (it <* SELF\representation.items |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MAPPED_ITEM' IN 
       TYPEOF (it)) |
       NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_BASED_2D_WIREFRAME_SHAPE_REPRESENTATION' IN
       TYPEOF (mi\mapped_item.mapping_source.mapped_representation)))) = 0;
  WR10: SELF\representation.
        context_of_items\geometric_representation_context.
        coordinate_space_dimension = 2;
END_ENTITY; -- edge_based_2d_wireframe_shape_representation
(*

EXPRESS specification:

*)
ENTITY edge_segment_cross_section
  SUBTYPE OF (volume_shape_intersection);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\representation ||
       SELF\representation_relationship || 
       SELF\shape_representation_relationship || 
       SELF\volume_shape_intersection || 
       SELF\edge_segment_cross_section))) = 0;
END_ENTITY; -- edge_segment_cross_section 
(* 

EXPRESS specification:

*)
ENTITY edge_segment_vertex
  SUBTYPE OF (physical_unit_datum);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\physical_unit_datum ||
       SELF\edge_segment_vertex)) = 0;
  WR2: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
        pd\property_definition.description = 'shape element characterization'
       )) = 1;
  WR3: SELF\shape_aspect.of_shape\property_definition.definition.
       frame_of_reference\application_context_element.name
       IN ['physical design occurrence', 'physical design usage'];
  WR4: SELF\shape_aspect.name = 'single datum';
END_ENTITY; -- edge_segment_vertex
(*

EXPRESS specification:

*)
ENTITY ee_specification 
 SUBTYPE OF (document);
WHERE
  WR1: SIZEOF (QUERY (apoa <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_PERSON_AND_ORGANIZATION_ASSIGNMENT.ITEMS') |
       apoa.role\person_and_organization_role.name = 'document source')) +
       SIZEOF (QUERY (apoa <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_ORGANIZATION_ASSIGNMENT.ITEMS') |
       apoa.role\organization_role.name = 'document source')) >= 1;
  WR2: SELF\document.kind\document_type.product_data_type IN 
       ['assembly technology specification',
       'design specification', 'fabrication technology specification',
       'interface specification', 'language reference manual',
       'lead form specification', 'material specification',
       'reference document', 'source code',
       'process specification', 'surface finish specification',
       'test specification'];
END_ENTITY; -- ee_specification
(*

EXPRESS specification:

*)
ENTITY electric_charge_measure_with_unit
 SUBTYPE OF (measure_with_unit);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\measure_with_unit ||
       SELF\electric_charge_measure_with_unit))) = 0;
  WR2: SELF\measure_with_unit.unit_component\si_unit.name = coulomb;
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SI_UNIT' IN 
       TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY; -- electric_charge_measure_with_unit
(*

EXPRESS specification:

*)
ENTITY electrical_isolation_component_shape_aspect
  SUBTYPE OF (filled_area_material_removal_component_shape_aspect);
END_ENTITY; -- electrical_isolation_component_shape_aspect
(*

EXPRESS specification:

*)
ENTITY electrical_isolation_removal_template_definition
  SUBTYPE OF (part_template_definition);
(*
WHERE
  WR1: (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'TEXT_LITERAL' IN
       TYPEOF (it))) = 1)) = 1))) = 0);
  WR2: (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] * 
       TYPEOF (it)) = 2) AND (it\representation_item.name = 
         'maximum font vertical extent'))) = 1
       )) = 1))) = 0);
  WR3: (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] * 
       TYPEOF (it)) = 2) AND (it\representation_item.name = 
         'maximum font horizontal extent'))) = 1
       )) = 1))) = 0);
*)
END_ENTITY; -- electrical_isolation_removal_template_definition
(*

EXPRESS specification:

*)
ENTITY electrical_network
  SUBTYPE OF (functional_unit);
END_ENTITY; -- electrical_network
(*

EXPRESS specification:

*)
ENTITY electromotive_force_measure_with_unit
 SUBTYPE OF (measure_with_unit);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\measure_with_unit ||
       SELF\electromotive_force_measure_with_unit))) = 0;
  WR2: SELF\measure_with_unit.unit_component\si_unit.name = volt ;
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SI_UNIT' IN 
       TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY; -- electromotive_force_measure_with_unit
(*

EXPRESS specification:

*)
ENTITY energy_measure_with_unit
 SUBTYPE OF (measure_with_unit);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\measure_with_unit ||
       SELF\energy_measure_with_unit))) = 0;
  WR2: SELF\measure_with_unit.unit_component\si_unit.name = joule;
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SI_UNIT' IN 
       TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY; -- energy_measure_with_unit
(*

EXPRESS specification:

*)
ENTITY evaluated_characteristic
  SUBTYPE OF (representation, representation_relationship);
UNIQUE
  UR1: SELF\representation_relationship.rep_1, SELF\representation_relationship.rep_2;
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\representation ||
       SELF\representation_relationship || 
       SELF\representation_relationship_with_transformation || 
       SELF\evaluated_characteristic))) = 0;
  WR2: SELF\representation_relationship.rep_1 <> 
       SELF\representation_relationship.rep_2;
  WR3: SELF\representation_relationship.name = '';
  WR4: SELF\representation.name = '';
  WR5: SELF\representation_relationship.rep_1.name = 'planned characteristic';
END_ENTITY; -- evaluated_characteristic 
(* 

EXPRESS specification:

*)
ENTITY evaluation_product_definition
 SUBTYPE OF (product_definition);
END_ENTITY; -- evaluation_product_definition
(*

EXPRESS specification:

*)
ENTITY external_definition
  SUPERTYPE OF(ONEOF(bond_category))
  SUBTYPE OF (characterized_object, descriptive_representation_item,
              externally_defined_representation_item);
WHERE
  WR1: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_DOCUMENT_REFERENCE.ITEMS')) = 1;
END_ENTITY; -- external_definition
(*

EXPRESS specification:

*)
ENTITY externally_defined_assembly_definition
 SUBTYPE OF (externally_defined_physical_unit);
WHERE
  WR1: EXISTS(SELF\product_definition.name);
  WR2: NOT EXISTS(SELF\product_definition.name) OR
       (SELF\product_definition.name = 'assembly module');
  WR3: (NOT (SELF.frame_of_reference\application_context_element.name = 'physical design usage')) 
        OR (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_MODULE_TERMINAL' IN
       TYPEOF (sa)) AND
       (sa\shape_aspect.description = 'pca terminal'))) >= 2))) = 0);
END_ENTITY; -- externally_defined_assembly_definition
(*

EXPRESS specification:

*)
ENTITY externally_defined_bare_die
  SUBTYPE OF (externally_defined_physical_unit);
WHERE
  WR1: SIZEOF (QUERY (ifdu <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.' +
       'RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'implemented function') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FUNCTIONAL_UNIT' IN 
       TYPEOF (ifdu.relating_product_definition)) AND
       (ifdu.relating_product_definition.frame_of_reference.name = 
       'functional design usage'))) = 1;
  WR2: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (dut <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION') |
       pdr\property_definition_relationship.name = 'device unit technology') |
       dut.relating_property_definition\property_definition.name = 
       'unit technology')) = 1)) = 1;
  WR3: SIZEOF (QUERY (pd <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'BARE_DIE_TERMINAL' IN 
       TYPEOF (sa))) >= 2))) = 0;
END_ENTITY; -- externally_defined_bare_die
(*

EXPRESS specification:

*)
ENTITY externally_defined_functional_unit
  SUBTYPE OF (functional_unit, externally_defined_product_definition);
END_ENTITY; -- externally_defined_functional_unit
(*

EXPRESS specification:

*)
ENTITY externally_defined_interconnect_definition
 SUBTYPE OF (externally_defined_physical_unit);
WHERE
  WR1: EXISTS(SELF\product_definition.name);
  WR2: NOT EXISTS(SELF\product_definition.name) OR
       (SELF\product_definition.name = 'interconnect module');
END_ENTITY; -- externally_defined_interconnect_definition
(*

EXPRESS specification:

*)
ENTITY externally_defined_package
 SUBTYPE OF (externally_defined_physical_unit);
WHERE
  WR1: SELF.frame_of_reference.name = 'physical design usage';
  WR2: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       pdr.used_representation\representation.name = 
                           'registered case style')) >= 1))) = 0;
  WR3: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sr_pdr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_REPRESENTATION' IN
       TYPEOF (pdr)) |
       sr_pdr.used_representation\representation.name = 'seating plane')) = 1))) = 0;
  WR4: SIZEOF (QUERY (pd <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE_BODY' IN 
       TYPEOF (sa))) <= 1))) = 0;
  WR5: SIZEOF (QUERY (pd <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE_TERMINAL' IN 
       TYPEOF (sa))) >= 1))) = 0;
  WR6: (NOT (SELF\product_definition.description = 'altered package')) OR
       (SIZEOF (QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       (pdr\product_definition_relationship.name = 'package preparation') AND
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PACKAGE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_PACKAGE'] * 
       TYPEOF (pdr.relating_product_definition)) = 1))) = 1); 
END_ENTITY; -- externally_defined_package
(*

EXPRESS specification:

*)
ENTITY externally_defined_packaged_connector
 SUBTYPE OF (externally_defined_packaged_part);
END_ENTITY; -- externally_defined_packaged_connector
(*

EXPRESS specification:

*)
ENTITY externally_defined_packaged_part
 SUPERTYPE OF (externally_defined_packaged_connector)
 SUBTYPE OF (externally_defined_physical_unit);
WHERE
  WR1: (NOT (SELF.frame_of_reference.name = 'physical design usage')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_PART_TERMINAL' IN 
       TYPEOF (sa))) >= 2))) = 0);
  WR2: (NOT (SELF.frame_of_reference.name = 'physical design usage')) OR
       (SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MATERIAL_DESIGNATION.DEFINITIONS')) = 1);
  WR3: (NOT (SELF.frame_of_reference.name = 'physical design usage')) OR
       (SIZEOF (QUERY (ifu <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'implemented function') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FUNCTIONAL_UNIT' IN
       TYPEOF (ifu.relating_product_definition)) AND
       (ifu.relating_product_definition.frame_of_reference.name =
       'functional design usage'))) = 1);
  WR4: (NOT (SELF.frame_of_reference.name = 'physical design usage')) OR
       (SIZEOF (QUERY (upkg <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'used package') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE' IN
       TYPEOF (upkg.related_product_definition))) = 1);
  WR5: (NOT (SELF\product_definition.description = 
       'altered packaged part')) OR
       (SIZEOF (QUERY (bpp <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'base packaged part') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_PART',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PACKAGED_PART',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_PACKAGED_PART'] * 
       TYPEOF (bpp.relating_product_definition)) = 1) AND
       (bpp.relating_product_definition.frame_of_reference.name =
       'physical design usage'))) >= 1);
  WR6: (NOT (SELF\product_definition.description = 
       'altered packaged part')) OR
       (SIZEOF (QUERY (upkg <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'used package') |
       SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_PART',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PACKAGED_PART',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_PACKAGED_PART'] * 
       TYPEOF (upkg.relating_product_definition)) = 1)) >= 1);
END_ENTITY; -- externally_defined_packaged_part
(*

EXPRESS specification:

*)
ENTITY externally_defined_physical_unit
 SUPERTYPE OF (ONEOF  (externally_defined_package, externally_defined_packaged_part,   
  externally_defined_bare_die, externally_defined_assembly_definition, 
  externally_defined_interconnect_definition))
 SUBTYPE OF (physical_unit, externally_defined_product_definition);
END_ENTITY; -- externally_defined_physical_unit
(*

EXPRESS specification:

*)
ENTITY externally_defined_product_definition
 SUPERTYPE OF (library_defined_product_definition)
 SUBTYPE OF (product_definition, externally_defined_item);
END_ENTITY; -- externally_defined_product_definition
(*

EXPRESS specification:

*)
ENTITY externally_defined_representation_item
  SUBTYPE OF (externally_defined_item, representation_item);
WHERE
  WR1: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_DOCUMENT_REFERENCE.ITEMS')) = 1;
END_ENTITY; -- externally_defined_representation_item
(*

EXPRESS specification:

*)
ENTITY fabrication_joint
  SUBTYPE OF (shape_aspect, shape_aspect_relationship);
WHERE
  WR1: (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL' IN
       TYPEOF (SELF.related_shape_aspect)) AND
       (SELF.related_shape_aspect\shape_aspect.description IN
       ['via terminal', 'printed component join terminal',
       'non functional land join terminal',
       'land join terminal', 'conductive interconnect element terminal',
       'component termination passage join terminal']));
  WR2: (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL' IN
       TYPEOF (SELF.relating_shape_aspect)) AND
       (SELF.relating_shape_aspect\shape_aspect.description IN
       ['via terminal', 'printed component join terminal',
       'non functional land join terminal',
       'land join terminal', 'conductive interconnect element terminal',
       'component termination passage join terminal']));
  WR3: SIZEOF (QUERY (ajm <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'auxiliary joint material') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND' IN
       TYPEOF (ajm.related_shape_aspect)) OR
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_SHAPE_ASPECT' IN
       TYPEOF (ajm.related_shape_aspect)) AND
       (ajm.related_shape_aspect\shape_aspect.description =
       'stratum feature template component')))) <= 1;
  WR4: acyclic_shape_aspect_relationship(SELF,
       [SELF\shape_aspect_relationship.related_shape_aspect],
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.'+
       'FABRICATION_JOINT');
END_ENTITY; -- fabrication_joint
(*

EXPRESS specification:

*)
ENTITY feature_shape_occurrence_relationship
  SUBTYPE OF (representation, shape_representation_relationship);
UNIQUE
  UR1: SELF\representation_relationship.rep_1, SELF\representation_relationship.rep_2;
WHERE
  WR1: SELF\representation_relationship.rep_1 :<>: SELF\representation_relationship.rep_2;
  WR2: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\representation ||
       SELF\representation_relationship || 
       SELF\shape_representation_relationship || 
       SELF\feature_shape_occurrence_relationship))) = 0;
END_ENTITY; -- feature_shape_occurrence_relationship 
(* 

EXPRESS specification:

*)
ENTITY fiducial
  SUBTYPE OF (component_shape_aspect);
WHERE
  wr1: (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
          'COMPONENT_DEFINITION') IN TYPEOF(SELF.of_shape.definition))
            AND (SELF.of_shape.definition\product_definition.description = 
                    'laminate component');
END_ENTITY; -- fiducial
(*

EXPRESS specification:

*)
ENTITY fiducial_part_feature
 SUBTYPE OF (part_tooling_feature);
END_ENTITY; -- fiducial_part_feature
(*

EXPRESS specification:

*)
ENTITY fiducial_stratum_feature
 SUBTYPE OF (stratum_feature);
END_ENTITY; -- fiducial_stratum_feature
(*

EXPRESS specification:

*)
ENTITY filled_area_material_removal_component_shape_aspect
  SUBTYPE OF (material_removal_component_shape_aspect);
END_ENTITY; -- filled_area_material_removal_component_shape_aspect
(*

EXPRESS specification:

*)
ENTITY footprint_definition
 SUBTYPE OF (product_definition);
WHERE
  WR1: (NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_WITH_ASSOCIATED_DOCUMENTS' IN 
       TYPEOF (SELF))) OR
       (SIZEOF (QUERY (docs <* 
       SELF\product_definition_with_associated_documents.
        documentation_ids |
       docs.kind\document_type.product_data_type = 'CAD filename')) <= 1);
  WR2: SIZEOF (QUERY (adta <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'APPLIED_DATE_AND_TIME_ASSIGNMENT.ITEMS') |
       adta.role\date_time_role.name = 'creation date')) + 
       SIZEOF (QUERY (ada <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'APPLIED_DATE_ASSIGNMENT.ITEMS') |
       ada.role\date_role.name = 'creation date')) = 1;
  WR3: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_APPROVAL_ASSIGNMENT.ITEMS')) = 1;
  WR4: SIZEOF (QUERY (apoa <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_PERSON_AND_ORGANIZATION_ASSIGNMENT.ITEMS') |
       apoa.role\person_and_organization_role.name = 'creator')) +
       SIZEOF (QUERY (apoa <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_ORGANIZATION_ASSIGNMENT.ITEMS') |
       apoa.role\organization_role.name = 'creator')) >= 1;
  WR5: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_SECURITY_CLASSIFICATION_ASSIGNMENT.ITEMS')) = 1;
  WR6: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\product_definition ||
       SELF\footprint_definition))) = 0;
  WR7: SELF.frame_of_reference.name IN ['layout design usage' ];
  WR8: SIZEOF (QUERY (prpc <* USEDIN (SELF.formation.of_product,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_RELATED_PRODUCT_CATEGORY.' +
       'PRODUCTS') |
       prpc\product_category.name = 'template model')) = 1;
END_ENTITY; -- footprint_definition
(*

EXPRESS specification:

*)
ENTITY footprint_occurrence
  SUBTYPE OF (assembly_group_component_shape_aspect);
END_ENTITY; -- footprint_occurrence
(*

EXPRESS specification:

*)
ENTITY footprint_occurrence_shape_aspect_relationship
  SUBTYPE OF (shape_aspect_relationship);
WHERE
  WR1: SELF\shape_aspect_relationship.related_shape_aspect :<>:
       SELF\shape_aspect_relationship.relating_shape_aspect;
  WR2: SELF\shape_aspect_relationship.name = 'footprint occurrence sub assembly relationship';
END_ENTITY; -- footprint_occurrence_shape_aspect_relationship 
(* 

EXPRESS specification:

*)
ENTITY force_measure_with_unit
 SUBTYPE OF (measure_with_unit);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\measure_with_unit ||
       SELF\force_measure_with_unit))) = 0;
  WR2: SELF\measure_with_unit.unit_component\si_unit.name = newton;
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SI_UNIT' IN 
       TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY; -- force_measure_with_unit
(*

EXPRESS specification:

*)
ENTITY frequency_measure_with_unit
 SUBTYPE OF (measure_with_unit);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\measure_with_unit ||
       SELF\frequency_measure_with_unit))) = 0;
  WR2: SELF\measure_with_unit.unit_component\si_unit.name = hertz;
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SI_UNIT' IN 
       TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY; -- frequency_measure_with_unit
(*

EXPRESS specification:

*)
ENTITY frozen_assignment 
 SUBTYPE OF (approval_assignment); 
 items : SET [1:?] OF frozen_assigned_item; 
WHERE
 WR1: SELF\approval_assignment.assigned_approval.status.name in ['approved', 'not yet approved'];
END_ENTITY; -- frozen_assignment
(*

EXPRESS specification:

*)
ENTITY functional_specification
  SUBTYPE OF (representation);
WHERE
  WR1: SIZEOF (QUERY (rr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION_RELATIONSHIP.REP_2') |
       (rr\representation_relationship.name = 'functional characteristic category') AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNAL_DEFINITION' IN
       TYPEOF (rr.rep_1.items[1])))) = 1;
  WR2: SIZEOF (QUERY (rr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION_RELATIONSHIP.REP_1') |
       (rr\representation_relationship.name = 'characterizing signal' +
       'for functional specification')
       )) = 1;
  WR3: SIZEOF (QUERY (rr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION_RELATIONSHIP.REP_1') |
       (rr\representation_relationship.name = 'reference signal for' +
        'functional specification') 
       )) = 1;
  WR4: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\representation ||
       SELF\functional_specification)) = 0;
  WR5: SELF\representation.name = '';
  WR6: SIZEOF(QUERY( pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'COMPONENT_FUNCTIONAL_UNIT' IN TYPEOF (pdr.definition.definition)) 
        )) = 0;
END_ENTITY; -- functional_specification
(*

EXPRESS specification:

*)
ENTITY functional_specification_definition
  SUBTYPE OF (functional_unit);
WHERE
  WR1: SELF.frame_of_reference\application_context_element.name =
             'functional network design';
  WR2: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FUNCTIONAL_SPECIFICATION' IN TYPEOF (pdr.used_representation))
       )) > 0))) > 0;
END_ENTITY; -- functional_specification_definition
(*

EXPRESS specification:

*)
ENTITY functional_terminal_group
 SUBTYPE OF (group);
UNIQUE
   UR1: SELF\group.name;
END_ENTITY; -- functional_terminal_group
(*

EXPRESS specification:

*)
ENTITY functional_unit
 SUPERTYPE OF ((electrical_network)
              ANDOR (thermal_network) 
	      ANDOR (functional_specification_definition))
 SUBTYPE OF (product_definition);
WHERE
  WR1: SELF.frame_of_reference.name IN ['functional design usage', 
       'functional network design'];
  WR2: (NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_WITH_ASSOCIATED_DOCUMENTS' IN 
       TYPEOF (SELF))) OR
       (SIZEOF (QUERY (docs <* 
   SELF\product_definition_with_associated_documents.documentation_ids |
       docs.kind\document_type.product_data_type = 'CAD filename')) <= 1);
  WR3: SIZEOF (QUERY (adta <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'APPLIED_DATE_AND_TIME_ASSIGNMENT.ITEMS') |
       adta.role\date_time_role.name = 'creation date')) = 1; 
  WR4: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_APPROVAL_ASSIGNMENT.ITEMS')) = 1;
  WR5: SIZEOF (QUERY (apoa <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_PERSON_AND_ORGANIZATION_ASSIGNMENT.ITEMS') |
       apoa.role\person_and_organization_role.name = 'creator')) +
       SIZEOF (QUERY (apoa <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_ORGANIZATION_ASSIGNMENT.ITEMS') |
       apoa.role\organization_role.name = 'creator')) >= 1;
  WR6: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_SECURITY_CLASSIFICATION_ASSIGNMENT.ITEMS')) = 1;
  WR7: (NOT (SELF.frame_of_reference.name = 
                                 'functional network design')) OR
       (SIZEOF (QUERY (du <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.' +
       'RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'design usage') |
       du.relating_product_definition.frame_of_reference.name = 
       'functional design usage')) = 1);
  WR8: (NOT (SIZEOF([
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
            'THERMAL_NETWORK',
            'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
            'ELECTRICAL_NETWORK'] * TYPEOF(SELF)) = 1))
        OR (SELF.frame_of_reference.name = 'functional network design');
END_ENTITY; -- functional_unit
(*

EXPRESS specification:

*)
ENTITY functional_unit_terminal_definition
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FUNCTIONAL_UNIT' IN
       TYPEOF (SELF.of_shape.definition)) AND
   (SELF.of_shape.definition\product_definition.frame_of_reference.name =
       'functional design usage');
  WR2: SIZEOF (QUERY (pd2 <* QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION' IN
       TYPEOF (pd)) |
       SIZEOF (QUERY (funtdba <* QUERY (pdr <* USEDIN (pd2,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION') |
       pdr\property_definition_relationship.name = 
       'functional unit network terminal definition bus assignment') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'BUS_STRUCTURAL_DEFINITION' IN 
       TYPEOF 
       (funtdba.relating_property_definition.definition))) <= 1)) <= 1;
  WR3: SIZEOF (QUERY (pd2 <* QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION' IN
       TYPEOF (pd)) |
       SIZEOF (QUERY (funtdna <* QUERY (pdr <* USEDIN (pd2,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION') |
       pdr\property_definition_relationship.name = 
       'functional unit network terminal definition node assignment') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'NETWORK_NODE_DEFINITION' IN 
       TYPEOF 
       (funtdna.relating_property_definition.definition))) <= 1)) <= 1;
END_ENTITY; -- functional_unit_terminal_definition
(*

EXPRESS specification:

*)
ENTITY geometric_tolerance_group
  SUBTYPE OF (property_definition);
WHERE
    WR1: SELF\property_definition.description
         IN ['separate requirement', 'simultaneous requirement'];
    WR2: (NOT (SELF\property_definition.description = 
          'separate requirement'))
         OR (SIZEOF (QUERY(pdr <* USEDIN(SELF,
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
         'PROPERTY_DEFINITION_RELATIONSHIP.RELATING_PROPERTY_DEFINITION') |
         ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
          'GEOMETRIC_TOLERANCE_WITH_SPECIFIED_DATUM_SYSTEM' 
         IN TYPEOF(pdr.related_property_definition)) AND
         (pdr\property_definition_relationship.name = 'group geometric tolerance')
         )) >=1);
    WR3: (NOT (SELF\property_definition.description = 
        'simultaneous requirement')) 
         OR (SIZEOF (QUERY(pdr <* USEDIN(SELF,
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
         'PROPERTY_DEFINITION_RELATIONSHIP.RELATING_PROPERTY_DEFINITION') |
         (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
          'PHYSICAL_UNIT_GEOMETRIC_TOLERANCE' 
         IN TYPEOF(pdr.related_property_definition)) AND
         (pdr\property_definition_relationship.name = 'group geometric tolerance'))
         )) >=2);
    WR4: (NOT (SELF\property_definition.description = 
         'separate requirement')) 
         OR (SIZEOF (QUERY(pdr <* USEDIN(SELF,
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
         'PROPERTY_DEFINITION_RELATIONSHIP.RELATING_PROPERTY_DEFINITION') |
         (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
          'LINEAR_PROFILE_TOLERANCE' IN 
          TYPEOF(pdr.related_property_definition)) AND
         (pdr.related_property_definition\property_definition.name = 
         'linear profile refinement') AND
         (pdr\property_definition_relationship.name = 'group geometric tolerance') )
         )) =0);
    WR5: (NOT (SELF\property_definition.description = 
         'separate requirement')) 
         OR (SIZEOF (QUERY(pdr <* USEDIN(SELF,
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
         'PROPERTY_DEFINITION_RELATIONSHIP.RELATING_PROPERTY_DEFINITION') |
         (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
          'SURFACE_PROFILE_TOLERANCE' IN 
         TYPEOF(pdr.related_property_definition)) AND
         (pdr.related_property_definition\property_definition.name = 
         'surface profile refinement') AND
         (pdr\property_definition_relationship.name = 'group geometric tolerance') )
         )) =0);
    WR6: (NOT (SELF\property_definition.description = 
         'separate requirement')) 
         OR (SIZEOF (QUERY(pdr <* USEDIN(SELF,
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
         'PROPERTY_DEFINITION_RELATIONSHIP.RELATING_PROPERTY_DEFINITION') |
         (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
          'POSITION_TOLERANCE' IN 
         TYPEOF(pdr.related_property_definition)) AND
         (pdr.related_property_definition\property_definition.name = 
         'feature relating position') AND
         (pdr\property_definition_relationship.name = 'group geometric tolerance') )
         )) =0);
    WR7: (NOT (SELF\property_definition.description = 
         'separate requirement')) 
         OR (SIZEOF (QUERY(pdr <* USEDIN(SELF,
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
         'PROPERTY_DEFINITION_RELATIONSHIP.RELATING_PROPERTY_DEFINITION') |
         (pdr\property_definition_relationship.name = 'group geometric tolerance') AND
      (SIZEOF(['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
         'LINEAR_PROFILE_TOLERANCE',
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
         'SURFACE_PROFILE_TOLERANCE',
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
     'POSITION_TOLERANCE'] * TYPEOF(pdr.related_property_definition)) > 0)
         )) =0);
END_ENTITY; -- geometric_tolerance_group
(*

EXPRESS specification:

*)
ENTITY geometric_tolerance_with_specified_datum_system
  SUBTYPE OF (physical_unit_geometric_tolerance);
WHERE
   WR1: SIZEOF(['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
               'ANGULARITY_TOLERANCE',
               'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
               'POSITION_TOLERANCE',
               'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
               'CIRCULAR_RUNOUT_TOLERANCE',
               'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
               'LINEAR_PROFILE_TOLERANCE',
               'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
               'SURFACE_PROFILE_TOLERANCE',
               'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
               'CONCENTRICITY_TOLERANCE',
               'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
               'PARALLELISM_TOLERANCE',
               'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
               'PERPENDICULARITY_TOLERANCE',
               'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
               'SYMMETRY_TOLERANCE',
               'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
               'TOTAL_RUNOUT_TOLERANCE'] * TYPEOF(SELF)) = 1;

   WR2: SIZEOF (QUERY(pdr <* USEDIN(SELF,
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
         'PROPERTY_DEFINITION_RELATIONSHIP.RELATING_PROPERTY_DEFINITION') |
         ((pdr.related_property_definition\property_definition.description =
           'datum system property with material conditions')
          OR (pdr.related_property_definition\property_definition.description =
              'datum system property without material conditions'))
         AND (pdr\property_definition_relationship.name = 'referenced datum system definition')
         )) = 1;

   WR3: SIZEOF (QUERY(pdr <* USEDIN(SELF,
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'PROPERTY_DEFINITION_RELATIONSHIP.RELATING_PROPERTY_DEFINITION') |
         ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.'
           + 'GEOMETRIC_TOLERANCE_GROUP' IN 
             TYPEOF(pdr.related_property_definition))
          AND (pdr.related_property_definition\property_definition.description = 
              'separate requirement')
          AND (pdr\property_definition_relationship.name = 'group geometric tolerance')
         )) <= 1;
END_ENTITY; -- geometric_tolerance_with_specified_datum_system
(*

EXPRESS specification:

*)
ENTITY group_product_definition
  SUBTYPE OF (component_definition);
WHERE
  WR1: SELF.frame_of_reference.name = 'design requirement';
  WR2: (NOT (SELF\product_definition.description = 
                                      'placement group')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REQUIREMENTS_PROPERTY' IN
       TYPEOF (pd))) >= 1);
END_ENTITY; -- group_product_definition
(*

EXPRESS specification:

*)
ENTITY group_shape_aspect
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION' IN
       TYPEOF (SELF\shape_aspect.of_shape.definition);
  WR2: NOT(SELF\shape_aspect.description IN 
       ['interconnect module constraint region']) OR
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_UNIT' IN
       TYPEOF (SELF\shape_aspect.of_shape.definition)) AND
       (EXISTS(SELF\shape_aspect.of_shape.definition\product_definition.name)) AND
       (NOT EXISTS(SELF\shape_aspect.of_shape.definition\product_definition.name) OR 
       (SELF\shape_aspect.of_shape.definition\product_definition.name = 'interconnect module')));
 WR3: ((NOT(SELF\shape_aspect.description IN 
       ['interconnect module constraint region'])) OR
               (SIZEOF( QUERY ( pd <* USEDIN(SELF,
            'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
                         'PROPERTY_DEFINITION.DEFINITION')
                     | (SIZEOF( QUERY ( pdr <* USEDIN(pd,
           'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
    'PROPERTY_DEFINITION_RELATIONSHIP.RELATING_PROPERTY_DEFINITION')
                            | ((pdr\property_definition_relationship.name = 'constrained object')
     AND (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
                    'INTERCONNECT_MODULE_DESIGN_OBJECT_CATEGORY') IN
                  TYPEOF(pdr.related_property_definition.definition)))
                        )) = 1)
                )) = 1));
 WR4: (NOT(SELF\shape_aspect.description IN 
       ['interconnect module constraint region'])) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESCRIPTIVE_REPRESENTATION_ITEM' IN
       TYPEOF (it)) AND
       (it\representation_item.name = 'design specific purpose'))) = 1)) = 1))) = 0);
  WR5: (NOT(SELF\shape_aspect.description IN 
       ['interconnect module constraint region'])) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESCRIPTIVE_REPRESENTATION_ITEM' IN
       TYPEOF (it)) AND
       (it\representation_item.name = 'keepout') AND
       (it\descriptive_representation_item.description IN ['true', 'false']))) = 1)) = 1))) = 0);
  WR6: (NOT(SELF\shape_aspect.description IN 
       ['interconnect module constraint region'])) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_REPRESENTATION' IN
       TYPEOF (pdr.used_representation))) = 1)) = 1);
  WR7: (NOT(SELF\shape_aspect.description IN
       ['interconnect module constraint region'])) OR
               (SIZEOF( QUERY ( pd <* USEDIN(SELF,
            'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
                         'PROPERTY_DEFINITION.DEFINITION')
                     | (SIZEOF( QUERY ( pdr <* USEDIN(pd,
           'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
    'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')
                            | ((pdr\property_definition_relationship.name = 'requirement')
     AND (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
                    'REQUIREMENTS_PROPERTY') IN
                  TYPEOF(pdr.relating_property_definition)))
                        )) = 1)
                )) = 1);
  WR8: (NOT(SELF\shape_aspect.description = 
       'termination constraint')) OR
       (SIZEOF (QUERY (ctm <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'constrained termination member') |
       ctm.related_shape_aspect\shape_aspect.description = 
       'mating connector termination')) >= 2);
  WR9: EXISTS(SELF\shape_aspect.description);
  WR10: (NOT(SELF\shape_aspect.description IN
       ['placement group'])) OR
               (SIZEOF( QUERY ( pd <* USEDIN(SELF,
            'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
                         'PROPERTY_DEFINITION.DEFINITION')
                     | (SIZEOF( QUERY ( pdr <* USEDIN(pd,
           'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
    'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')
                            | ((pdr\property_definition_relationship.name = 'requirement')
     AND (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
                    'REQUIREMENTS_PROPERTY') IN
                  TYPEOF(pdr.relating_property_definition))
               AND
           (pdr.relating_property_definition\property_definition.name = 'requirement')))
                   ) = 1)
                )) = 1);
  WR11: (NOT(SELF\shape_aspect.description IN
       ['termination constraint'])) OR
               (SIZEOF( QUERY ( pd <* USEDIN(SELF,
            'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
                         'PROPERTY_DEFINITION.DEFINITION')
                     | (SIZEOF( QUERY ( pdr <* USEDIN(pd,
           'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
    'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')
                            | ((pdr\property_definition_relationship.name = 'termination usage constraint')
     AND (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
                    'REQUIREMENTS_PROPERTY') IN
                  TYPEOF(pdr.relating_property_definition))
                           AND
    (pdr.relating_property_definition\property_definition.name = 'termination usage constraint')))
                        ) = 1) 
                )) = 1);
END_ENTITY; -- group_shape_aspect
(*

EXPRESS specification:

*)
ENTITY grouped_requirements_property
  SUBTYPE OF (group, requirements_property);
WHERE
  WR1: (NOT (SELF\group.name = 
        'item restricted requirements property')) OR
       (SIZEOF (QUERY (aga <* QUERY (ga <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'GROUP_ASSIGNMENT.ASSIGNED_GROUP') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_GROUP_ASSIGNMENT' IN
       TYPEOF (ga)) |
       SIZEOF (aga.items) = 1)) = 1);
  WR2: (NOT (SELF\group.name = 
        'layout spacing requirements property')) OR
       (SIZEOF (QUERY (aga <* QUERY (ga <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'GROUP_ASSIGNMENT.ASSIGNED_GROUP') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_GROUP_ASSIGNMENT' IN
       TYPEOF (ga)) |
       (SIZEOF (aga.items) = 2) AND
       (SIZEOF (QUERY (rp <* QUERY (it <* aga.items |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESIGN_OBJECT' IN 
       TYPEOF (it)) |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESIGN_OBJECT' IN 
       TYPEOF (rp)) AND
       (rp\characterized_object.name IN [
       'assembly module assembly component',
       'assembly module component terminal',
       'assembly module component',
       'assembly module macro component join terminal',
       'assembly module macro component',
       'assembly module',
       'bare die component terminal',
       'bare die component',
       'bonded conductive base blind via',
       'buried via',
       'cable component',
       'component feature',
       'component mounting feature',
       'component termination passage and contact size dependent land',
       'component termination passage and contact size dependent non functional land',
       'component termination passage dependent land',
       'component termination passage dependent non functional land',
       'component termination passage interface terminal',
       'component termination passage join terminal',
       'component termination passage',
       'conductive interconnect element terminal',
       'conductive interconnect element with pre defined transitions',
       'conductive interconnect element with user defined single transition',
       'connected area component',
       'contact size dependent land',
       'contact size dependent non functional land',
       'cutout edge segment',
       'cutout',
       'dielectric material passage',
       'electrical isolation laminate component',
       'embedded component terminal',
       'fiducial',
       'fill area',
       'filled area material removal laminate component',
       'inter stratum feature',
       'interconnect component interface terminal',
       'interconnect component join terminal',
       'interconnect module assembly component',
       'interconnect module component stratum based terminal',
       'interconnect module component surface feature',
       'interconnect module component terminal',
       'interconnect module component',
       'interconnect module edge segment',
       'interconnect module edge',
       'interconnect module macro component join terminal',
       'interconnect module macro component',
       'interface access material removal laminate component',
       'interface access stratum feature template component',
       'interface component',
       'interfacial connection',
       'internal probe access area',
       'join two physical connectivity definition supporting inter stratum feature',
       'join two physical connectivity definition supporting printed component',
       'laminate component',
       'laminate text component',
       'laminate text string component',
       'land interface terminal',
       'land join terminal',
       'land',
       'material removal laminate component',
       'minimally defined component terminal',
       'movable packaged component join terminal',
       'multi layer material removal laminate component',
       'multi layer stratum feature template component',
       'non conductive base blind via',
       'non functional land interface terminal',
       'non functional land join terminal',
       'non functional land',
       'packaged component join terminal',
       'packaged component',
       'packaged connector component interface terminal',
       'packaged connector component',
       'partially plated cutout',
       'partially plated interconnect module edge',
       'physical component',
       'physical connectivity interrupting cutout',
       'physical laminate component',
       'physical network supporting inter stratum feature',
       'plated conductive base blind via',
       'plated cutout edge segment',
       'plated cutout',
       'plated interconnect module edge segment',
       'plated interconnect module edge',
       'plated passage or unsupported passage',
       'plated passage',
       'primary stratum indicator symbol',
       'printed component join terminal',
       'printed connector component interface terminal',
       'probe access area',
       'routed interconnect component',
       'routed physical component',
       'special symbol laminate component',
       'stratum feature template component',
       'stratum feature',
       'thermal isolation laminate component',
       'unrouted conductive interconnect element',
       'unsupported passage dependent non functional land',
       'unsupported passage',
       'via and contact size dependent land',
       'via and contact size dependent non functional land',
       'via dependent land',
       'via dependent non functional land',
       'via terminal',
       'via']))) = 2))) = 1);
  WR3: (NOT (SELF\group.name = 
       'layout spacing requirements property')) OR
       (SIZEOF (QUERY (aga <* QUERY (ga <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'GROUP_ASSIGNMENT.ASSIGNED_GROUP') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_GROUP_ASSIGNMENT' IN
       TYPEOF (ga)) |
       (SIZEOF (QUERY (rp <* QUERY (it <* aga.items |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESIGN_OBJECT' IN 
       TYPEOF (it)) |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESIGN_OBJECT' IN 
       TYPEOF (rp)) AND
       (rp\characterized_object.description = 
       'dependent design object category'))) = 1))) = 1);
  WR4: (NOT (SELF\group.name = 
       'layout spacing requirements property')) OR
       (SIZEOF (QUERY (aga <* QUERY (ga <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'GROUP_ASSIGNMENT.ASSIGNED_GROUP') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_GROUP_ASSIGNMENT' IN
       TYPEOF (ga)) |
       (SIZEOF (QUERY (rp <* QUERY (it <* aga.items |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESIGN_OBJECT' IN 
       TYPEOF (it)) |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESIGN_OBJECT' IN 
       TYPEOF (rp)) AND
       (rp\characterized_object.description = 
       'reference design object category'))) = 1))) = 1);
END_ENTITY; -- grouped_requirements_property
(*

EXPRESS specification:

*)
ENTITY guided_wave_terminal
   SUBTYPE OF (package_terminal);
END_ENTITY; -- guided_wave_terminal
(*

EXPRESS specification:

*)
ENTITY illuminance_measure_with_unit
 SUBTYPE OF (measure_with_unit);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\measure_with_unit ||
       SELF\illuminance_measure_with_unit))) = 0;
  WR2: SELF\measure_with_unit.unit_component\si_unit.name = lux;
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SI_UNIT' IN 
       TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY; -- illuminance_measure_with_unit
(*

EXPRESS specification:

*)
ENTITY inductance_measure_with_unit
 SUBTYPE OF (measure_with_unit);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\measure_with_unit ||
       SELF\inductance_measure_with_unit))) = 0;
  WR2: SELF\measure_with_unit.unit_component\si_unit.name = henry;
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SI_UNIT' IN 
       TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY; -- inductance_measure_with_unit
(*

EXPRESS specification:

*)
ENTITY integral_shield
  SUBTYPE OF (component_shape_aspect);
WHERE
  WR1: SIZEOF (QUERY(pdr <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN TYPEOF(pdr.relating_property_definition))
       OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
    'COMPONENT_SHAPE_ASPECT' IN TYPEOF(pdr.relating_property_definition)))
       AND (pdr\property_definition_relationship.name = 'shielded item'))) >=1;
END_ENTITY; -- integral_shield
(*

EXPRESS specification:

*)
ENTITY inter_stratum_feature
 SUBTYPE OF (component_shape_aspect);
WHERE
  WR1: SELF\shape_aspect.description IN ['bonded conductive base blind via', 
       'buried via', 'component termination passage', 
       'interfacial connection', 'non conductive base blind via', 
       'plated conductive base blind via', 'plated cutout', 
       'partially plated cutout', 
       'plated cutout edge segment', 
       'partially plated interconnect module edge', 
       'plated interconnect module edge segment', 
       'plated interconnect module edge', 'unsupported passage', 'cutout', 
       'physical connectivity interrupting cutout', 
       'dielectric material passage', 'cutout edge segment', 
       'interconnect module edge segment', 'interconnect module edge'];
  WR2: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESCRIPTIVE_REPRESENTATION_ITEM'
       IN TYPEOF (it)) AND
       (it\representation_item.name = 'feature of size') AND
       (it\descriptive_representation_item.description IN ['true', 'false']))) = 1)) = 1))) = 1;
  WR3: SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PART_TEMPLATE_DEFINITION' IN
       TYPEOF (it.relating_shape_aspect)) AND
       (it.relating_shape_aspect\shape_aspect.description IN
       ['inter stratum feature template',
       'via template',
       'component termination passage template',
       'unsupported passage template']))) = 1;
  WR4: (NOT (SELF\shape_aspect.description = 'cutout edge segment')) OR
       (SIZEOF (QUERY (cc <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'composed cutout') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTER_STRATUM_FEATURE' IN
       TYPEOF (cc.relating_shape_aspect)) AND
       ((cc.relating_shape_aspect\shape_aspect.description =
       'cutout') OR
       (cc.relating_shape_aspect\shape_aspect.description =
       'physical connectivity interrupting cutout') OR
       (cc.relating_shape_aspect\shape_aspect.description =
       'partially plated cutout')))) = 1);
  WR5: (NOT (SELF\shape_aspect.description = 'interconnect module edge segment')) OR
       (SIZEOF (QUERY (ce <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'composed edge') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTER_STRATUM_FEATURE' IN
       TYPEOF (ce.relating_shape_aspect)) AND
       ((ce.relating_shape_aspect\shape_aspect.description =
       'interconnect module edge') OR
       (ce.relating_shape_aspect\shape_aspect.description =
       'interconnect module edge')
        ))) = 1);
  WR6: (NOT (SELF\shape_aspect.description = 'dielectric material passage')) OR
       (SIZEOF (QUERY (pp <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'precedent passage') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTER_STRATUM_FEATURE' IN
       TYPEOF (pp.relating_shape_aspect)) AND
       ((pp.relating_shape_aspect\shape_aspect.description =
       'cutout') OR
       (pp.relating_shape_aspect\shape_aspect.description =
       'physical connectivity interrupting cutout') OR
       (pp.relating_shape_aspect\shape_aspect.description =
       'partially plated cutout')))) = 1);
  WR7: (NOT (SELF\shape_aspect.description = 'dielectric material passage')) OR
       ((SIZEOF (QUERY (rp <* QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REQUIREMENTS_PROPERTY' IN
       TYPEOF (pd)) |
       rp\property_definition.name = 'feature material')) <= 1) OR
       (SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MATERIAL_DESIGNATION.DEFINITIONS')) <= 1));
  WR8: (NOT (SELF\shape_aspect.description = 
       'physical connectivity interrupting cutout')) OR
       (SIZEOF (QUERY (ice <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'interrupted connectivity elements') |
       ice.relating_shape_aspect\shape_aspect.name =
       'conductive interconnect element')) >= 1);
  WR9: (NOT (SELF\shape_aspect.description = 'unsupported passage')) OR
       (SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PART_TEMPLATE_DEFINITION' IN
       TYPEOF (it.relating_shape_aspect)) AND
       (it.relating_shape_aspect\shape_aspect.description =
       'unsupported passage template'))) = 1);
  WR10: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN
       TYPEOF (SELF.of_shape.definition)) AND
       (SIZEOF (QUERY (prpc <*
       USEDIN (SELF.of_shape.definition.formation.of_product,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS') |
       prpc\product_category.name = 'template model')) >= 1);
 WR11: (NOT (SELF\shape_aspect.description = 'cutout edge segment')) OR
       (SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTER_STRATUM_FEATURE_EDGE_SEGMENT_TEMPLATE' IN
       TYPEOF (it.relating_shape_aspect)))) = 1);
 WR12: (NOT (SELF\shape_aspect.description = 
       'plated cutout edge segment')) OR
       (SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTER_STRATUM_FEATURE_EDGE_SEGMENT_TEMPLATE' IN
       TYPEOF (it.relating_shape_aspect)))) = 1);
 WR13: (NOT (SELF\shape_aspect.description = 
       'interconnect module edge segment')) OR
       (SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTER_STRATUM_FEATURE_EDGE_SEGMENT_TEMPLATE' IN
       TYPEOF (it.relating_shape_aspect)))) = 1);
 WR14: (NOT (SELF\shape_aspect.description = 
       'plated interconnect module edge segment')) OR
       (SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTER_STRATUM_FEATURE_EDGE_SEGMENT_TEMPLATE' IN
       TYPEOF (it.relating_shape_aspect)))) = 1);
END_ENTITY; -- inter_stratum_feature
(*

EXPRESS specification:

*)
ENTITY inter_stratum_feature_edge_segment_template
  SUBTYPE OF (part_template_definition,shape_aspect_relationship);
WHERE
  wr1: (SIZEOF (QUERY (ce <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTER_STRATUM_FEATURE_EDGE_TEMPLATE' IN
       TYPEOF (ce.relating_shape_aspect)) 
       )) = 1);
  wr2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_SEGMENT_VERTEX' IN
       TYPEOF (SELF\shape_aspect_relationship.related_shape_aspect);
  wr3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_SEGMENT_VERTEX' IN
       TYPEOF (SELF\shape_aspect_relationship.relating_shape_aspect);
  wr4: SELF\shape_aspect_relationship.relating_shape_aspect :<>:
       SELF\shape_aspect_relationship.related_shape_aspect;
  wr5: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\part_template_definition ||
       SELF\shape_aspect_relationship ||
       SELF\inter_stratum_feature_edge_segment_template)) = 0;
END_ENTITY; -- inter_stratum_feature_edge_segment_template
(*

EXPRESS specification:

*)
ENTITY inter_stratum_feature_edge_template
  SUBTYPE OF (part_template_definition);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\part_template_definition ||
       SELF\inter_stratum_feature_edge_template)) = 0;
  WR2: SELF\shape_aspect.description = 
       'inter stratum feature edge template';
END_ENTITY; -- inter_stratum_feature_edge_template
(*

EXPRESS specification:

*)
ENTITY interconnect_definition
 SUBTYPE OF (physical_unit);
WHERE
  WR1: EXISTS(SELF\product_definition.name);
  WR2: NOT EXISTS(SELF\product_definition.name) OR
       (SELF\product_definition.name = 'interconnect module');
  WR3: (NOT (SELF.frame_of_reference.name = 'physical design')) OR
       (SIZEOF (QUERY (du <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.' +
       'RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'design usage') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTERCONNECT_DEFINITION', 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_INTERCONNECT_DEFINITION', 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_INTERCONNECT_DEFINITION'] *
       TYPEOF (du.relating_product_definition)) = 1) AND
       (du.relating_product_definition.frame_of_reference.name = 
       'physical design usage') AND
       (du.relating_product_definition\product_definition.name = 
       'interconnect module')
)) = 1);
END_ENTITY; -- interconnect_definition
(*

EXPRESS specification:

*)
ENTITY interconnect_module_component_surface_feature
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN
       TYPEOF (SELF.of_shape.definition);
  WR2: (SELF\shape_aspect.description IN [
       'interconnect module component surface feature']);
  WR3: SIZEOF (QUERY (i_f <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated feature') |
       i_f.relating_shape_aspect\shape_aspect.description IN
       ['interconnect module secondary surface',
        'interconnect module primary surface',
        'interconnect module cavity surface',
        'interconnect module cutout surface',
        'interconnect module edge surface',
        'interconnect module edge segment surface'])) = 1;
END_ENTITY; -- interconnect_module_component_surface_feature
(*

EXPRESS specification:

*)
ENTITY interconnect_module_design_object_category
  SUBTYPE OF (characterized_object);
WHERE
  WR1: SELF\characterized_object.description IN 
       ['cutout category', 
       'fill area category', 
       'inter stratum feature category', 
       'stratum feature category', 
       'via category'];
END_ENTITY; -- interconnect_module_design_object_category
(*

EXPRESS specification:

*)
ENTITY interconnect_module_cutout_segment_surface
  SUBTYPE OF (shape_aspect, shape_aspect_relationship);
WHERE
  wr1: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_SEGMENT_VERTEX' IN
       TYPEOF (SELF\shape_aspect_relationship.related_shape_aspect);
  wr2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_SEGMENT_VERTEX' IN
       TYPEOF (SELF\shape_aspect_relationship.relating_shape_aspect);
  wr3: SELF\shape_aspect_relationship.relating_shape_aspect :<>:
       SELF\shape_aspect_relationship.related_shape_aspect;
  WR4: SIZEOF (QUERY (ce <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'composed surface') |
       ('interconnect module cutout surface' = 
       ce.relating_shape_aspect\shape_aspect.description) )) = 1;
  WR5: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\shape_aspect_relationship ||
       SELF\interconnect_module_cutout_segment_surface)) = 0;
END_ENTITY; -- interconnect_module_cutout_segment_surface
(*

EXPRESS specification:

*)
ENTITY interconnect_module_edge_segment
  SUBTYPE OF (inter_stratum_feature,shape_aspect_relationship);
WHERE
  WR1: SELF\shape_aspect.description IN [
       'plated interconnect module edge segment', 
       'interconnect module edge segment'];
  WR2: SIZEOF (QUERY (ji <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'join implementation') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'JOIN_SHAPE_ASPECT' IN
       TYPEOF (ji.relating_shape_aspect)) AND
       (ji.relating_shape_aspect\shape_aspect.name =
       'inter stratum join'))) <= 1;
  WR3: (NOT (SELF\shape_aspect.description = 
       'plated interconnect module edge segment')) OR
       (SIZEOF (QUERY (ce <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'composed edge') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PLATED_INTER_STRATUM_FEATURE' IN
       TYPEOF (ce.relating_shape_aspect)) AND
       (ce.relating_shape_aspect\shape_aspect.description =
       'plated interconnect module edge'))) = 1);
  WR4: (NOT (SELF\shape_aspect.description = 'interconnect module edge segment')) OR
       (SIZEOF (QUERY (ce <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'composed edge') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTER_STRATUM_FEATURE' IN
       TYPEOF (ce.relating_shape_aspect)) AND
       (ce.relating_shape_aspect\shape_aspect.description =
       'interconnect module edge'))) = 1);
  wr5: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_SEGMENT_VERTEX' IN
       TYPEOF (SELF\shape_aspect_relationship.related_shape_aspect);
  wr6: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_SEGMENT_VERTEX' IN
       TYPEOF (SELF\shape_aspect_relationship.relating_shape_aspect);
  wr7: SELF\shape_aspect_relationship.relating_shape_aspect :<>:
       SELF\shape_aspect_relationship.related_shape_aspect;
END_ENTITY; -- interconnect_module_edge_segment
(*

EXPRESS specification:

*)
ENTITY interconnect_module_edge_segment_surface
  SUBTYPE OF (shape_aspect, shape_aspect_relationship);
WHERE
  wr1: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_SEGMENT_VERTEX' IN
       TYPEOF (SELF\shape_aspect_relationship.related_shape_aspect);
  wr2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_SEGMENT_VERTEX' IN
       TYPEOF (SELF\shape_aspect_relationship.relating_shape_aspect);
  wr3: SELF\shape_aspect_relationship.relating_shape_aspect :<>:
       SELF\shape_aspect_relationship.related_shape_aspect;
  WR4: SIZEOF (QUERY (ce <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'composed surface') |
       ('interconnect module edge surface' = 
       ce.relating_shape_aspect\shape_aspect.description) )) = 1;
  WR5: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\shape_aspect_relationship ||
       SELF\interconnect_module_edge_segment_surface)) = 0;
END_ENTITY; -- interconnect_module_edge_segment_surface
(*

EXPRESS specification:

*)
ENTITY interconnect_module_interface_terminal
  SUBTYPE OF (interconnect_module_terminal);
END_ENTITY; -- interconnect_module_interface_terminal
(*

EXPRESS specification:

*)
ENTITY interconnect_module_join_terminal
  SUBTYPE OF (interconnect_module_terminal);
END_ENTITY; -- interconnect_module_join_terminal
(*

EXPRESS specification:

*)
ENTITY interconnect_module_macro_component_join_terminal
  SUBTYPE OF (component_terminal);
WHERE
  WR1: NOT (SELF\shape_aspect.description IN 
       ['assembly module component terminal', 
        'bare die component terminal', 
       'component termination passage join terminal', 
       'conductive interconnect element terminal', 
       'interconnect component join terminal', 
       'land join terminal', 
       'minimally defined component terminal',
       'non functional land join terminal', 
       'packaged component join terminal', 
       'printed component join terminal', 'package terminal occurrence',
       'via terminal']);
END_ENTITY; -- interconnect_module_macro_component_join_terminal
(*

EXPRESS specification:

*)
ENTITY interconnect_module_stratum_based_terminal
  SUBTYPE OF (interconnect_module_terminal);
END_ENTITY; -- interconnect_module_stratum_based_terminal
(*

EXPRESS specification:

*)
ENTITY interconnect_module_terminal
  SUPERTYPE OF (ONEOF(interconnect_module_interface_terminal,
                      interconnect_module_join_terminal))
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: EXISTS(SELF.of_shape.definition\product_definition.name);
  WR2: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_UNIT' IN
       TYPEOF (SELF.of_shape.definition)) AND
       (SELF.of_shape.definition\product_definition.
       frame_of_reference.name = 
       'physical design usage') AND
       (SELF.of_shape.definition\product_definition.name = 
       'interconnect module');
  WR3: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_REPRESENTATION' IN
       TYPEOF (pdr.used_representation))) >= 1)) >= 1; 
  WR4: SIZEOF (QUERY (mct <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'member connected terminal') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PART_CONNECTED_TERMINALS_DEFINITION'
       IN TYPEOF (mct.relating_shape_aspect))) <= 1;
  WR5: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar.related_shape_aspect\shape_aspect.description = 
       'connection zone')) <= 1;
END_ENTITY; -- interconnect_module_terminal
(*

EXPRESS specification:

*)
ENTITY interface_access_component_shape_aspect
  SUBTYPE OF (component_shape_aspect);
END_ENTITY; -- interface_access_component_shape_aspect
(*

EXPRESS specification:

*)
ENTITY interface_access_material_removal_component_shape_aspect
  SUBTYPE OF (material_removal_component_shape_aspect);
END_ENTITY; -- interface_access_material_removal_component_shape_aspect
(*

EXPRESS specification:

*)
ENTITY interface_component_definition
  SUBTYPE OF (component_definition);
WHERE
  WR1: (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_INTERFACE_TERMINAL' IN 
       TYPEOF (sa)) AND
       (sa\shape_aspect.description IN ['interconnect component interface terminal',
       'packaged connector component interface terminal']))) >= 1)) >= 1);
END_ENTITY; -- interface_component_definition
(*

EXPRESS specification:

*)
ENTITY interface_mounted_join
 SUBTYPE OF (shape_aspect_relationship,shape_aspect);
WHERE
  WR1: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_INTERFACE_TERMINAL' IN
       TYPEOF (SELF.related_shape_aspect)) AND
       (SELF.related_shape_aspect\shape_aspect.description = 
       'packaged connector component interface terminal');
  WR2: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL' IN
       TYPEOF (SELF.relating_shape_aspect)) AND
       ((SELF.relating_shape_aspect\shape_aspect.description = 
       'packaged connector component interface terminal') OR
       (SELF.relating_shape_aspect\shape_aspect.description = 
       'packaged connector component interface terminal') OR
       (SELF.relating_shape_aspect\shape_aspect.description = 
       'packaged connector component interface terminal') OR
       (SELF.relating_shape_aspect\shape_aspect.description = 
       'packaged connector component interface terminal') OR
       (SELF.relating_shape_aspect\shape_aspect.description = 
       'packaged connector component interface terminal') OR
       (SELF.relating_shape_aspect\shape_aspect.description = 
       'packaged connector component interface terminal'));
END_ENTITY; -- interface_mounted_join
(*

EXPRESS specification:

*)
ENTITY interfaced_group_component_definition
  SUBTYPE OF (assembly_group_component_definition);
WHERE
  WR1: (SIZEOF (QUERY (gc <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'group component') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTERFACE_COMPONENT_DEFINITION' IN 
       TYPEOF (gc.related_product_definition))))
       >= 1);
END_ENTITY; -- interfaced_group_component_definition
(*

EXPRESS specification:

*)
ENTITY join_shape_aspect
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: NOT(SELF\shape_aspect.name IN ['constrained intra layer join',
       'inter stratum join', 'intra stratum join']) OR 
       (SIZEOF (QUERY (cp <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'connected point') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAYER_CONNECTION_POINT' IN
       TYPEOF (cp.related_shape_aspect))) >= 2);
  WR2: SIZEOF (QUERY (nt <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'network topology') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_NETWORK' IN
       TYPEOF (nt.relating_shape_aspect))) = 1;
  WR3: (NOT (SELF\shape_aspect.name = 'intra stratum join')) OR
       (SIZEOF (QUERY (ji <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'join implementation') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'STRATUM_FEATURE' IN
       TYPEOF (ji.related_shape_aspect)) AND
       (ji.related_shape_aspect\shape_aspect.description = 'conductor'))) <= 1);
  WR4: (NOT (SELF\shape_aspect.name = 'intra stratum join')) OR
       (SIZEOF (QUERY (ji <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'join implementation') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'STRATUM_FEATURE' IN
       TYPEOF (ji.related_shape_aspect)) AND
       (ji.related_shape_aspect\shape_aspect.description = 'connected filled area'))) 
       <= 1);
  WR5: (NOT (SELF\shape_aspect.name = 'inter stratum join')) OR
       (SIZEOF (QUERY (ji <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'join implementation') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'STRATUM_CONCEPT_RELATIONSHIP' IN
       TYPEOF (ji.related_shape_aspect)) AND
       (ji.related_shape_aspect\shape_aspect.description = 
       'physical network supporting stratum feature conductive join')) OR
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PLATED_INTER_STRATUM_FEATURE' IN
       TYPEOF (ji.related_shape_aspect)))) <= 1);
  WR6: NOT(SELF\shape_aspect.name = 'unrouted join') OR
       (SIZEOF (QUERY (cp <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'unrouted terminals') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL' IN
       TYPEOF (cp.related_shape_aspect))) >= 2);
END_ENTITY; -- join_shape_aspect
(*

EXPRESS specification:

*)
ENTITY keepout_design_object_category
  SUBTYPE OF (characterized_object);
WHERE
  WR1: SELF\characterized_object.description IN 
       ['assembly module assembly component category',
        'component feature category',
        'assembly ee material category',
        'interconnect ee material category',
        'interconnect module assembly component category',
        'via category',
        'inter stratum feature category',
        'cutout category',
        'fill area category',
        'laminate component category',
        'stratum feature category'];
END_ENTITY; -- keepout_design_object_category
(*

EXPRESS specification:

*)
ENTITY laminate_component_interface_terminal
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: (NOT (SELF\shape_aspect.description IN 
       ['component termination passage interface terminal', 
       'land interface terminal', 
       'printed connector component interface terminal',
       'non functional land interface terminal'])) OR
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN
       TYPEOF (SELF.of_shape.definition));
  WR2: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated feature')) = 1;
(*
  WR3: (NOT (SELF\shape_aspect.description = 
       'component termination passage interface terminal')) OR
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PLATED_PASSAGE' IN
       TYPEOF (associated_component(SELF))) AND
       (associated_component(SELF).description =
       'component termination passage'));
*)
  WR4: (NOT (SELF\shape_aspect.description = 
       'component termination passage interface terminal')) OR
       (SIZEOF (QUERY (i_f <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated feature') |
       i_f.relating_shape_aspect\shape_aspect.description =
       'component termination passage template interface terminal')) = 1);
 WR5: (NOT (SELF\shape_aspect.description IN
       ['land interface terminal',
       'non functional land interface terminal'])) OR
       (SIZEOF (QUERY (i_f <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated feature') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND_TEMPLATE_TERMINAL' IN
       TYPEOF (i_f.relating_shape_aspect)) AND
       (TRUE)))) = 1);
(*
 WR6: NOT(SELF\shape_aspect.description = 'land interface terminal') OR
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND' IN
       TYPEOF (associated_component(SELF))) AND
(associated_component(SELF).description IN
       ['via and contact size dependent land',
       'contact size dependent land',
    'component termination passage and contact size dependent land']));
 WR7: NOT(SELF\shape_aspect.description =
       'non functional land interface terminal') OR
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND' IN
       TYPEOF (associated_component(SELF))) AND
(associated_component(SELF).description IN
       ['via and contact size dependent non functional land',
       'contact size dependent non functional land',
    'component termination passage and contact size dependent non functional land']));
*)
 WR8: (NOT (SELF\shape_aspect.description = 
       'printed connector component interface terminal')) OR
       (SELF.product_definitional);
 WR9: (NOT (SELF\shape_aspect.description = 
       'printed connector component interface terminal')) OR
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_COMPONENT' IN
       TYPEOF (SELF.of_shape.definition)) AND
       (SELF.of_shape.definition\product_definition.description = 
       'printed connector component'));
 WR10: (NOT (SELF\shape_aspect.description = 
       'printed connector component interface terminal')) OR
       (SIZEOF (QUERY (i_f <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated feature') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_TERMINAL' IN
       TYPEOF (i_f.relating_shape_aspect)) AND
       (i_f.relating_shape_aspect\shape_aspect.description =
       'interface terminal'))) = 1);
 WR11: (NOT (SELF\shape_aspect.description =
       'printed connector component interface terminal')) OR
       (SIZEOF (QUERY (i <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       pdr\shape_aspect_relationship.name = 'implementation') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'STRATUM_FEATURE'] *
       TYPEOF (i.relating_shape_aspect)) = 1)
       )) = 1);
 WR12: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN
       TYPEOF (SELF.of_shape.definition)) AND
       (SELF.of_shape.definition\
        product_definition.frame_of_reference\
        application_context_element.name = 'layout occurrence');
END_ENTITY; -- laminate_component_interface_terminal
(*

EXPRESS specification:

*)
ENTITY laminate_group_component_make_from_relationship
  SUBTYPE OF (make_from_usage_option);
WHERE
  WR1: SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_GROUP_COMPONENT_DEFINITION'] *
       TYPEOF (SELF.relating_product_definition)) = 1;
  WR2: SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_GROUP_COMPONENT_DEFINITION'] *
       TYPEOF (SELF.related_product_definition)) = 1;
  WR3: SIZEOF( QUERY(pd <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
        (SIZEOF( QUERY(pdr <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATING_PROPERTY_DEFINITION') |
       ((pdr.name = 'stratum mapping') AND
       (pdr.related_property_definition\property_definition.
         definition\product_definition_relationship.name = 'stratum make from')
        AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'MAKE_FROM_USAGE_OPTION' IN 
         TYPEOF(pdr.related_property_definition\property_definition.definition)))
          )) > 0) 
        )) > 0;
END_ENTITY; -- laminate_group_component_make_from_relationship
(*

EXPRESS specification:

*)
ENTITY land
 SUBTYPE OF (component_shape_aspect);
WHERE
  WR1: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN  
       TYPEOF (SELF.of_shape.definition)) AND 
       (SIZEOF (QUERY (prpc <* 
       USEDIN (SELF.of_shape.definition.formation.of_product,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS') |
       prpc\product_category.name = 'template model')) >= 1);
  WR2: SIZEOF (QUERY (i_f <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND_PHYSICAL_TEMPLATE' IN
       TYPEOF (i_f.relating_shape_aspect))) = 1;
  WR3: SIZEOF (QUERY (aud <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'alternate usage definition') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND_PHYSICAL_TEMPLATE' IN
       TYPEOF (aud.relating_shape_aspect))) <= 1;
  WR4: SIZEOF (QUERY (sfi <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'stratum feature implementation') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'STRATUM_FEATURE' IN
       TYPEOF (sfi.relating_shape_aspect))) = 1;
(*
  WR5: (NOT (SELF\shape_aspect.description IN
       ['via and contact size dependent land',
    'component termination passage and contact size dependent land'])) OR
       (SIZEOF (QUERY (at <* associated_terminals(SELF) |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_SHAPE_ASPECT' IN
       TYPEOF (at)) AND
       (at\shape_aspect.description =
       'land interface terminal')))) >= 0);
  WR6: (NOT (SELF\shape_aspect.description IN
       ['functional land', 'via dependent land',
       'via and contact size dependent land',
       'component termination passage dependent land',
       'contact size dependent land',
   'component termination passage and contact size dependent land'])) OR
       (SIZEOF (QUERY (at <* associated_terminals(SELF) |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL' IN
       TYPEOF (at)) AND
       (at\shape_aspect.description =
       'land join terminal')))) >= 1);
  WR7: (NOT (SELF\shape_aspect.description IN
       ['via and contact size dependent non functional land',
       'component termination passage and contact size '])) OR
       (SIZEOF (QUERY (at <* associated_terminals(SELF) |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_SHAPE_ASPECT' IN
       TYPEOF (at)) AND
       (at\shape_aspect.description =
       'non functional land interface terminal')))) = 1);
  WR8: (NOT (SELF\shape_aspect.description IN
       ['non functional land', 'via dependent non functional land',
       'via and contact size dependent non functional land',
       'component termination passage dependent non functional land',
       'contact size dependent non functional land',
       'component termination passage and contact size ' + 
       'dependent non functional land',
       'unsupported passage dependent non functional land'])) OR
       (SIZEOF (QUERY (at <* associated_terminals(SELF)|
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL' IN
       TYPEOF (at)) AND
       (at\shape_aspect.description =
       'non functional land join terminal')))) >= 1);
*)
  WR9: (NOT (SELF\shape_aspect.description IN
       ['component termination passage and contact size dependent land',
       'component termination passage and contact size dependent' + 
       'non functional land',
       'component termination passage dependent land',
       'component termination passage dependent non functional land'])) OR
       (SIZEOF (QUERY (rp <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'reference passage') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PLATED_PASSAGE' IN
       TYPEOF (rp.relating_shape_aspect)) AND
       (rp.relating_shape_aspect\shape_aspect.description =
       'component termination passage')))) = 1);
 WR10: (NOT (SELF\shape_aspect.description IN
       ['via and contact size dependent land',
       'via and contact size dependent non functional land',
       'via dependent land', 'via dependent non functional land'])) OR
       (SIZEOF (QUERY (rv <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'reference via') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PLATED_PASSAGE' IN
       TYPEOF (rv.relating_shape_aspect)) AND
       (rv.relating_shape_aspect\shape_aspect.description IN
       ['buried via', 'interfacial connection', 
       'bonded conductive base blind via', 'non conductive base blind via',
       'plated conductive base blind via'])))) = 1);
 WR11: (NOT (SELF\shape_aspect.description = 
       'unsupported passage dependent non functional land')) OR
       (SIZEOF (QUERY (rp <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'reference passage') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTER_STRATUM_FEATURE' IN
       TYPEOF (rp.relating_shape_aspect)) AND
       (rp.relating_shape_aspect\shape_aspect.description =
       'unsupported passage'))) = 1);
 WR12: (NOT (SELF\shape_aspect.description IN
       ['component termination passage dependent land',
       'component termination passage dependent non functional land'])) OR
       (SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND_PHYSICAL_TEMPLATE' IN
       TYPEOF (it.relating_shape_aspect)) AND
       (it.relating_shape_aspect\shape_aspect.description =
       'default component termination passage based')))) = 1);
 WR13: (NOT (SELF\shape_aspect.description IN
       ['component termination passage and contact size dependent land',
       'component termination passage and contact size dependent ' +
       'non functional land'])) OR
       (SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND_PHYSICAL_TEMPLATE' IN
       TYPEOF (it.relating_shape_aspect)) AND
       (it.relating_shape_aspect\shape_aspect.description =
       'default attachment size and component termination ' +
       'passage based')))) = 1);
 WR14: (NOT (SELF\shape_aspect.description IN
       ['contact size dependent land',
       'contact size dependent non functional land'])) OR
       (SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND_PHYSICAL_TEMPLATE' IN
       TYPEOF (it.relating_shape_aspect)) AND
       (it.relating_shape_aspect\shape_aspect.description =
       'default attachment size based')))) = 1);
 WR15: (NOT (SELF\shape_aspect.description IN
       ['via and contact size dependent land',
       'via and contact size dependent non functional land'])) OR
       (SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND_PHYSICAL_TEMPLATE' IN
       TYPEOF (it.relating_shape_aspect)) AND
       (it.relating_shape_aspect\shape_aspect.description =
       'default attachment size and via based')))) = 1);
 WR16: (NOT (SELF\shape_aspect.description IN
       ['via dependent land',
       'via dependent non functional land'])) OR
       (SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND_PHYSICAL_TEMPLATE' IN
       TYPEOF (it.relating_shape_aspect)) AND
       (it.relating_shape_aspect\shape_aspect.description =
       'default via based')))) = 1);
 WR17: (NOT (SELF\shape_aspect.description = 
       'unsupported passage dependent ' +
       'non functional land')) OR
       (SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND_PHYSICAL_TEMPLATE' IN
       TYPEOF (it.relating_shape_aspect)) AND
       (it.relating_shape_aspect\shape_aspect.description =
       'default unsupported passage based'))) = 1);
END_ENTITY; -- land
(*

EXPRESS specification:

*)
ENTITY land_physical_template
  SUBTYPE OF (part_template_definition);
WHERE
  WR1: SIZEOF (QUERY (ada <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_DOCUMENT_REFERENCE.ITEMS') |
       SIZEOF (QUERY (duc <* USEDIN (ada.assigned_document,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DOCUMENT_USAGE_CONSTRAINT.SOURCE') |
    duc\document_usage_constraint.subject_element = 
                 'pre defined classification code')) = 1)) <= 1;
  WR2: SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'associated definition') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAND_TEMPLATE_TERMINAL' IN
       TYPEOF (am.related_shape_aspect))) >= 1;
 WR3:  NOT(EXISTS(SELF\shape_aspect.description)) OR
       ((NOT (SELF\shape_aspect.description IN ['default attachment size based',
       'default attachment size and component termination passage based', 
       'default attachment size and via based'])) OR
       (SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       ((sar\shape_aspect_relationship.name = 'minimum attachment region size') AND 
       (sar.related_shape_aspect\shape_aspect.description = 'connection zone')))) <= 1));
 WR4:  NOT(EXISTS(SELF\shape_aspect.description)) OR
       ((NOT (SELF\shape_aspect.description IN ['default attachment size based',
       'default attachment size and component termination passage based', 
       'default attachment size and via based'])) OR
       (SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       ((sar\shape_aspect_relationship.name = 'maximum attachment region size') AND 
       (sar.related_shape_aspect\shape_aspect.description = 'connection zone')))) <= 1));
 WR5:  NOT(EXISTS(SELF\shape_aspect.description)) OR
       ((NOT (SELF\shape_aspect.description IN 
       ['default component termination passage based',
   'default attachment size and component termination passage based'])) OR
       (SIZEOF (QUERY (tu <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'technology usage') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PASSAGE_TECHNOLOGY' IN
       TYPEOF (tu.related_shape_aspect)) AND
       (tu.related_shape_aspect\shape_aspect.description = 
       'default component termination passage definition'))) = 1));
 WR6:  NOT(EXISTS(SELF\shape_aspect.description)) OR
       ((NOT (SELF\shape_aspect.description IN 
       ['default attachment size and component termination passage based',
       'default attachment size based', 
       'default attachment size and via based', 
       'default component termination passage based',
       'default via based',
       'default unsupported passage based'])) OR
       (SIZEOF (QUERY (ost <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'of stratum technology') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'STRATUM_TECHNOLOGY' IN 
       TYPEOF (ost.relating_shape_aspect.of_shape.definition)
       )) = 1));
 WR7:  NOT(EXISTS(SELF\shape_aspect.description)) OR
       ((NOT (SELF\shape_aspect.description IN 
       ['default attachment size and component termination passage based', 
       'default attachment size and via based', 
       'default component termination passage based', 'default via based', 
       'default unsupported passage based'])) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] * 
       TYPEOF (it)) = 2)) = 2)) = 1))) = 0));
 WR8:  NOT(EXISTS(SELF\shape_aspect.description)) OR
       ((NOT (SELF\shape_aspect.description IN 
       ['default attachment size and component termination passage based', 
       'default attachment size and via based', 
       'default component termination passage based', 'default via based', 
       'default unsupported passage based'])) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] * 
       TYPEOF (it)) = 2) AND 
       (it\representation_item.name = 'minimum fabrication allowance'))) 
       = 1)) = 1))) = 0));
 WR9:  NOT(EXISTS(SELF\shape_aspect.description)) OR
       ((NOT (SELF\shape_aspect.description IN 
       ['default attachment size and component termination passage based', 
       'default attachment size and via based', 
       'default component termination passage based', 'default via based', 
       'default unsupported passage based'])) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] * 
       TYPEOF (it)) = 2) AND (it\representation_item.name = 'minimum annular ring'))) = 1
       )) = 1))) = 0));
 WR10: NOT(EXISTS(SELF\shape_aspect.description)) OR
       ((NOT (SELF\shape_aspect.description IN 
       ['default attachment size and component termination passage based', 
       'default attachment size and via based', 
       'default component termination passage based', 'default via based', 
       'default unsupported passage based'])) OR
       (SIZEOF (QUERY (tu <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'technology usage') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PASSAGE_TECHNOLOGY' IN
       TYPEOF (tu.related_shape_aspect))) = 1));
 WR11: NOT(EXISTS(SELF\shape_aspect.description)) OR
       ((NOT (SELF\shape_aspect.description IN ['default via based',
       'default attachment size and via based'])) OR
       (SIZEOF (QUERY (tu <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'technology usage') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PASSAGE_TECHNOLOGY' IN
       TYPEOF (tu.related_shape_aspect)) AND
       (tu.related_shape_aspect\shape_aspect.description = 'default via definition'))) 
       = 1));
 WR12: NOT(EXISTS(SELF\shape_aspect.description)) OR
       ((NOT (SELF\shape_aspect.description = 'default unsupported passage')) OR
       (SIZEOF (QUERY (tu <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'technology usage') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PASSAGE_TECHNOLOGY' IN
       TYPEOF (tu.related_shape_aspect)) AND
       (tu.related_shape_aspect\shape_aspect.description = 
       'default unsupported passage definition'))) = 1));
END_ENTITY; -- land_physical_template
(*

EXPRESS specification:

*)
ENTITY land_template_terminal
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: SELF\shape_aspect.description IN ['interface terminal', 'join terminal'];
  WR2: SIZEOF (QUERY (tcz <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       (sar\shape_aspect_relationship.name = 'terminal connection zone') AND
       (sar\shape_aspect_relationship.description IN ['edge curve', 'edge point', 
       'surface area', 'surface point'])) |
       tcz.related_shape_aspect\shape_aspect.description = 'connection zone')) >= 0;
END_ENTITY; -- land_template_terminal
(*

EXPRESS specification:

*)
ENTITY layer
 SUBTYPE OF (shape_aspect);
UNIQUE
  UR1: SELF\shape_aspect.name;
WHERE
  WR1: SIZEOF (QUERY (ada <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_DOCUMENT_REFERENCE.ITEMS') |
       SIZEOF (QUERY (duc <* USEDIN (ada.assigned_document,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DOCUMENT_USAGE_CONSTRAINT.SOURCE') |
       duc\document_usage_constraint.subject_element = 'layer definition')) = 1)) <= 1;       
  WR2: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP'
       IN TYPEOF (SELF.of_shape.definition)) AND
       (SELF.of_shape.definition\product_definition_relationship.name = 
                                    'inter stratum extent');
END_ENTITY; -- layer
(*

EXPRESS specification:

*)
ENTITY layer_connection_point
  SUBTYPE OF (shape_aspect);
UNIQUE
  UR1: SELF\shape_aspect.name, SELF\shape_aspect.of_shape;
WHERE
  WR1: SELF\shape_aspect.of_shape.definition\product_definition.
       name = 'design layer';
  WR2: SIZEOF (QUERY (cp <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'connected point') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'JOIN_SHAPE_ASPECT' IN
       TYPEOF (cp.relating_shape_aspect)) AND 
       (cp.relating_shape_aspect.name = 'inter stratum join')))) <= 1;
  WR3: SIZEOF (QUERY (cp <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'connected point') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'JOIN_SHAPE_ASPECT' IN
       TYPEOF (cp.relating_shape_aspect)) AND 
       (cp.relating_shape_aspect.name = 'intra stratum join')))) = 1;
  WR4: NOT(
       SIZEOF (QUERY (cp <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'connected point') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'JOIN_SHAPE_ASPECT' IN
       TYPEOF (cp.relating_shape_aspect)) AND 
       (cp.relating_shape_aspect.name = 'inter stratum join')))) = 1)
       OR
       (SIZEOF (QUERY (cp <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'connected point') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'JOIN_SHAPE_ASPECT' IN
       TYPEOF (cp.relating_shape_aspect)) AND 
       (cp.relating_shape_aspect.name = 'intra stratum join')))) = 1);
  WR5: (NOT (SELF\shape_aspect.description = 'dependently located')) OR
       (SIZEOF (QUERY (ado <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'associated design object') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTER_STRATUM_FEATURE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTERCONNECT_MODULE_TERMINAL'] *
       TYPEOF (ado.relating_shape_aspect)) = 1) OR
       ((SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL'] *
       TYPEOF (ado.relating_shape_aspect)) = 1) AND
       (ado.relating_shape_aspect.description IN ['printed component join terminal',
        'embedded component terminal']))
       )) = 1);
  WR6: (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_REPRESENTATION' IN 
       TYPEOF (pdr.used_representation)) AND
       (pdr.used_representation\representation.name = 'connection point location 2d') AND
       (SIZEOF (QUERY (it <* pdr.used_representation.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'CARTESIAN_POINT' IN
       TYPEOF (it)) AND (it\geometric_representation_item.dim = 2 )
       )) = 1))) <= 1))) = 0);
  WR7: (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_REPRESENTATION' IN 
       TYPEOF (pdr.used_representation)) AND
       (pdr.used_representation\representation.name = 'connection point location 3d') AND
       (SIZEOF (QUERY (it <* pdr.used_representation.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'CARTESIAN_POINT' IN
       TYPEOF (it)) AND (it\geometric_representation_item.dim = 3 )
       )) = 1))) <= 1))) = 0);
  WR8: (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_REPRESENTATION' IN 
       TYPEOF (pdr.used_representation)) AND
       ((pdr.used_representation\representation.name = 'connection point location 2d')
       OR
       (pdr.used_representation\representation.name = 'connection point location 3d'))
       )) >= 1))) = 0);
  WR9: (NOT (SELF\shape_aspect.description = 'dependently located')) OR
       (SIZEOF (QUERY (ado <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'reference zone') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT'] *
       TYPEOF (ado.relating_shape_aspect)) = 1) OR
       ((SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT'] *
       TYPEOF (ado.relating_shape_aspect)) = 1) AND
       (ado.relating_shape_aspect.description IN ['connection zone']))
       )) <= 1);
END_ENTITY; -- layer_connection_point
(*

EXPRESS specification:

*)
ENTITY layer_connection_point_link
  SUBTYPE OF (shape_aspect,shape_aspect_relationship);
WHERE
  WR1: SELF\shape_aspect_relationship.related_shape_aspect :<>:
       SELF\shape_aspect_relationship.relating_shape_aspect;
  WR2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAYER_CONNECTION_POINT' IN
       TYPEOF (SELF\shape_aspect_relationship.related_shape_aspect);
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAYER_CONNECTION_POINT' IN
       TYPEOF (SELF\shape_aspect_relationship.relating_shape_aspect);
  WR4: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\shape_aspect_relationship ||
       SELF\layer_connection_point_link)) = 0;
  WR5: SELF\shape_aspect.name = '';
  WR6: SELF\shape_aspect_relationship.name = '';
  WR7: SIZEOF(QUERY( cp <* USEDIN(SELF, 
             'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
             'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
              cp\shape_aspect_relationship.name = 'connected points')) = 1;
END_ENTITY; -- layer_connection_point_link 
(* 

EXPRESS specification:

*)
ENTITY layout_macro_component
  SUBTYPE OF (printed_component);
WHERE
  WR1: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pt_occ <* QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       sa\shape_aspect.description = 'layout macro component shape aspect') |
       SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (pt_occ,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAYOUT_MACRO_FLOOR_PLAN_TEMPLATE' IN
       TYPEOF (it.relating_shape_aspect))
       )) = 1)) = 1))) = 0;
  WR2: SIZEOF (QUERY (ip <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'design definition') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAYOUT_MACRO_DEFINITION'] *
       TYPEOF (ip.relating_product_definition)) = 1)
       )) = 1;
  WR3: SELF\product_definition.description <> 'printed connector component';
END_ENTITY; -- layout_macro_component
(*

EXPRESS specification:

*)
ENTITY layout_macro_definition
 SUBTYPE OF (interconnect_definition);
WHERE
  WR1: EXISTS(SELF\product_definition.name);
  WR2: SIZEOF (QUERY (du <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.' +
       'RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'design usage') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTERCONNECT_DEFINITION', 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_INTERCONNECT_DEFINITION', 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_INTERCONNECT_DEFINITION'] *
       TYPEOF (du.relating_product_definition)) = 1) AND
       (du.relating_product_definition.frame_of_reference.name = 
       'physical design usage') AND
       (du.relating_product_definition\product_definition.name = 'interconnect module')
       )) = 0;
 WR3: SELF.frame_of_reference\application_context_element.name = 'physical design';
 WR4: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pt_occ <* QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       sa\shape_aspect.description = 'layout macro definition shape aspect') |
       SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (pt_occ,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'floor layout view') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAYOUT_MACRO_FLOOR_PLAN_TEMPLATE' IN
       TYPEOF (it.relating_shape_aspect))
       )) = 1)) = 1))) = 0;
END_ENTITY; -- layout_macro_definition
(*

EXPRESS specification:

*)
ENTITY layout_macro_definition_terminal_to_usage_terminal_assignment
  SUBTYPE OF (shape_aspect, shape_aspect_relationship);
UNIQUE
  UR1: SELF\shape_aspect_relationship.name;
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect_relationship ||
       SELF\layout_macro_definition_terminal_to_usage_terminal_assignment ||
       SELF\shape_aspect)) = 0;
  WR2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_TERMINAL' IN 
       TYPEOF(SELF\shape_aspect_relationship.relating_shape_aspect);
  WR3: SELF\shape_aspect_relationship.related_shape_aspect\shape_aspect.description
       IN ['component termination passage join terminal',
           'conductive interconnect element terminal',
           'land join terminal',
           'non functional land join terminal',
           'printed component join terminal',
           'via terminal'];
  WR4: SIZEOF(USEDIN(SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')) <= 1;

END_ENTITY; -- layout_macro_definition_terminal_to_usage_terminal_assignment
(*

EXPRESS specification:

*)
ENTITY layout_macro_floor_plan_template
  SUBTYPE OF (part_template_definition);
WHERE
  WR1: NOT(SELF\shape_aspect.description IN
      ['component termination passage template',
       'component termination passage template',
       'default trace template',
       'inter stratum feature template',
       'printed connector template',
       'printed part cross section template',
       'printed part template',
       'trace template',
       'unsupported passage template',
       'via template',
       'non conductive cross section template']);
  WR2: SIZEOF(QUERY( sar <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       ((sar\shape_aspect_relationship.name = 'access maps') AND
      ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAYOUT_MACRO_DEFINITION_TERMINAL_TO_USAGE_TERMINAL_ASSIGNMENT' IN
       TYPEOF (sar.relating_shape_aspect)))
       )) >=1;
END_ENTITY; -- layout_macro_floor_plan_template
(*

EXPRESS specification:

*)
ENTITY length_trimmed_terminal
   SUBTYPE OF (altered_package_terminal);
WHERE
 WR1: (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] *
       TYPEOF (it)) = 2)) = 2)) = 1))) = 0);
 WR2:  (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] *
       TYPEOF (it)) = 2) AND
       (it\representation_item.name = 
                   'maximum trimmed length'))) = 1)) = 1))) = 0);
 WR3:  (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] *
       TYPEOF (it)) = 2) AND 
        (it\representation_item.name = 
                  'minimum trimmed length'))) = 1
       )) = 1))) = 0);

END_ENTITY;
(*

EXPRESS specification:

*)
ENTITY library_defined_assembly_definition
 SUBTYPE OF (library_defined_physical_unit);
WHERE
  WR1: EXISTS(SELF\product_definition.name);
  WR2: SELF\product_definition.name = 'assembly module';
  WR3: (NOT (SELF.frame_of_reference.name = 'physical design usage')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_MODULE_TERMINAL' IN
       TYPEOF (sa)) AND
       (sa\shape_aspect.description = 'pca terminal'))) >= 2))) = 0);
END_ENTITY; -- library_defined_assembly_definition
(*

EXPRESS specification:

*)
ENTITY library_defined_bare_die
 SUBTYPE OF (library_defined_physical_unit);
WHERE
  WR1: SIZEOF (QUERY (ifdu <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.' +
       'RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'implemented function') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FUNCTIONAL_UNIT' IN 
       TYPEOF (ifdu.relating_product_definition)) AND
       (ifdu.relating_product_definition.frame_of_reference.name = 
       'functional design usage'))) = 1;
  WR2: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (dut <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION') |
       pdr\property_definition_relationship.name = 'device unit technology') |
       dut.relating_property_definition\property_definition.name = 
       'unit technology')) = 1)) = 1;
  WR3: SIZEOF (QUERY (pd <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'BARE_DIE_TERMINAL' IN 
       TYPEOF (sa))) >= 2))) = 0;
END_ENTITY; -- library_defined_bare_die
(*

EXPRESS specification:

*)
ENTITY library_defined_functional_unit
 SUBTYPE OF (externally_defined_functional_unit);
DERIVE
  library : external_source := SELF\externally_defined_item.source;
END_ENTITY; -- library_defined_functional_unit
(*

EXPRESS specification:

*)
ENTITY library_defined_interconnect_definition
 SUBTYPE OF (library_defined_physical_unit);
WHERE
  WR1: EXISTS(SELF\product_definition.name);
  WR2: SELF\product_definition.name = 'interconnect module';
END_ENTITY; -- library_defined_interconnect_definition
(*

EXPRESS specification:

*)
ENTITY library_defined_package
 SUBTYPE OF (library_defined_physical_unit);
WHERE
  WR1: SELF.frame_of_reference.name = 'physical design usage';
  WR2: SIZEOF(USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION')) > 0;
  WR3: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY(sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SEATING_PLANE' IN
       TYPEOF (sa))) = 1))) = 1;
  WR4: SIZEOF (QUERY (pd <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE_BODY' IN 
       TYPEOF (sa))) = 1))) <= 1;
  WR5: NOT(EXISTS(SELF\product_definition.description) AND
        (SELF\product_definition.description = 'altered package')) OR
       (SIZEOF (QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       (pdr\product_definition_relationship.name = 'package preparation') AND
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PACKAGE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_PACKAGE'] * 
       TYPEOF (pdr.relating_product_definition)) = 1))) = 1); 
END_ENTITY; -- library_defined_package
(*

EXPRESS specification:

*)
ENTITY library_defined_packaged_connector
 SUBTYPE OF (library_defined_packaged_part);
END_ENTITY; -- library_defined_packaged_connector
(*

EXPRESS specification:

*)
ENTITY library_defined_packaged_part
 SUBTYPE OF (library_defined_physical_unit);
WHERE
  WR1: (NOT (SELF.frame_of_reference.name = 'physical design usage')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_PART_TERMINAL' IN 
       TYPEOF (sa))) >= 2))) = 0);
  WR2: (NOT (SELF.frame_of_reference.name = 'physical design usage')) OR
       (SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MATERIAL_DESIGNATION.DEFINITIONS')) = 1);
  WR3: (NOT (SELF.frame_of_reference.name = 'physical design usage')) OR
       (SIZEOF (QUERY (ifu <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'implemented function') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FUNCTIONAL_UNIT' IN
       TYPEOF (ifu.relating_product_definition)) AND
       (ifu.relating_product_definition.frame_of_reference.name =
       'functional design usage'))) = 1);
  WR4: (NOT (SELF.frame_of_reference.name = 'physical design usage')) OR
       (SIZEOF (QUERY (upkg <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'used package') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE' IN
       TYPEOF (upkg.related_product_definition))) = 1);
  WR5: (NOT (SELF\product_definition.description = 'altered packaged part')) OR
       (SIZEOF (QUERY (bpp <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'base packaged part') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_PART',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PACKAGED_PART',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_PACKAGED_PART'] * 
       TYPEOF (bpp.relating_product_definition)) = 1) AND
       (bpp.relating_product_definition.frame_of_reference.name =
       'physical design usage'))) >= 1);
  WR6: (NOT (SELF\product_definition.description = 'altered packaged part')) OR
       (SIZEOF (QUERY (upkg <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'used package') |
       SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_PART',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PACKAGED_PART',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_PACKAGED_PART'] * 
       TYPEOF (upkg.relating_product_definition)) = 1)) >= 1);
END_ENTITY; -- library_defined_packaged_part
(*

EXPRESS specification:

*)
ENTITY library_defined_physical_unit
 SUPERTYPE OF (ONEOF (library_defined_package,
                      library_defined_assembly_definition,
                      library_defined_interconnect_definition,
                      library_defined_packaged_part, 
                      library_defined_bare_die))
 SUBTYPE OF (externally_defined_physical_unit);
DERIVE
  library : external_source := SELF\externally_defined_item.source;
END_ENTITY; -- library_defined_physical_unit
(*

EXPRESS specification:

*)
ENTITY library_defined_product_definition
 SUBTYPE OF (externally_defined_product_definition);
DERIVE
  library : external_source := SELF\externally_defined_item.source;
END_ENTITY; -- library_defined_product_definition
(*

EXPRESS specification:

*)
ENTITY linear_array_component_definition_link
  SUBTYPE OF (product_definition,product_definition_relationship);
WHERE
  WR1: SELF\product_definition_relationship.related_product_definition :<>:
       SELF\product_definition_relationship.relating_product_definition;
  WR2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LINEAR_ARRAY_PLACEMENT_GROUP_COMPONENT_DEFINITION' IN
       TYPEOF (SELF\product_definition_relationship.related_product_definition);
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LINEAR_ARRAY_PLACEMENT_GROUP_COMPONENT_DEFINITION' IN
       TYPEOF (SELF\product_definition_relationship.relating_product_definition);
  WR4: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\product_definition ||
       SELF\product_definition_relationship ||
       SELF\linear_array_component_definition_link)) = 0;
  WR5: SELF\product_definition.name = '';
  WR6: SELF\product_definition_relationship.name = '';
  WR7: SIZEOF(USEDIN(SELF, 
             'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
             'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')) = 1;
END_ENTITY; -- linear_array_component_definition_link 
(* 

EXPRESS specification:

*)
ENTITY linear_array_component_shape_aspect_link
  SUBTYPE OF (shape_aspect,shape_aspect_relationship);
WHERE
  WR1: SELF\shape_aspect_relationship.related_shape_aspect :<>:
       SELF\shape_aspect_relationship.relating_shape_aspect;
  WR2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LINEAR_ARRAY_PLACEMENT_GROUP_COMPONENT_SHAPE_ASPECT' IN
       TYPEOF (SELF\shape_aspect_relationship.related_shape_aspect);
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LINEAR_ARRAY_PLACEMENT_GROUP_COMPONENT_SHAPE_ASPECT' IN
       TYPEOF (SELF\shape_aspect_relationship.relating_shape_aspect);
  WR4: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\shape_aspect_relationship ||
       SELF\linear_array_component_shape_aspect_link)) = 0;
  WR5: SELF\shape_aspect.name = '';
  WR6: SELF\shape_aspect_relationship.name = '';
  WR7: SIZEOF(USEDIN(SELF, 
             'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
             'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')) = 1;
END_ENTITY; -- linear_array_component_shape_aspect_link 
(* 

EXPRESS specification:

*)
ENTITY linear_array_placement_group_component_definition
  SUBTYPE OF (array_placement_group_component_definition);
END_ENTITY; -- linear_array_placement_group_component_definition
(*

EXPRESS specification:

*)
ENTITY linear_array_placement_group_component_shape_aspect
  SUBTYPE OF (array_placement_group_component_shape_aspect);
END_ENTITY; -- linear_array_placement_group_component_shape_aspect
(*

EXPRESS specification:

*)
ENTITY linear_composite_array_shape_aspect
  SUBTYPE OF (composite_array_shape_aspect);
END_ENTITY; -- linear_composite_array_shape_aspect
(*

EXPRESS specification:

*)
ENTITY linear_composite_array_shape_aspect_link
  SUBTYPE OF (shape_aspect,shape_aspect_relationship);
WHERE
  WR1: SELF\shape_aspect_relationship.related_shape_aspect :<>:
       SELF\shape_aspect_relationship.relating_shape_aspect;
  WR2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LINEAR_COMPOSITE_ARRAY_SHAPE_ASPECT' IN
       TYPEOF (SELF\shape_aspect_relationship.related_shape_aspect);
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LINEAR_COMPOSITE_ARRAY_SHAPE_ASPECT' IN
       TYPEOF (SELF\shape_aspect_relationship.relating_shape_aspect);
  WR4: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\shape_aspect_relationship ||
       SELF\linear_composite_array_shape_aspect_link)) = 0;
  WR5: SELF\shape_aspect.name = '';
  WR6: SELF\shape_aspect_relationship.name = '';
  WR7: SIZEOF(USEDIN(SELF, 
             'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
             'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')) = 1;
END_ENTITY; -- linear_composite_array_shape_aspect_link 
(* 

EXPRESS specification:

*)
ENTITY linear_profile_tolerance
  SUBTYPE OF (physical_unit_geometric_tolerance);
WHERE
  WR1: ( NOT( SELF\geometric_tolerance.name = 
        'linear profile refinement')) OR
       ( SIZEOF (QUERY( gtr <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'GEOMETRIC_TOLERANCE_RELATIONSHIP.RELATED_GEOMETRIC_TOLERANCE') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LINEAR_PROFILE_TOLERANCE' IN 
        TYPEOF(gtr.relating_geometric_tolerance))
       AND (gtr\geometric_tolerance_relationship.name = 'linear profile refining control')
       AND ((gtr.relating_geometric_tolerance\geometric_tolerance.name = 
       'linear profile locating')
       OR (gtr.relating_geometric_tolerance\geometric_tolerance.name = 
       'linear profile refinement')))
       )) = 1);
  WR2: ( NOT(SELF\geometric_tolerance.name = 'linear profile locating')) OR
       ( SIZEOF( QUERY( gtr <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'GEOMETRIC_TOLERANCE_RELATIONSHIP.RELATED_GEOMETRIC_TOLERANCE') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LINEAR_PROFILE_TOLERANCE' IN 
       TYPEOF(gtr.relating_geometric_tolerance))
       AND (gtr.relating_geometric_tolerance\geometric_tolerance.name = 
       'linear profile refinement'))
       AND (gtr\geometric_tolerance_relationship.name = 'linear profile refining control'))) = 1);
  WR3: ( NOT( ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'GEOMETRIC_TOLERANCE_WITH_SPECIFIED_DATUM_SYSTEM' IN TYPEOF(SELF))
       AND ( SELF\geometric_tolerance.name = 
       'linear profile refinement'))) OR
       ( SIZEOF( QUERY( gtr <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'GEOMETRIC_TOLERANCE_RELATIONSHIP.RELATED_GEOMETRIC_TOLERANCE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LINEAR_PROFILE_TOLERANCE' IN 
       TYPEOF(gtr.relating_geometric_tolerance))
       AND (gtr.relating_geometric_tolerance\geometric_tolerance.name = 
      'linear profile refinement')
       AND (gtr\geometric_tolerance_relationship.name = 'linear profile refining control')
       )) = 0);
  WR4: ( NOT( SELF\geometric_tolerance.name = 
       'linear profile refinement')) OR
       ( SIZEOF (QUERY( gtr <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'GEOMETRIC_TOLERANCE_RELATIONSHIP.RELATING_GEOMETRIC_TOLERANCE') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LINEAR_PROFILE_TOLERANCE' IN 
       TYPEOF(gtr.relating_geometric_tolerance))
       AND (gtr.related_geometric_tolerance\geometric_tolerance.name = 
       'linear profile refinement')
       AND (gtr\geometric_tolerance_relationship.name = 'linear profile refining control'))
       )) <= 1);
  WR5: NOT('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MODIFIED_GEOMETRIC_TOLERANCE' IN TYPEOF(SELF));
END_ENTITY; -- linear_profile_tolerance
(*

EXPRESS specification:

*)
ENTITY luminous_flux_measure_with_unit
 SUBTYPE OF (measure_with_unit);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\measure_with_unit ||
       SELF\luminous_flux_measure_with_unit))) = 0;
  WR2: SELF\measure_with_unit.unit_component\si_unit.name = lumen;
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SI_UNIT' IN 
       TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY; -- luminous_flux_measure_with_unit
(*

EXPRESS specification:

*)
ENTITY magnetic_flux_density_measure_with_unit
 SUBTYPE OF (measure_with_unit);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\measure_with_unit ||
       SELF\magnetic_flux_density_measure_with_unit))) = 0;
  WR2: SELF\measure_with_unit.unit_component\si_unit.name = tesla;
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SI_UNIT' IN 
       TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY; -- magnetic_flux_density_measure_with_unit
(*

EXPRESS specification:

*)
ENTITY magnetic_flux_measure_with_unit
 SUBTYPE OF (measure_with_unit);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\measure_with_unit ||
       SELF\magnetic_flux_measure_with_unit))) = 0;
  WR2: SELF\measure_with_unit.unit_component\si_unit.name = weber;
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SI_UNIT' IN 
       TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY; -- magnetic_flux_measure_with_unit
(*

EXPRESS specification:

*)
ENTITY make_from_connectivity_relationship
 SUBTYPE OF (shape_aspect_relationship);
WHERE
  WR1: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_CONNECTIVITY_DEFINITION'
       IN TYPEOF (SELF.relating_shape_aspect);
  WR2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_CONNECTIVITY_DEFINITION'
       IN TYPEOF (SELF.related_shape_aspect);
END_ENTITY; -- make_from_connectivity_relationship
(*

EXPRESS specification:

*)
ENTITY make_from_feature_relationship
 SUBTYPE OF (shape_aspect, shape_aspect_relationship);
WHERE
  WR1: SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_INTERFACE_TERMINAL',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_SHAPE_ASPECT'] *
       TYPEOF (SELF.relating_shape_aspect)) = 1;
  WR2: SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_INTERFACE_TERMINAL',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_SHAPE_ASPECT'] *
       TYPEOF (SELF.related_shape_aspect)) = 1;
  WR3: (NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_SHAPE_ASPECT' IN
       TYPEOF (SELF.relating_shape_aspect))) OR
       (SELF.relating_shape_aspect\shape_aspect.description IN ['component feature',
       'component termination passage interface terminal', 
       'land or non functional land interface terminal',  
       'printed connector component interface terminal']);
  WR4: (NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_SHAPE_ASPECT' IN
       TYPEOF (SELF.related_shape_aspect))) OR
       (SELF.related_shape_aspect\shape_aspect.description IN ['component feature',
       'component termination passage interface terminal', 
       'land or non functional land interface terminal',  
       'printed connector component interface terminal']);
END_ENTITY; -- make_from_feature_relationship
(*

EXPRESS specification:

*)
ENTITY make_from_functional_unit_terminal_definition_relationship
 SUBTYPE OF (shape_aspect, shape_aspect_relationship);
UNIQUE
  UR1: SELF\shape_aspect_relationship.relating_shape_aspect, 
       SELF\shape_aspect_relationship.related_shape_aspect;
WHERE
  WR1: SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FUNCTIONAL_UNIT_TERMINAL_DEFINITION'] *
       TYPEOF (SELF.relating_shape_aspect)) = 1;
  WR2: SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FUNCTIONAL_UNIT_TERMINAL_DEFINITION'] *
       TYPEOF (SELF.related_shape_aspect)) = 1;
  WR3: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\shape_aspect_relationship ||
    SELF\make_from_functional_unit_terminal_definition_relationship)) = 0;
  WR4: relating_shape_aspect.of_shape :<>: 
       related_shape_aspect.of_shape;
  WR5: SELF\shape_aspect.name = '';
  WR6: SELF\shape_aspect.description = '';
  WR7: SELF\shape_aspect.product_definitional = FALSE;
  WR8: SIZEOF (USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION')) = 0;
  WR9: SIZEOF (QUERY( sar <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESIGN_MAKE_FROM_RELATIONSHIP') IN TYPEOF
       (sar.of_shape\property_definition.definition))
       )) = 1;


END_ENTITY; -- make_from_functional_unit_terminal_definition_relationship
(*

EXPRESS specification:

*)
ENTITY make_from_model_port_relationship
 SUBTYPE OF (representation, representation_relationship);
UNIQUE
  UR1: SELF\representation_relationship.rep_1, 
       SELF\representation_relationship.rep_2;
WHERE
  WR1: SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ANALYTICAL_MODEL_PORT'] *
       TYPEOF (SELF.rep_1)) = 1;
  WR2: SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ANALYTICAL_MODEL_PORT'] *
       TYPEOF (SELF.rep_2)) = 1;
  WR3: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\representation ||
       SELF\representation_relationship ||
       SELF\make_from_model_port_relationship)) = 0;
  WR4: rep_1 :<>: rep_2;
  WR5: SIZEOF(QUERY( rr1 <* USEDIN(SELF.rep_1,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION_RELATIONSHIP.REP_2') |
        (SIZEOF(QUERY(rr2 <* USEDIN(SELF.rep_2,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION_RELATIONSHIP.REP_2') | 
        (rr1.rep_1 :=: rr2.rep_1)
        )) = 0))) = 1;
  WR6: SIZEOF (QUERY( rr <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION_RELATIONSHIP.REP_2') | 
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ANALYTICAL_MODEL_MAKE_FROM_RELATIONSHIP') IN TYPEOF (rr.rep_1))
       )) = 1; 
       
END_ENTITY; -- make_from_model_port_relationship
(*

EXPRESS specification:

*)
ENTITY make_from_part_feature_relationship
 SUBTYPE OF (shape_aspect, shape_aspect_relationship);
UNIQUE
  UR1: SELF\shape_aspect_relationship.relating_shape_aspect, 
       SELF\shape_aspect_relationship.related_shape_aspect;
WHERE
  WR1: SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_INTERFACE_TERMINAL',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_SHAPE_ASPECT'] *
       TYPEOF (SELF.relating_shape_aspect)) = 0;
  WR2: SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_INTERFACE_TERMINAL',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_SHAPE_ASPECT'] *
       TYPEOF (SELF.related_shape_aspect)) = 0;
  WR3: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\shape_aspect_relationship ||
       SELF\make_from_part_feature_relationship)) = 0;
  WR4: SELF.related_shape_aspect.product_definitional = TRUE;
  WR5: SELF.relating_shape_aspect.product_definitional = TRUE;
  WR6: SELF\shape_aspect.name = '';
  WR7: SELF\shape_aspect.description = '';
  WR8: SELF\shape_aspect.product_definitional = FALSE;
  WR9: SIZEOF (USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION')) = 0;
 WR10: SIZEOF (QUERY( sar <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESIGN_MAKE_FROM_RELATIONSHIP') IN TYPEOF
       (sar.of_shape\property_definition.definition))
       )) = 1;
END_ENTITY; -- make_from_part_feature_relationship 
(* 

EXPRESS specification:

*)
ENTITY manifold_constraining_context_dependent_shape_representation
  SUBTYPE OF (context_dependent_shape_representation, representation_relationship);
END_ENTITY; -- manifold_constraining_context_dependent_shape_representation 
(* 

EXPRESS specification:

*)
ENTITY material_electrical_conductivity_category
  SUBTYPE OF (group);
WHERE
  WR1: SELF\group.name IN ['conductive', 'non conductive', 'resistive',  
       'semi conductive'];
END_ENTITY; -- material_electrical_conductivity_category
(*

EXPRESS specification:

*)
ENTITY material_functional_category
  SUBTYPE OF (group);
WHERE
  WR1: SELF\group.name IN 
     ['bonding agent', 'potting compound', 'marking material'];
END_ENTITY; -- material_functional_category
(*

EXPRESS specification:

*)
ENTITY material_optical_conductivity_category
  SUBTYPE OF (group);
WHERE
  WR1: SELF\group.name IN ['conductive', 'non conductive', 'resistive',  
       'semi conductive'];
END_ENTITY; -- material_optical_conductivity_category
(*

EXPRESS specification:

*)
ENTITY material_removal_component_shape_aspect
  SUBTYPE OF (component_shape_aspect);
END_ENTITY; -- material_removal_component_shape_aspect
(*

EXPRESS specification:

*)
ENTITY material_thermal_conductivity_category
  SUBTYPE OF (group);
WHERE
  WR1: SELF\group.name IN ['conductive', 'non conductive', 'resistive',  
       'semi conductive'];
END_ENTITY; -- material_thermal_conductivity_category
(*

EXPRESS specification:

*)
ENTITY minimally_defined_bare_die_terminal
  SUPERTYPE OF (bare_die_terminal)
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'BARE_DIE' IN 
       TYPEOF (SELF.of_shape.definition);
  WR2: SIZEOF (QUERY (eca <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'external connection area') |
       eca.related_shape_aspect\shape_aspect.description = 'connection zone')) <= 1;
  WR3: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MATERIAL_DESIGNATION.DEFINITIONS')) <= 1;
  WR4: SIZEOF (QUERY (mct <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'member connected terminal') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PART_CONNECTED_TERMINALS_DEFINITION'
       IN TYPEOF (mct.relating_shape_aspect))) <= 1;
END_ENTITY; -- minimally_defined_bare_die_terminal
(*

EXPRESS specification:

*)
ENTITY model_parameter 
 SUBTYPE OF (representation_item);
WHERE
  WR1: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_DOCUMENT_REFERENCE.ITEMS')) = 1;
  WR2: SIZEOF (QUERY (cri <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION.ITEMS') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COORDINATED_REPRESENTATION_ITEM' IN TYPEOF(cri)) AND 
       (cri\representation.name = 
       'model parameter with valid range value'))) <= 1;
  WR3: SIZEOF (QUERY (aga <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_GROUP_ASSIGNMENT.ITEMS') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PARAMETER_TYPE' IN 
       TYPEOF (aga.assigned_group)) AND
       (aga.assigned_group\group.name IN ['string property type', 
       'logical property type', 'physical property type', 
       'boolean property type']))) = 1;
END_ENTITY; -- model_parameter
(*

EXPRESS specification:

*)
ENTITY mounting_restriction_area
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: EXISTS(SELF.of_shape.definition\product_definition.name);
  WR2: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_UNIT' IN TYPEOF (SELF.of_shape.definition));

  WR3: SELF.of_shape.definition.frame_of_reference.name IN ['physical design'];

  WR4: SELF.of_shape.definition\product_definition.name = 'assembly module';

  WR5: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_REPRESENTATION' IN 
       TYPEOF (pdr.used_representation)) AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'CSG_2D_SHAPE_REPRESENTATION' IN 
       TYPEOF (pdr.used_representation)))) = 1))) = 0;
  WR6: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       ((sar\shape_aspect_relationship.name = 'mounting surface') AND 
       (sar.related_shape_aspect\shape_aspect.description =
       'interconnect module component surface feature')))) = 1;
  WR7: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\shape_aspect ||
       SELF\mounting_restriction_area))) = 0;

END_ENTITY; -- mounting_restriction_area
(*

EXPRESS specification:

*)
ENTITY mounting_restriction_volume
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_UNIT' IN TYPEOF (SELF.of_shape.definition));

  WR2: SELF.of_shape.definition.frame_of_reference.name IN ['physical design'];

  WR3: SELF.of_shape.definition.name = 'assembly module';

  WR4: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_REPRESENTATION' IN 
       TYPEOF (pdr.used_representation)) AND
        (pdr.used_representation\representation.context_of_items\
       geometric_representation_context.coordinate_space_dimension = 3)
       )) = 1))) = 0;

  WR5: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_SHAPE_ASPECT' IN
       TYPEOF (sar.related_shape_aspect)) AND
       (sar\shape_aspect_relationship.name = 'mounting surface') AND 
       (sar.related_shape_aspect\shape_aspect.description =
       'interconnect module component surface feature'))) = 1;
  WR6: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\shape_aspect ||
       SELF\mounting_restriction_volume))) = 0;
END_ENTITY; -- mounting_restriction_volume
(*

EXPRESS specification:

*)
ENTITY multi_layer_component_shape_aspect
  SUBTYPE OF (component_shape_aspect);
END_ENTITY; -- multi_layer_component_shape_aspect
(*

EXPRESS specification:

*)
ENTITY multi_layer_material_removal_component_shape_aspect
  SUBTYPE OF (material_removal_component_shape_aspect);
END_ENTITY; -- multi_layer_material_removal_component_shape_aspect
(*

EXPRESS specification:

*)
ENTITY multi_layer_stratum_feature
 SUBTYPE OF (stratum_feature);
END_ENTITY; -- multi_layer_stratum_feature
(*

EXPRESS specification:

*)
ENTITY network_node_definition
  SUBTYPE OF (product_definition);
WHERE
  WR1: SELF.frame_of_reference.name = 'functional network design';
  WR2: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (funtdna <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATING_PROPERTY_DEFINITION') |
       pdr\property_definition_relationship.name =
       'functional unit network terminal definition node assignment') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_SHAPE' IN 
       TYPEOF (funtdna.related_property_definition)) AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'FUNCTIONAL_UNIT_TERMINAL_DEFINITION' IN 
       TYPEOF 
       (funtdna.related_property_definition.definition)))) <= 1)) <= 1;
  WR3: SIZEOF (QUERY (funn <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FUNCTIONAL_UNIT' IN 
       TYPEOF (funn.relating_product_definition)) AND
       (funn.relating_product_definition.frame_of_reference.name =
       'functional network design'))) = 1;
END_ENTITY; -- network_node_definition
(*

EXPRESS specification:

*)
ENTITY opposing_boundary_dimensional_size
  SUBTYPE OF (dimensional_size);
WHERE
    wr1: SELF\dimensional_size.name  IN ['angular', 'linear'];
END_ENTITY; -- opposing_boundary_dimensional_size
(*

EXPRESS specification:

*)
ENTITY owner_assignment 
 SUBTYPE OF (person_and_organization_assignment); 
 items : SET [1:?] OF owner_assigned_item; 
END_ENTITY; -- owner_assignment
(*

EXPRESS specification:

*)
ENTITY package
 SUBTYPE OF (physical_unit);
WHERE
  WR1: SELF.frame_of_reference.name = 'physical design usage';
  -- WR2 deleleted
  WR3: SIZEOF (QUERY (pd <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE_BODY' IN 
       TYPEOF (sa))) = 1))) <= 1;
  WR4: SIZEOF (QUERY (pd <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE_TERMINAL' IN 
       TYPEOF (sa))) >= 1))) >= 1;
  WR5: (NOT (SELF\product_definition.description = 'altered package')) OR
       (SIZEOF (QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       (pdr\product_definition_relationship.name = 'package alteration') AND
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PACKAGE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_PACKAGE'] * 
       TYPEOF (pdr.relating_product_definition)) = 1))) = 1); 
  WR6: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       pdr.used_representation\representation.name = 'package mounting data')) = 1))) = 1;

  WR7: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       (pdr.used_representation\representation.name = 'package mounting data')
       AND (SIZEOF (QUERY (item <* USEDIN( pdr.used_representation,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION.ITEMS') | item\representation_item.name =
       'maximum body height above seating plane')) = 1)
       )) = 1))) = 1;

  WR8: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       (pdr.used_representation\representation.name = 'package mounting data')
       AND (SIZEOF (QUERY (item <* USEDIN( pdr.used_representation,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION.ITEMS') | item\representation_item.name =
       'maximum body height below seating plane')) = 1)
       )) = 1))) <= 1;

  WR9: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       (pdr.used_representation\representation.name = 'package mounting data')
       AND (SIZEOF (QUERY (item <* USEDIN( pdr.used_representation,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION.ITEMS') | item\representation_item.name =
       'maximum body clearance above seating plane')) = 1)
       )) = 1))) <= 1;

  WR10: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       (pdr.used_representation\representation.name = 'package mounting data')
       AND (SIZEOF (QUERY (item <* USEDIN( pdr.used_representation,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION.ITEMS') | item\representation_item.name =
       'maximum body clearance below seating plane')) = 1)
       )) = 1))) <= 1;

  WR11: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       (pdr.used_representation\representation.name = 'package mounting data')
       AND (SIZEOF (QUERY (item <* USEDIN( pdr.used_representation,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION.ITEMS') | item\representation_item.name =
       'minimum body clearance above seating plane')) = 1)
       )) = 1))) <= 1;

  WR12: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       (pdr.used_representation\representation.name = 'package mounting data')
       AND (SIZEOF (QUERY (item <* USEDIN( pdr.used_representation,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION.ITEMS') | item\representation_item.name =
       'minimum body clearance below seating plane')) = 1)
       )) = 1))) <= 1;

  WR13: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       (pdr.used_representation\representation.name = 'package mounting data')
       AND (SIZEOF (QUERY (item <* USEDIN( pdr.used_representation,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION.ITEMS') | item\representation_item.name =
       'maximum lead length below seating plane')) = 1)
       )) = 1))) <= 1;

  WR14: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       (pdr.used_representation\representation.name = 'package mounting data')
       AND (SIZEOF (QUERY (item <* USEDIN( pdr.used_representation,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION.ITEMS') | item\representation_item.name =
       'least lead length below seating plane')) = 1)
       )) = 1))) <= 1;
  WR15: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT' IN TYPEOF(sa)) AND
       (SIZEOF (QUERY ( sar <* USEDIN(sa,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
        ((sar\shape_aspect_relationship.name = 'package seating plane') AND
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SEATING_PLANE' IN TYPEOF(sar.related_shape_aspect))) )) = 1))
       )) = 1)
       )
       ) = 1;

  WR16: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SEATING_PLANE' IN
       TYPEOF (sa)))) = 1))) = 1;

  WR17: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT' IN TYPEOF(sa)) AND
       (SIZEOF (QUERY ( sar <* USEDIN(sa,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
        ((sar\shape_aspect_relationship.name = 'of datum reference plane') AND
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DATUM_REFERENCE_FRAME' IN TYPEOF(sar.related_shape_aspect))) )) = 1))
       )) = 1)
       )
       ) <= 1;
 WR18: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRIMARY_REFERENCE_TERMINAL' IN TYPEOF(sa))
       )) = 1)
       )
       ) <= 1;
END_ENTITY; -- package
(*

EXPRESS specification:

*)
ENTITY package_body
 SUBTYPE OF (shape_aspect);
WHERE
  WR1: SIZEOF (TYPEOF (SELF.of_shape.definition) *
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PACKAGE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_PACKAGE']) = 1;
  WR2: SIZEOF (USEDIN (SELF, 
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MATERIAL_DESIGNATION.DEFINITIONS')) = 1;
END_ENTITY; -- package_body
(*

EXPRESS specification:

*)
ENTITY package_body_bottom_surface
 SUBTYPE OF (package_body_surface);
END_ENTITY; -- package_body_bottom_surface
(*

EXPRESS specification:

*)
ENTITY package_body_edge_segment_surface
  SUBTYPE OF (shape_aspect, shape_aspect_relationship);
WHERE
  wr1: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_SEGMENT_VERTEX' IN
       TYPEOF (SELF\shape_aspect_relationship.related_shape_aspect);
  wr2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EDGE_SEGMENT_VERTEX' IN
       TYPEOF (SELF\shape_aspect_relationship.relating_shape_aspect);
  wr3: SELF\shape_aspect_relationship.relating_shape_aspect :<>:
       SELF\shape_aspect_relationship.related_shape_aspect;
  WR4: SIZEOF (QUERY (ce <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'composed surface') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE_BODY_EDGE_SURFACE' IN TYPEOF
       (ce.relating_shape_aspect) ))) = 1;
  WR5: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\shape_aspect_relationship ||
       SELF\package_body_edge_segment_surface)) = 0;
END_ENTITY; -- package_body_edge_segment_surface
(*

EXPRESS specification:

*)
ENTITY package_body_edge_surface
 SUBTYPE OF (package_body_surface);
WHERE
  WR1: SELF\shape_aspect.product_definitional;
  WR2: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\part_mounting_feature ||
       SELF\package_body_edge_surface ||
       SELF\package_body_surface)) = 0;
END_ENTITY; -- package_body_edge_surface
(*

EXPRESS specification:

*)
ENTITY package_body_surface
ABSTRACT SUPERTYPE OF (ONEOF(package_body_top_surface,
                         package_body_edge_surface,
                         package_body_bottom_surface))
 SUBTYPE OF (shape_aspect);
WHERE
  WR1: SIZEOF (TYPEOF (SELF.of_shape.definition) *
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PACKAGE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_PACKAGE']) = 1;
  WR2: SELF\shape_aspect.product_definitional;
  WR3: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       (TYPEOF(sar\shape_aspect_relationship.relating_shape_aspect) = 
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE_BODY']))) = 1;
END_ENTITY; -- package_body_surface
(*

EXPRESS specification:

*)
ENTITY package_body_top_surface
 SUBTYPE OF (package_body_surface);
END_ENTITY; -- package_body_top_surface
(*

EXPRESS specification:

*)
ENTITY package_terminal
 SUPERTYPE OF (((altered_package_terminal ANDOR guided_wave_terminal)
      ANDOR wire_terminal) ANDOR primary_reference_terminal)
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_REPRESENTATION' IN
       TYPEOF (pdr.used_representation))) >= 1))) = 0;
  WR2: SIZEOF (TYPEOF (SELF.of_shape.definition) *
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PACKAGE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_PACKAGE']) = 1;
  WR3: SIZEOF (QUERY (sar <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |(
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION' IN TYPEOF (sar.relating_shape_aspect.of_shape.definition)) AND
       (sar\shape_aspect_relationship.name = 'terminal core material') AND
       (sar.relating_shape_aspect.of_shape.definition.
        frame_of_reference\application_context_element.name = 'material definition') 
       )) <= 1;
  WR4: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |(
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION' IN TYPEOF (sar.relating_shape_aspect.of_shape.definition)) AND
       (sar\shape_aspect_relationship.name = 'terminal surface material') AND
       (sar.relating_shape_aspect.of_shape.definition.
        frame_of_reference\application_context_element.name = 'material definition') 
       )) = 1;
  WR5: SIZEOF (QUERY (mct <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'member connected terminal') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PART_CONNECTED_TERMINALS_DEFINITION'
       IN TYPEOF (mct.relating_shape_aspect))) <= 1;
 WR6: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       (sar\shape_aspect_relationship.name  = 'external connection zone') AND
       (sar.related_shape_aspect\shape_aspect.description = 'connection zone'))) >= 0;
 WR7: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (lmwu <* QUERY (it <* pdr.used_representation.items |
       SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] *
       TYPEOF (it)) = 2) |
       lmwu\representation_item.name = 'maximum terminal diametrical extent')) 
        <= 1)) <= 1)) <= 1;
 WR8: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (lmwu <* QUERY (it <* pdr.used_representation.items |
       SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] *
       TYPEOF (it)) = 2) |
       lmwu\representation_item.name = 'minimum terminal diametrical extent')) 
         <= 1)) <= 1)) <= 1;
 WR9: SIZEOF(QUERY ( sar <* USEDIN (SELF,
      'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
      'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'precedent feaure' ))
       <= 1;
 WR10: SIZEOF(QUERY ( sar <* USEDIN (SELF,
      'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
      'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'precedent feaure' ))
       <= 1;
 WR11: SIZEOF (QUERY (eca <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'seating plane zone') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'CONNECTION_ZONE_INTERFACE_PLANE_RELATIONSHIP' IN
       TYPEOF (eca.related_shape_aspect))) <= 1;
END_ENTITY; -- package_terminal
(*

EXPRESS specification:

*)
ENTITY packaged_component
  SUBTYPE OF (component_definition);
WHERE
  WR1: SIZEOF (QUERY (ip <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'instantiated part') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_PART',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PACKAGED_PART',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_PACKAGED_PART'] *
       TYPEOF (ip.relating_product_definition)) = 1) AND
       (ip.relating_product_definition.frame_of_reference.name =
       'physical design usage'))) = 1;
  WR2: SIZEOF (QUERY (pa <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'package alternate') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PACKAGE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_PACKAGE'] *
       TYPEOF (pa.relating_product_definition)) = 1) AND
       (pa.relating_product_definition\product_definition.description =
       'altered package'))) <= 1;
  WR3: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL' IN
       TYPEOF (sa)) AND
       (sa\shape_aspect.description = 'packaged component join terminal'))) >= 1))) = 0;
  WR4: (NOT (SELF\product_definition.description = 'packaged connector component')) OR
       (SIZEOF (QUERY (ip <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'instantiated part') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_PART',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PACKAGED_PART',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_PACKAGED_PART'] *
       TYPEOF (ip.relating_product_definition)) = 1) AND
       (TRUE))) = 1);
  WR5: (NOT (SELF\product_definition.description = 'packaged connector component')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL' IN
       TYPEOF (sa)) AND
       (sa\shape_aspect.description = 'packaged component join terminal'))) 
        >= 1))) = 0);
  WR6: (NOT (SELF\product_definition.description = 'routed packaged component')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       SIZEOF (QUERY (pd <* USEDIN (sa,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (USEDIN (pd, 
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')) 
       = 1)) = 1)) = 1))) = 0);
END_ENTITY; -- packaged_component
(*

EXPRESS specification:

*)
ENTITY packaged_connector
  SUBTYPE OF (packaged_part);
WHERE
  WR1: SIZEOF (QUERY (pd <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_CONNECTOR_TERMINAL_RELATIONSHIP' IN
       TYPEOF (sa)))) = 1))) >= 1;

  WR2: SIZEOF (QUERY (pd <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       (SIZEOF (QUERY ( sar <* USEDIN(sa,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
        sar\shape_aspect_relationship.name = 'interface plane')) = 1)
       )) = 1)
       )
       ) <= 1;

  WR3: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SEATING_PLANE' IN
       TYPEOF (sa)))) = 1))) <= 1;

END_ENTITY; -- packaged_connector
(*

EXPRESS specification:

*)
ENTITY packaged_connector_terminal_relationship
 SUBTYPE OF (shape_aspect, shape_aspect_relationship);
WHERE
  WR1: (SIZEOF (TYPEOF (SELF.of_shape.definition) *
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_PART',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PACKAGED_PART',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_PACKAGED_PART']) 
       = 1) AND
       (SELF.of_shape.definition\product_definition.description =
       'packaged connector');
  WR2: (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_PART_TERMINAL' IN 
       TYPEOF (SELF\shape_aspect_relationship.related_shape_aspect)) AND
       (SELF\shape_aspect_relationship.related_shape_aspect\shape_aspect.description 
        = 'interface terminal'));
  WR3: (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_PART_TERMINAL' IN 
       TYPEOF (SELF\shape_aspect_relationship.related_shape_aspect)) AND
       (SELF\shape_aspect_relationship.related_shape_aspect\shape_aspect.description 
        = 'join terminal'));
END_ENTITY; -- packaged_connector_terminal_relationship
(*

EXPRESS specification:

*)
ENTITY packaged_part
 SUPERTYPE OF (packaged_connector)
 SUBTYPE OF (physical_unit);
WHERE 
  WR1: SIZEOF (QUERY (pd <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_PART_TERMINAL' IN 
       TYPEOF (sa))) >= 0))) = 0;
  WR2: SIZEOF (USEDIN (SELF, 
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MATERIAL_DESIGNATION.DEFINITIONS')) <= 1;
  WR3: SIZEOF (QUERY (ifu <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'implemented function') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FUNCTIONAL_UNIT' IN
       TYPEOF (ifu.relating_product_definition)) AND
       (ifu.relating_product_definition.frame_of_reference.name =
       'functional design usage'))) <= 1;
  WR4: NOT(EXISTS(SELF\product_definition.description)) OR
       ((NOT (SELF\product_definition.description = 'altered packaged part')) OR
       (SIZEOF (QUERY (bpp <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'base packaged part') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_PART',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PACKAGED_PART',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_PACKAGED_PART'] * 
       TYPEOF (bpp.relating_product_definition)) = 1) AND
       (bpp.relating_product_definition.frame_of_reference.name =
       'physical design usage'))) >= 1));
  WR5: SIZEOF (QUERY (upkg <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'used package') |
       SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PACKAGE',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_PACKAGE'] * 
       TYPEOF (upkg.relating_product_definition)) = 1)) >= 1;
  WR6: SELF.frame_of_reference.name = 'physical design usage';
END_ENTITY; -- packaged_part
(*

EXPRESS specification:

*)
ENTITY packaged_part_terminal
 SUBTYPE OF (shape_aspect);
WHERE
  WR1: SELF\shape_aspect.description IN ['interface terminal', 
       'join terminal'];
  WR2: (SIZEOF (TYPEOF (SELF.of_shape.definition) *
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_PART',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PACKAGED_PART',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_PACKAGED_PART']) 
       = 1) AND
  (SELF.of_shape.definition\product_definition.frame_of_reference.name = 
       'physical design usage');
  WR3: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_REPRESENTATION' IN
       TYPEOF (pdr.used_representation))) >= 1))) = 0;
  WR4: SIZEOF (QUERY (top <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'terminal of package') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE_TERMINAL' IN
       TYPEOF (top.related_shape_aspect))) >= 1;
  WR5: SIZEOF (QUERY (mct <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'member connected terminal') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PART_CONNECTED_TERMINALS_DEFINITION'
       IN TYPEOF (mct.relating_shape_aspect))) <= 1;
  WR6: (NOT(SELF\shape_aspect.description = 'interface terminal')) OR
       (SIZEOF(QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_CONNECTOR_TERMINAL_RELATIONSHIP' IN TYPEOF(sar))
       AND (sar.relating_shape_aspect\shape_aspect.description = 
       'join terminal'))) >= 1);
  WR7: (NOT(SELF\shape_aspect.description = 'join terminal')) OR
       (SIZEOF(QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_CONNECTOR_TERMINAL_RELATIONSHIP' IN TYPEOF(sar))
       AND (sar.relating_shape_aspect\shape_aspect.description = 
        'interface terminal'))) <= 1);
END_ENTITY; -- packaged_part_terminal
(*

EXPRESS specification:

*)
ENTITY padstack_definition
 SUPERTYPE OF (ONEOF( design_layer_type_specific_padstack_definition,
               stratum_occurrence_specific_padstack_definition,
               stratum_type_independent_padstack_definition))
 SUBTYPE OF (product_definition);
WHERE
  WR1: (NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_WITH_ASSOCIATED_DOCUMENTS' IN 
       TYPEOF (SELF))) OR
       (SIZEOF (QUERY (docs <* 
       SELF\product_definition_with_associated_documents.
        documentation_ids |
       docs.kind\document_type.product_data_type = 'CAD filename')) <= 1);
  WR2: SIZEOF (QUERY (adta <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'APPLIED_DATE_AND_TIME_ASSIGNMENT.ITEMS') |
       adta.role\date_time_role.name = 'creation date')) + 
       SIZEOF (QUERY (ada <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'APPLIED_DATE_ASSIGNMENT.ITEMS') |
       ada.role\date_role.name = 'creation date')) = 1;
  WR3: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_APPROVAL_ASSIGNMENT.ITEMS')) = 1;
  WR4: SIZEOF (QUERY (apoa <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_PERSON_AND_ORGANIZATION_ASSIGNMENT.ITEMS') |
       apoa.role\person_and_organization_role.name = 'creator')) +
       SIZEOF (QUERY (apoa <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_ORGANIZATION_ASSIGNMENT.ITEMS') |
       apoa.role\organization_role.name = 'creator')) >= 1;
  WR5: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_SECURITY_CLASSIFICATION_ASSIGNMENT.ITEMS')) = 1;
  WR6: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\product_definition ||
       SELF\padstack_definition))) = 0;
  WR7: SELF.frame_of_reference.name IN ['layout design usage' ];
  WR9: SIZEOF (QUERY (prpc <* USEDIN (SELF.formation.of_product,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_RELATED_PRODUCT_CATEGORY.' +
       'PRODUCTS') |
       prpc\product_category.name = 'template model')) = 1;
END_ENTITY; -- padstack_definition
(*

EXPRESS specification:

*)
ENTITY padstack_occurrence
  SUBTYPE OF (assembly_group_component_shape_aspect);
END_ENTITY; -- padstack_occurrence
(*

EXPRESS specification:

*)
ENTITY padstack_occurrence_shape_aspect_relationship
  SUBTYPE OF (shape_aspect_relationship);
WHERE
  WR1: SELF\shape_aspect_relationship.related_shape_aspect :<>:
       SELF\shape_aspect_relationship.relating_shape_aspect;
  WR2: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\shape_aspect_relationship ||
       SELF\padstack_occurrence_shape_aspect_relationship)) = 0;
  WR3: SELF\shape_aspect_relationship.name = 'padstack occurrence sub assembly relationship';
END_ENTITY; -- padstack_occurrence_shape_aspect_relationship 
(* 

EXPRESS specification:

*)
ENTITY parallelism_tolerance
  SUBTYPE OF (geometric_tolerance_with_specified_datum_system);
WHERE
  WR1: SELF\geometric_tolerance.name = 'parallelism';
END_ENTITY; -- parallelism_tolerance
(*

EXPRESS specification:

*)
ENTITY parameter_assignment_representation
  SUBTYPE OF (representation);
WHERE
  WR1: SIZEOF (SELF.items) = 2;
  WR2: SIZEOF (QUERY (it <* SELF.items |
       (SIZEOF (TYPEOF (it) *
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MODEL_PARAMETER']) 
       = 1))) = 1;
  WR3: SIZEOF (QUERY (it <* SELF.items |
       (SIZEOF (TYPEOF (it) *
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COORDINATED_REPRESENTATION_ITEM']) 
       = 1))) <= 1;
  WR4: SIZEOF (QUERY (it <* SELF.items |
        (SIZEOF (QUERY(aga <* USEDIN (it,
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'APPLIED_GROUP_ASSIGNMENT.ITEMS') |
             (SIZEOF (TYPEOF ( aga\group_assignment.assigned_group) *
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'CHARACTERISTIC_TYPE']) = 1))) 
       = 1))) <= 1;
  WR5: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\representation ||
       SELF\parameter_assignment_representation)) = 0; 
END_ENTITY; -- parameter_assignment_representation
(*

EXPRESS specification:

*)
ENTITY parameter_type
  SUBTYPE OF (group);
WHERE
  WR1: SELF\group.name IN ['string property type','logical property type',
       'physical property type','boolean property type'];
END_ENTITY; -- parameter_type
(*

EXPRESS specification:

*)
ENTITY part_connected_terminals_definition
  SUBTYPE OF (shape_aspect);
UNIQUE
  UR1: SELF\shape_aspect.name;
WHERE
  WR1: SIZEOF (QUERY (mct <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'member connected terminal') |
       SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_MODULE_TERMINAL',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'BARE_DIE_TERMINAL',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'INTERCONNECT_MODULE_TERMINAL',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE_TERMINAL',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGED_PART_TERMINAL'] *
       TYPEOF (mct.related_shape_aspect)) = 1)) >= 2;
END_ENTITY; -- part_connected_terminals_definition
(*

EXPRESS specification:

*)
ENTITY part_interface_access_feature
 SUBTYPE OF (shape_aspect);
WHERE
  WR1: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       (sar\shape_aspect_relationship.name  = 'interface_access area') AND
       (sar.related_shape_aspect\shape_aspect.description = 'connection zone'))) = 1;
END_ENTITY; -- part_interface_access_feature
(*

EXPRESS specification:

*)
ENTITY part_mating_feature
 SUBTYPE OF (shape_aspect);
WHERE
  WR1: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       (sar\shape_aspect_relationship.name  = 'mating area') AND
       (sar.related_shape_aspect\shape_aspect.description = 'connection zone'))) = 1;
END_ENTITY; -- part_mating_feature
(*

EXPRESS specification:

*)
ENTITY part_mounting_feature
 SUPERTYPE OF (bare_die_surface)
 SUBTYPE OF (shape_aspect);
WHERE
  WR1: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       (sar\shape_aspect_relationship.name  = 'mounting area') AND
       (sar.related_shape_aspect\shape_aspect.description = 'connection zone'))) = 1;
END_ENTITY; -- part_mounting_feature
(*

EXPRESS specification:

*)
ENTITY part_template_definition
  SUPERTYPE OF (dependent_material_removal_feature_template)
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: SELF\
       shape_aspect.of_shape\
       property_definition.definition.frame_of_reference\
       application_context_element.name = 'template definition';

  WR2: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ANALYTICAL_MODEL' IN 
       TYPEOF (pdr.used_representation)) AND
       (pdr.used_representation\representation.name = 'part template analytical model'))) 
       <= 1))) = 0;       

  WR3: (NOT (SELF\shape_aspect.description = 
         'component termination passage template')) OR
       (SIZEOF (QUERY (ctpt <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'inter stratum feature passage technology') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PASSAGE_TECHNOLOGY' IN
       TYPEOF (ctpt.relating_shape_aspect)) AND
       (ctpt.relating_shape_aspect\shape_aspect.description = 
       'default component termination passage definition'))) = 1);

  WR4: (NOT (SELF\shape_aspect.description = 
        'component termination passage template')) OR
       (SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'access mechanism') |
       am.related_shape_aspect\shape_aspect.description IN 
       ['component termination passage template interface terminal',
       'component termination passage template join terminal'])) >= 2);

  WR5: (NOT (SELF\shape_aspect.description = 'default trace template')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (tu <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION') |
       pdr\property_definition_relationship.name = 'technology usage') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'STRATUM_TECHNOLOGY' IN 
       TYPEOF (tu.relating_property_definition.definition))) = 1)) = 1);

  WR6: (NOT (SELF\shape_aspect.description = 'inter stratum feature template')) OR
       (SIZEOF (QUERY (isfpt <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'inter stratum feature passage technology') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PASSAGE_TECHNOLOGY' IN
       TYPEOF (isfpt.relating_shape_aspect)))) = 1);

  WR7: (NOT (SELF\shape_aspect.description = 'printed connector template')) OR
       (SIZEOF (QUERY (sar <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name IN 
       ['connector'])) >= 1);

  WR8: (NOT (SELF\shape_aspect.description = 'printed part cross section template')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ANALYTICAL_MODEL' IN 
       TYPEOF (pdr.used_representation)) AND
       (pdr.used_representation\representation.name = 'transmission line model'))) 
       = 1))) = 0);

  WR9: (NOT (SELF\shape_aspect.description = 'printed part cross section template')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] * 
       TYPEOF (it)) = 2)) = 2)) = 1))) = 0);

 WR10: (NOT (SELF\shape_aspect.description = 'printed part cross section template')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] * 
       TYPEOF (it)) = 2) AND (it\representation_item.name = 'maximum width'))) = 1
       )) = 1))) = 0);

 WR11: (NOT (SELF\shape_aspect.description = 'printed part cross section template')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] * 
       TYPEOF (it)) = 2) AND (it\representation_item.name = 'minimum width'))) = 1
       )) = 1))) = 0);

 WR12: (NOT (SELF\shape_aspect.description = 'printed part template')) OR
       (SIZEOF (QUERY (impl_func <* QUERY (pdr <* 
       USEDIN (SELF.of_shape.definition,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.' +
       'RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'implemented function') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'FUNCTIONAL_UNIT' IN 
       TYPEOF (impl_func.relating_product_definition)) AND
       (impl_func.relating_product_definition.frame_of_reference.name =
       'functional design usage'))) = 1);
 
 WR13: (NOT (SELF\shape_aspect.description = 'printed part template')) OR
       (SIZEOF (QUERY (ad <* QUERY (sar <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'associated definition') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_TERMINAL' IN 
       TYPEOF (ad.related_shape_aspect)) AND
       (ad.related_shape_aspect\shape_aspect.description IN 
       ['interface terminal', 'join terminal']))) >= 2);

 WR14: (NOT (SELF\shape_aspect.description = 'trace template')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       pdr.used_representation\representation.name = 'curve style parameters'
       )) = 1 ) )) = 1 );  

 WR15: (NOT (SELF\shape_aspect.description = 'unsupported passage template')) OR
       (SIZEOF (QUERY (upt <* QUERY (sar <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'inter stratum feature passage technology') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PASSAGE_TECHNOLOGY' IN 
       TYPEOF (upt.relating_shape_aspect)) AND
       (upt.relating_shape_aspect\shape_aspect.description = 
       'default unsupported passage definition'))) = 1);

 WR16: (NOT (SELF\shape_aspect.description = 'via template')) OR
       (SIZEOF (QUERY (vpt <* QUERY (sar <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'inter stratum feature passage technology') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PASSAGE_TECHNOLOGY' IN 
       TYPEOF (vpt.relating_shape_aspect)) AND
       (vpt.relating_shape_aspect\shape_aspect.description = 
       'default via definition'))) = 1);

 WR17: (NOT (SELF\shape_aspect.description = 'via template')) OR
       (SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'access mechanism') |
       am.related_shape_aspect\shape_aspect.description =
                                 'via template terminal')) >= 2);

 WR18: EXISTS(SELF\shape_aspect.name);

 WR19: (NOT (SELF\shape_aspect.description = 'non conductive cross section template')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (tu <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION') |
       pdr\property_definition_relationship.name = 'technology usage') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'STRATUM_TECHNOLOGY' IN
       TYPEOF (tu.relating_property_definition.definition)))) = 1)) = 1);

 WR20: (NOT (SELF\shape_aspect.description = 'non conductive cross section template')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] *
       TYPEOF (it)) = 2) AND (it\representation_item.name = 'nominal width'))) = 1
       )) = 1))) = 0);

 WR21: (NOT (SELF\shape_aspect.description = 'printed connector template')) OR
       (SIZEOF (QUERY (ad <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'associated definition') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_TERMINAL' IN
       TYPEOF (ad.related_shape_aspect)) AND
       (ad.relating_shape_aspect\shape_aspect.description IN
       ['interface terminal', 'join terminal']))) >= 2);

 WR22: (NOT (SELF\shape_aspect.description = 
                         'printed part cross section template')) OR
       (SIZEOF (QUERY (ad <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'horizontal material link') |
       NOT(('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (ad.relating_shape_aspect)) AND
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'TEMPLATE_MATERIAL_CROSS_SECTION_BOUNDARY' IN
       TYPEOF (ad.relating_shape_aspect\shape_aspect_relationship.
                                                   related_shape_aspect)) AND
       (ad.relating_shape_aspect\shape_aspect_relationship.
                 related_shape_aspect\shape_aspect.description = 'left'))))) = 0); 

 WR27: (NOT (SELF\shape_aspect.description = 
                        'printed part cross section template')) OR
       (SIZEOF (QUERY (ad <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'horizontal material link') |
       NOT(('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (ad.relating_shape_aspect)) AND
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'TEMPLATE_MATERIAL_CROSS_SECTION_BOUNDARY' IN
       TYPEOF (ad.relating_shape_aspect\shape_aspect_relationship.
                                                 relating_shape_aspect)) AND
       (ad.relating_shape_aspect\shape_aspect_relationship.
              relating_shape_aspect\shape_aspect.description = 'right'))))) = 0); 

 WR28: (NOT (SELF\shape_aspect.description = 
                                'printed part cross section template')) OR
       (SIZEOF (QUERY (ad <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'vertical material link') |
       NOT(('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (ad.relating_shape_aspect)) AND
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'TEMPLATE_MATERIAL_CROSS_SECTION_BOUNDARY' IN
       TYPEOF (ad.relating_shape_aspect\shape_aspect_relationship.
                                              related_shape_aspect)) AND
       (ad.relating_shape_aspect\shape_aspect_relationship.
          related_shape_aspect\shape_aspect.description = 'bottom'))))) = 0); 

 WR29: (NOT (SELF\shape_aspect.description = 
                                 'printed part cross section template')) OR
       (SIZEOF (QUERY (ad <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'vertical material link') |
       NOT(('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (ad.relating_shape_aspect)) AND
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'TEMPLATE_MATERIAL_CROSS_SECTION_BOUNDARY' IN
       TYPEOF (ad.relating_shape_aspect\shape_aspect_relationship.
                                          relating_shape_aspect)) AND
       (ad.relating_shape_aspect\shape_aspect_relationship.
          relating_shape_aspect\shape_aspect.description = 'top'))))) = 0); 
 WR30: SELF\shape_aspect.name = 'NULL';
END_ENTITY; -- part_template_definition
(*

EXPRESS specification:

*)
ENTITY part_text_template_definition
  SUBTYPE OF (part_template_definition);
WHERE
  WR1: (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'TEXT_LITERAL' IN
       TYPEOF (it))) = 1)) = 1))) = 0);
  WR2: (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] * 
       TYPEOF (it)) = 2) AND (it\representation_item.name = 
         'maximum font vertical extent'))) = 1
       )) = 1))) = 0);
  WR3: (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] * 
       TYPEOF (it)) = 2) AND (it\representation_item.name = 
         'maximum font horizontal extent'))) = 1
       )) = 1))) = 0);
END_ENTITY; -- part_text_template_definition
(*

EXPRESS specification:

*)
ENTITY part_tooling_feature
 SUPERTYPE OF (fiducial_part_feature ANDOR 
               test_point_part_feature)
 SUBTYPE OF (shape_aspect);
END_ENTITY; -- part_tooling_feature
(*

EXPRESS specification:

*)
ENTITY passage_technology
  SUBTYPE OF (shape_aspect);
UNIQUE
  UR1: SELF\shape_aspect.name, SELF\shape_aspect.of_shape;
WHERE
  WR1: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION' IN 
       TYPEOF (SELF.of_shape.definition);
  WR2: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MATERIAL_DESIGNATION.DEFINITIONS')) <= 1;
  WR3: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       pdr.used_representation\representation.name = 
       'physical characteristics representation')) = 1))) = 0;
  WR4: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pcr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       pdr.used_representation\representation.name = 
       'physical characteristics representation') |
       NOT (
          {1 <= SIZEOF (pcr.used_representation.items) <= 8}
                                             ))) = 0))) = 0;
  WR5: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pcr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       pdr.used_representation\representation.name = 
       'physical characteristics representation') |
       NOT (SIZEOF (QUERY (it <* pcr.used_representation.items | 
       NOT (it\representation_item.name IN ['maximum aspect ratio', 'plated passage', 
       'maximum allowed component terminal extent', 
       'minimum allowed component terminal extent', 
       'maximum as finished deposition thickness',  
       'minimum as finished deposition thickness',  
       'maximum as finished passage extent', 
       'minimum as finished passage extent']))) = 0))) = 0))) = 0;
  WR6: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pcr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       pdr.used_representation\representation.name = 
       'physical characteristics representation') |
       NOT (SIZEOF (QUERY (it <* pcr.used_representation.items |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'RATIO_MEASURE_WITH_UNIT'] *
       TYPEOF (it)) = 2) AND
       (it\representation_item.name = 'maximum aspect ratio') AND
       (it\measure_with_unit.value_component > 1.0))) <= 1))) = 0))) = 0;
  WR7: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pcr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       pdr.used_representation\representation.name = 
       'physical characteristics representation') |
       NOT (SIZEOF (QUERY (it <* pcr.used_representation.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESCRIPTIVE_REPRESENTATION_ITEM' IN
       TYPEOF (it)) AND
       (it\representation_item.name = 'plated passage') AND
       (it\descriptive_representation_item.description IN ['true', 'false']))) = 1))) = 0))) = 0;
  WR8: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pcr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       pdr.used_representation\representation.name = 
       'physical characteristics representation') |
       NOT (SIZEOF (QUERY (it <* pcr.used_representation.items |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] *
       TYPEOF (it)) = 2) AND
       (it\representation_item.name = 'minimum as finished passage extent')
       )) <= 1))) = 0))) = 0;
  WR9: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pcr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       pdr.used_representation\representation.name = 
       'physical characteristics representation') |
       NOT (SIZEOF (QUERY (it <* pcr.used_representation.items |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] *
       TYPEOF (it)) = 2) AND
       (it\representation_item.name = 
       'maximum as finished deposition thickness'))) <= 1))) = 0))) = 0;
 WR10: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pcr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       pdr.used_representation\representation.name = 
       'physical characteristics representation') |
       NOT (SIZEOF (QUERY (it <* pcr.used_representation.items |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] *
       TYPEOF (it)) = 2) AND
       (it\representation_item.name = 
       'minimum as finished deposition thickness'))) <= 1))) = 0))) = 0;
 WR11: (NOT (SELF\shape_aspect.description IN 
       ['default component termination passage definition',
       'default via definition'])) OR 
       (SIZEOF (USEDIN (SELF, 
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MATERIAL_DESIGNATION.DEFINITIONS')) = 1);
 WR12: (NOT (SELF\shape_aspect.description IN  
       ['default component termination passage definition',
       'default unsupported passage definition',
       'default via definition'])) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pcr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       pdr.used_representation\representation.name = 
       'physical characteristics representation') |
       NOT (SIZEOF (QUERY (it <* pcr.used_representation.items |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] *
       TYPEOF (it)) = 2) AND
       (it\representation_item.name = 'minimum as finished passage extent'))) 
        = 1))) = 0))) = 0);
 WR13: (NOT (SELF\shape_aspect.description =
       'default component termination passage definition')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pcr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       pdr.used_representation\representation.name = 
       'physical characteristics representation') |
       NOT (SIZEOF (QUERY (it <* pcr.used_representation.items |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] *
       TYPEOF (it)) = 2) AND
       (it\representation_item.name = 
       'minimum as finished deposition thickness'))) 
         = 1))) = 0))) = 0);
 WR14: (NOT (SELF\shape_aspect.description =
       'default component termination passage definition')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pcr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       pdr.used_representation\representation.name = 
       'physical characteristics representation') |
       NOT (SIZEOF (QUERY (it <* pcr.used_representation.items |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] *
       TYPEOF (it)) = 2) AND
       (it\representation_item.name = 
       'minimum allowed component terminal extent'))) = 1))) = 0))) = 0);
 WR15: (NOT (SELF\shape_aspect.description =
       'default component termination passage definition')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pcr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       pdr.used_representation\representation.name = 
       'physical characteristics representation') |
       NOT (SIZEOF (QUERY (it <* pcr.used_representation.items |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] *
       TYPEOF (it)) = 2) AND
       (it\representation_item.name = 
       'maximum allowed component terminal extent'))) = 1))) = 0))) = 0);
 WR16: (NOT (SELF\shape_aspect.description = 'default via definition')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pcr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       pdr.used_representation\representation.name = 
       'physical characteristics representation') |
       NOT (SIZEOF (QUERY (it <* pcr.used_representation.items |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT'] *
       TYPEOF (it)) = 2) AND
       (it\representation_item.name = 
       'minimum as finished deposition thickness'))) = 1))) = 0))) = 0);
 WR17: SIZEOF (QUERY (rpt <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'as finished inter stratum extent') |
       (rpt.related_shape_aspect.of_shape\property_definition.description =
       'finished stratum extent') AND
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP' 
       IN 
        TYPEOF (rpt.related_shape_aspect.of_shape\property_definition.
       definition)) 
       AND    
       (rpt.related_shape_aspect.of_shape\property_definition.
        definition\product_definition_relationship.name =
       'inter stratum extent')))) = 1;
END_ENTITY; -- passage_technology
(*

EXPRESS specification:

*)
ENTITY perpendicularity_tolerance
  SUBTYPE OF (geometric_tolerance_with_specified_datum_system);
WHERE
  WR1: SELF\geometric_tolerance.name = 'perpendicularity';
END_ENTITY; -- perpendicularity_tolerance
(*

EXPRESS specification:

*)
ENTITY physical_connectivity_definition
  SUBTYPE OF (shape_aspect);
UNIQUE
  UR1: SELF\shape_aspect.name,SELF\shape_aspect.of_shape;
WHERE
  WR1: SIZEOF (QUERY (at <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'associated terminals') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL' IN
       TYPEOF (at.related_shape_aspect)) AND
((at.related_shape_aspect\shape_aspect.description = 
                 'assembly module component terminal') OR
(at.related_shape_aspect\shape_aspect.description = 
                        'bare die component terminal') OR
(at.related_shape_aspect\shape_aspect.description = 
               'interconnect component join terminal') OR
(at.related_shape_aspect\shape_aspect.description = 
             'interconnect module component terminal') OR
(at.related_shape_aspect\shape_aspect.description = 
              'minimally defined component terminal') OR
(at.related_shape_aspect\shape_aspect.description = 
                     'packaged component join terminal'))
       )) > 1;
  WR2: SIZEOF (QUERY( pd <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
        (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION') |
       pdr\property_definition_relationship.name = 'connectivity allocation')) = 1)
       ))
       <= 1;
END_ENTITY; -- physical_connectivity_definition
(*

EXPRESS specification:

*)
ENTITY physical_connectivity_element
  SUBTYPE OF (shape_aspect_relationship, shape_aspect);
WHERE
  WR1: (SELF.relating_shape_aspect\shape_aspect.description = 
                          'topological junction') XOR
       (SIZEOF ([
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL'] *
       TYPEOF (SELF.relating_shape_aspect)) = 1);
  WR2: (SELF.related_shape_aspect\shape_aspect.description = 'topological junction') XOR
       (SIZEOF ([
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL'] *
       TYPEOF (SELF.related_shape_aspect)) = 1);
  WR3: SIZEOF (QUERY (se <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'structure element') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_CONNECTIVITY_DEFINITION' IN
       TYPEOF (se.relating_shape_aspect))) = 1;
  WR4: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_UNIT' IN 
       TYPEOF (SELF.of_shape.definition)) AND
       (SELF.of_shape.definition\product_definition.
         frame_of_reference.name = 
       'physical design');
END_ENTITY; -- physical_connectivity_element
(*

EXPRESS specification:

*)
ENTITY physical_network
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: SIZEOF (QUERY (cr <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'connectivity requirement') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL' IN
       TYPEOF (cr.related_shape_aspect)) AND
((cr.related_shape_aspect\shape_aspect.description = 
     'component termination passage join terminal') OR
(cr.related_shape_aspect\shape_aspect.description = 
                              'land join terminal') OR
(cr.related_shape_aspect\shape_aspect.description = 
               'non functional land join terminal') OR
(cr.related_shape_aspect\shape_aspect.description = 
                 'printed component join terminal'))
)) >= 2;
  WR2: SIZEOF (QUERY (nt <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'network topology') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'JOIN_SHAPE_ASPECT' IN
       TYPEOF (nt.related_shape_aspect))) >= 1;
  WR3: SIZEOF (QUERY (nt <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'reference connected terminals') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PART_CONNECTED_TERMINALS_DEFINITION' IN
       TYPEOF (nt.relating_shape_aspect))) <= 1;
END_ENTITY; -- physical_network
(*

EXPRESS specification:

*)
ENTITY physical_node_requirement_to_implementing_component_allocation
  SUBTYPE OF (shape_aspect_relationship, shape_aspect);
WHERE
  WR1: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN
       TYPEOF (SELF.related_shape_aspect.of_shape\property_definition.definition)) AND
       (NOT (SELF.related_shape_aspect.of_shape\property_definition.definition\product_definition.description IN 
       ['laminate component']));
  WR2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_CONNECTIVITY_DEFINITION' IN
       TYPEOF (SELF.relating_shape_aspect);
  WR3: acyclic_shape_aspect_relationship(SELF,
       [SELF\shape_aspect_relationship.related_shape_aspect],
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.'+
       'PHYSICAL_NODE_REQUIREMENT_TO_IMPLEMENTING_COMPONENT_ALLOCATION');
  WR4: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\shape_aspect_relationship ||
       SELF\physical_node_requirement_to_implementing_component_allocation)) = 0;
(*
  WR5: SIZEOF(terminal_of_implementing_component(SELF,SELF.relating_shape_aspect)) = 0;
*)
END_ENTITY; -- physical_node_requirement_to_implementing_component_allocation
(*

EXPRESS specification:

*)
ENTITY physical_unit
 SUPERTYPE OF (ONEOF (bare_die, 
                      package, 
                      packaged_part, 
                      assembly_definition, 
                      interconnect_definition,
                      reference_packaged_part_assembly_implementation,
                      reference_packaged_part_interconnect_implementation))
 SUBTYPE OF (product_definition);
WHERE
  WR1: (NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_WITH_ASSOCIATED_DOCUMENTS' IN 
       TYPEOF (SELF))) OR
       (SIZEOF (QUERY (docs <* 
       SELF\product_definition_with_associated_documents.
        documentation_ids |
       docs.kind\document_type.product_data_type = 'CAD filename')) <= 1);
  WR2: SIZEOF (QUERY (adta <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'APPLIED_DATE_AND_TIME_ASSIGNMENT.ITEMS') |
       adta.role\date_time_role.name = 'creation date')) + 
       SIZEOF (QUERY (ada <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'APPLIED_DATE_ASSIGNMENT.ITEMS') |
       ada.role\date_role.name = 'creation date')) = 1;
  WR3: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_APPROVAL_ASSIGNMENT.ITEMS')) = 1;
  WR4: SIZEOF (QUERY (apoa <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_PERSON_AND_ORGANIZATION_ASSIGNMENT.ITEMS') |
       apoa.role\person_and_organization_role.name = 'creator')) +
       SIZEOF (QUERY (apoa <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_ORGANIZATION_ASSIGNMENT.ITEMS') |
       apoa.role\organization_role.name = 'creator')) >= 1;
  WR5: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_SECURITY_CLASSIFICATION_ASSIGNMENT.ITEMS')) = 1;
  WR6: SELF.frame_of_reference.name IN ['physical design', 
       'physical design usage'];
  WR7: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (dut <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION') |
       pdr\property_definition_relationship.name = 'physical unit technology') |
       dut.relating_property_definition\property_definition.name =
       'unit technology')) = 1)) <= 1;
  WR8: NOT(is_assembly_module_usage(SELF)) 
       OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_MODULE_TERMINAL' IN
       TYPEOF (sa))) >= 1))) = 0);
  WR9: NOT(is_assembly_module_usage(SELF)) 
       OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       pdr.used_representation\representation.name = 
               'maximum negative component height')) <= 1))) = 0);
 WR10: NOT(is_assembly_module_usage(SELF)) 
       OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       pdr.used_representation\representation.name = 
                 'maximum positive component height')) <= 1))) = 0);
 WR11: NOT(is_assembly_module_usage(SELF)) 
       OR
       (SIZEOF (QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.' +
       'RELATED_PRODUCT_DEFINITION') |
       (pdr\product_definition_relationship.name = 'implemented function') AND
       (pdr.relating_product_definition.frame_of_reference.name = 
       'functional design usage'))) = 1);
 WR12: NOT(is_assembly_module_design(SELF)) 
       OR
       (SIZEOF (QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.' +
       'RELATING_PRODUCT_DEFINITION') |
       (is_laminate_component(pdr.related_product_definition)
       ))) = 0);
 WR14: NOT(is_interconnect_module_usage(SELF)) 
       OR
       (SIZEOF (QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.' +
       'RELATED_PRODUCT_DEFINITION') |
       (pdr\product_definition_relationship.name = 'implemented function') AND
       (pdr.relating_product_definition.frame_of_reference.name = 
       'functional design usage'))) <= 1);
 WR15: NOT(is_interconnect_module_usage(SELF)) 
       OR
       (SIZEOF (QUERY (pd1 <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_SHAPE' IN TYPEOF (pd1)) 
       AND (SIZEOF(QUERY(cd <* USEDIN(pd1,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'CHARACTERIZED_DEFINITION' IN TYPEOF (cd))
       AND (SIZEOF(QUERY(pd2 <* USEDIN(cd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (pd2\property_definition.name = 'located interconnect module thickness')
       AND (SIZEOF(USEDIN(pd2,        
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')) > 1)
       )) = 1))) = 1))) <=1 );
 WR16: NOT(is_interconnect_module_usage(SELF))
       OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (pd\property_definition.name = 
       'interconnect module usage view physical characteristics'))) <= 1);
 WR17: NOT(is_interconnect_module_usage(SELF))
       OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (pd\property_definition.name = 
          'interconnect module usage view physical characteristics')
       AND (SIZEOF (QUERY (pdr <* USEDIN (pd, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       (pdr.used_representation\representation.name = 
          'minimum thickness over metal requirement')
       AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT' IN TYPEOF (pdr.used_representation))
       )) <= 1))) <= 1);
 WR18: NOT(is_interconnect_module_usage(SELF))
        OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (pd\property_definition.name = 
         'interconnect module usage view physical characteristics')
       AND (SIZEOF (QUERY (pdr <* USEDIN (pd, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       (pdr.used_representation\representation.name = 
         'maximum thickness over metal requirement')
       AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT' IN TYPEOF (pdr.used_representation))
       )) <= 1))) <= 1);
 WR19: NOT(is_interconnect_module_usage(SELF))
       OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (pd\property_definition.name = 
          'interconnect module usage view physical characteristics')
       AND (SIZEOF (QUERY (pdr <* USEDIN (pd, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       (pdr.used_representation\representation.name = 
         'minimum thickness over dielectric requirement')
       AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT' IN TYPEOF (pdr.used_representation))
       )) <= 1))) <= 1);
 WR20: NOT(is_interconnect_module_usage(SELF))
       OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (pd\property_definition.name = 
          'interconnect module usage view physical characteristics')
       AND (SIZEOF (QUERY (pdr <* USEDIN (pd, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       (pdr.used_representation\representation.name = 
           'maximum thickness over dielectric requirement')
       AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LENGTH_MEASURE_WITH_UNIT' IN TYPEOF (pdr.used_representation))
       )) <= 1))) <= 1);
 WR21: NOT(is_interconnect_module_usage(SELF))
       OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       ((pd\property_definition.name = 'restraint') OR
       (pd\property_definition.name = 'tolerance specific restraint')))) <= 1);
 WR22: NOT(is_interconnect_module_usage(SELF))
       OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       (sa\shape_aspect.description = 
                                 'interconnect module primary surface')
       )) <= 1))) = 0);
WR23: NOT(is_interconnect_module_usage(SELF))
       OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       (sa\shape_aspect.description = 
                              'interconnect module secondary surface')
       )) <= 1))) = 0);
WR24: NOT(is_interconnect_module_usage(SELF))
       OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       (sa\shape_aspect.description =
                                 'interconnect module edge surface')
       )) <= 1))) = 0);
WR25: NOT(is_assembly_module_design(SELF)) OR
((NOT ((SELF.frame_of_reference.name = 'physical design') AND
       (SELF\product_definition.name = 'assembly module')      
       AND (SIZEOF (QUERY(pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY(sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_JOINT' IN TYPEOF (sa)))) > 0 ))) = 0)))
       OR (SIZEOF (QUERY(pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF (QUERY(sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_JOINT' IN TYPEOF (sa)) AND
       (SIZEOF (QUERY( acu <* USEDIN (
       sa\shape_aspect_relationship.relating_shape_aspect.of_shape.definition,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_COMPONENT_USAGE' IN TYPEOF (acu))
       AND (acu\product_definition_relationship.relating_product_definition = SELF)
       )) >= 1))) >=1 ))) >= 1));
WR26: NOT(is_assembly_module_design(SELF)) OR
      ((NOT ((SELF.frame_of_reference.name = 'physical design') AND
       (SELF\product_definition.name = 'assembly module')      
       ))
       AND (SIZEOF (QUERY(aj <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_JOINT' IN TYPEOF (aj)))) = 0) OR
       (SIZEOF (QUERY(aj <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_JOINT' IN TYPEOF (aj))AND
       (SIZEOF (QUERY( acu <* USEDIN (aj\
        shape_aspect_relationship.related_shape_aspect,
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_COMPONENT_USAGE' IN TYPEOF (acu))
        AND (acu\product_definition_relationship.relating_product_definition = SELF)
        )) = 0))) = 0));
WR27: NOT(is_assembly_module_design(SELF)) OR
      ((NOT ((SELF.frame_of_reference.name = 'physical design') AND
       (SELF\product_definition.name = 'assembly module')      
       ))
       AND (SIZEOF (QUERY(aj <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_JOINT' IN TYPEOF (aj)))) = 0) OR
       (SIZEOF (QUERY(aj <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'ASSEMBLY_JOINT' IN TYPEOF (aj)) AND
        (SIZEOF (QUERY( cl <* USEDIN (aj\
        shape_aspect_relationship.related_shape_aspect.of_shape.definition,
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'REPRESENTATION.ITEMS') |
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'COMPONENT_LOCATION' IN TYPEOF (cl))
        AND (aj IN cl\representation.items))) = 0))) = 0));
WR28: NOT(is_interconnect_module_design(SELF)) OR
       ((NOT ((SELF.frame_of_reference.name = 'physical design') AND
       (SELF\product_definition.name = 'interconnect module')
       )) OR
       (SIZEOF (QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.' +
       'RELATING_PRODUCT_DEFINITION') |
        (
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_COMPONENT_USAGE' IN TYPEOF(pdr))
       AND
       (pdr\product_definition_relationship.name = 'interconnect module stratum assembly relationship')
       AND
       (pdr.related_product_definition\product_definition.description = 'primary design layer stratum')
       AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'STRATUM' IN TYPEOF(pdr.related_product_definition))
        )
       )
       ) = 1));

END_ENTITY; -- physical_unit
(*

EXPRESS specification:

*)
ENTITY physical_unit_datum
  SUPERTYPE OF (edge_segment_vertex)
  SUBTYPE OF (shape_aspect);
WHERE
    WR1: SELF\shape_aspect.description IN ['axis', 'plane', 'point', ''];
    WR2: SELF\shape_aspect.product_definitional = False;
    WR3: SELF\shape_aspect.name IN ['single datum', 'common datum', ''];
    WR4: (NOT (SELF\shape_aspect.name = 'common datum')) OR
         (SIZEOF (QUERY ( sar <* USEDIN(SELF,
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
         (sar\shape_aspect_relationship.name = 'datum feature usage in datum system') AND
         ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'DATUM_SYSTEM' IN TYPEOF(SAR)))) >= 1);
    WR5: (NOT (SELF\shape_aspect.name = 'common datum')) OR
         (SIZEOF (QUERY ( sar <* USEDIN(SELF,
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
         (sar\shape_aspect_relationship.name = 'datum feature usage in common datum') AND
         ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'DATUM_SYSTEM' IN TYPEOF(SAR)))) >= 2);
    WR6: (NOT ((SELF\shape_aspect.description = 'axis') AND
         (SELF\shape_aspect.name IN ['common datum', 'single datum']))) OR
         (SIZEOF (QUERY ( sar <* USEDIN(SELF,
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
         NOT(sar\shape_aspect_relationship.name = 'reference axis') AND
         ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'DATUM_REFERENCE_FRAME' IN TYPEOF(SAR)))) = 1);
    WR7: (NOT ((SELF\shape_aspect.description = 'plane') AND
         (SELF\shape_aspect.name IN ['common datum', 'single datum']))) OR
         (SIZEOF (QUERY ( sar <* USEDIN(SELF,
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
         NOT(sar\shape_aspect_relationship.name = 'reference plane') AND
         ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'DATUM_REFERENCE_FRAME' IN TYPEOF(SAR)))) = 1);
    WR8: (NOT ((SELF\shape_aspect.description = 'point') AND
         (SELF\shape_aspect.name IN ['common datum', 'single datum']))) OR
         (SIZEOF (QUERY ( sar <* USEDIN(SELF,
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
         NOT(sar\shape_aspect_relationship.name = 'reference origin') AND
         ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'DATUM_REFERENCE_FRAME' IN TYPEOF(SAR)))) = 1);
    WR9: (NOT (SELF\shape_aspect.name = 'single datum')) OR
         (SIZEOF (QUERY ( sar <* USEDIN(SELF,
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
         (sar\shape_aspect_relationship.name = 'datum usage in datum system') AND
         ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'DATUM_SYSTEM' IN TYPEOF(SAR)))) >= 1);
   WR10: (NOT (SELF\shape_aspect.name = 'single datum')) OR
         (SIZEOF (QUERY ( sar <* USEDIN(SELF,
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
         (sar\shape_aspect_relationship.name = 'datum feature usage in single datum') AND
         (TRUE))) <= 1);
   WR11: NOT ((SELF\shape_aspect.name IN [''])
         AND (SELF\shape_aspect.description IN ['']));
   WR12: (NOT(SELF\shape_aspect.description = 'plane')) OR
         (SIZEOF(QUERY ( pd <* USEDIN(SELF,
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'PROPERTY_DEFINITION.DEFINITION') |
         pd\property_definition.description = 'datum direction property')) <= 2);
END_ENTITY; -- physical_unit_datum
(*

EXPRESS specification:

*)
ENTITY physical_unit_datum_feature
  SUBTYPE OF (shape_aspect);
WHERE
    WR1: (SIZEOF(QUERY ( pd <* USEDIN(SELF,
             'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
             'PROPERTY_DEFINITION.' + 'DEFINITION') | 
             (pd\property_definition.description = 'datum feature identification')))) = 1;
    WR2: (SIZEOF (QUERY ( sar <* USEDIN(SELF,
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
         sar\shape_aspect_relationship.name IN ['datum feature usage in common datum',
         'datum feature usage in single datum'])) >= 1);
    WR3: (SIZEOF (QUERY ( sar <* USEDIN(SELF,
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
         sar\shape_aspect_relationship.name = 'datum feature usage in single datum')) <= 1);
END_ENTITY; -- physical_unit_datum_feature
(*

EXPRESS specification:

*)
ENTITY physical_unit_datum_target
  SUBTYPE OF (shape_aspect);
WHERE
    WR1: (SIZEOF (QUERY ( sar <* USEDIN(SELF,
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
         sar\shape_aspect_relationship.name = 'datum target usage')) >= 1);
END_ENTITY; -- physical_unit_datum_target
(*

EXPRESS specification:

*)
ENTITY physical_unit_datum_target_set
  SUBTYPE OF (physical_unit_datum_feature);
WHERE
    WR1: (SIZEOF (QUERY ( sar <* USEDIN(SELF,
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
         sar\shape_aspect_relationship.name = 'datum target usage')) >= 1);
    WR2: (SIZEOF (QUERY ( sar <* USEDIN(SELF,
         'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
         sar\shape_aspect_relationship.name = 'constituent')) = 0);
END_ENTITY; -- physical_unit_datum_target_set
(*

EXPRESS specification:

*)
ENTITY physical_unit_geometric_tolerance
  SUBTYPE OF (geometric_tolerance, property_definition);
WHERE
    WR1: SELF\geometric_tolerance.name = SELF\property_definition.name;
    WR2: SELF\geometric_tolerance.toleranced_shape_aspect
         = SELF\property_definition.definition;
    WR3: (NOT (SIZEOF([
              'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
              'GEOMETRIC_TOLERANCE_WITH_SPECIFIED_DATUM_SYSTEM',
              'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
              'LINEAR_PROFILE_TOLERANCE',
              'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
              'SURFACE_PROFILE_TOLERANCE',
              'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
              'POSITION_TOLERANCE'] * TYPEOF(SELF)) = 0))
         OR (SELF\geometric_tolerance.name IN ['circularity',
             'cylindricity', 'flatness', 'straightness']);
    WR4: (NOT (SELF\geometric_tolerance.name = 'circularity')) OR
         (NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'MODIFIED_GEOMETRIC_TOLERANCE' IN TYPEOF(SELF)));
    WR5: (NOT (SELF\geometric_tolerance.name = 'cylindricity')) OR
         (NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
             'MODIFIED_GEOMETRIC_TOLERANCE' IN TYPEOF(SELF)));
    WR6: (NOT (SELF\geometric_tolerance.name = 'flatness')) OR
         (NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
         'MODIFIED_GEOMETRIC_TOLERANCE' IN TYPEOF(SELF)));
    WR7: (SIZEOF (QUERY (pugt <* QUERY ( sar <* USEDIN(SELF,
          'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
          'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
          sar\shape_aspect_relationship.name = 'group geometric tolerance') | 
          pugt.relating_shape_aspect\shape_aspect.description = 
          'simultaneous requirement')) <= 1);
END_ENTITY; -- physical_unit_geometric_tolerance
(*

EXPRESS specification:

*)
ENTITY physical_unit_network_definition
 SUBTYPE OF (product_definition);
WHERE
  WR1: (NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_WITH_ASSOCIATED_DOCUMENTS' IN 
       TYPEOF (SELF))) OR
       (SIZEOF (QUERY (docs <* 
       SELF\product_definition_with_associated_documents.
        documentation_ids |
       docs.kind\document_type.product_data_type = 'CAD filename')) <= 1);
  WR2: SIZEOF (QUERY (adta <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'APPLIED_DATE_AND_TIME_ASSIGNMENT.ITEMS') |
       adta.role\date_time_role.name = 'creation date')) + 
       SIZEOF (QUERY (ada <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'APPLIED_DATE_ASSIGNMENT.ITEMS') |
       ada.role\date_role.name = 'creation date')) = 1;
  WR3: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_APPROVAL_ASSIGNMENT.ITEMS')) = 1;
  WR4: SIZEOF (QUERY (apoa <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_PERSON_AND_ORGANIZATION_ASSIGNMENT.ITEMS') |
       apoa.role\person_and_organization_role.name = 'creator')) +
       SIZEOF (QUERY (apoa <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_ORGANIZATION_ASSIGNMENT.ITEMS') |
       apoa.role\organization_role.name = 'creator')) >= 1;
  WR5: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_SECURITY_CLASSIFICATION_ASSIGNMENT.ITEMS')) = 1;
  WR6: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\product_definition ||
       SELF\physical_unit_network_definition))) = 0;
  WR7: SELF.frame_of_reference.name IN ['physical network design'];
END_ENTITY; -- physical_unit_network_definition
(*

EXPRESS specification:

*)
ENTITY plated_cutout_edge_segment
  SUBTYPE OF (cutout_edge_segment,plated_inter_stratum_feature);
WHERE
  WR1: SELF\shape_aspect.description IN ['plated cutout edge segment'];
  WR2: SIZEOF (QUERY (ji <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'join implementation') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'JOIN_SHAPE_ASPECT' IN
       TYPEOF (ji.relating_shape_aspect)) AND
       (ji.relating_shape_aspect\shape_aspect.name =
       'inter stratum join'))) <= 1;
  WR3: (NOT (SELF\shape_aspect.description = 'plated cutout edge segment')) OR
       (SIZEOF (QUERY (cc <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'composed cutout') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PLATED_INTER_STRATUM_FEATURE' IN
       TYPEOF (cc.relating_shape_aspect)) AND
       (cc.relating_shape_aspect\shape_aspect.description =
       'plated cutout'))) = 1);
END_ENTITY; -- plated_cutout_edge_segment
(*

EXPRESS specification:

*)
ENTITY plated_inter_stratum_feature
  SUPERTYPE OF (ONEOF(plated_passage,plated_cutout_edge_segment, 
 plated_interconnect_module_edge_segment))
  SUBTYPE OF (inter_stratum_feature);
WHERE
  WR1: (SELF\shape_aspect.description IN ['bonded conductive base blind via', 
        'buried via',
       'component termination passage', 'interfacial connection', 
       'non conductive base blind via', 
       'join two physical connectivity definition supporting inter stratum feature', 
       'plated conductive base blind via', 
       'plated cutout', 'plated interconnect module edge']) OR 
       (SIZEOF 
       (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
	'PLATED_CUTOUT_EDGE_SEGMENT',
	'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
	'PLATED_INTERCONNECT_MODULE_EDGE_SEGMENT'] * TYPEOF (SELF)) = 1 );
  WR2: SIZEOF (QUERY (ji <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'join implementation') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'JOIN_SHAPE_ASPECT' IN
       TYPEOF (ji.relating_shape_aspect)) AND
       (ji.relating_shape_aspect\shape_aspect.name =
       'inter stratum join'))) <= 1;
END_ENTITY; -- plated_inter_stratum_feature
(*

EXPRESS specification:

*)
ENTITY plated_interconnect_module_edge_segment
  SUBTYPE OF (interconnect_module_edge_segment,
              plated_inter_stratum_feature);
WHERE
  WR1: SELF\shape_aspect.description IN ['plated interconnect module edge segment'];
  WR2: SIZEOF (QUERY (ji <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'join implementation') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'JOIN_SHAPE_ASPECT' IN
       TYPEOF (ji.relating_shape_aspect)) AND
       (ji.relating_shape_aspect\shape_aspect.name =
       'inter stratum join'))) <= 1;
  WR3: (NOT (SELF\shape_aspect.description = 
          'plated interconnect module edge segment')) OR
       (SIZEOF (QUERY (ce <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'composed edge') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PLATED_INTER_STRATUM_FEATURE' IN
       TYPEOF (ce.relating_shape_aspect)) AND
       (ce.relating_shape_aspect\shape_aspect.description =
       'plated interconnect module edge'))) = 1);
END_ENTITY; -- plated_interconnect_module_edge_segment
(*

EXPRESS specification:

*)
ENTITY plated_passage 
  SUBTYPE OF (plated_inter_stratum_feature);
WHERE
  WR1: SELF\shape_aspect.description IN ['bonded conductive base blind via', 
       'buried via', 'component termination passage', 
       'interfacial connection', 'non conductive base blind via',
       'plated conductive base blind via'];
  WR2: (NOT (SELF\shape_aspect.description = 'bonded conductive base blind via')) OR
       (SIZEOF (QUERY (fj <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'features join') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'STRATUM_CONCEPT_RELATIONSHIP' IN
       TYPEOF (fj.relating_shape_aspect)) AND
       (fj.relating_shape_aspect\shape_aspect.name =
       'stratum feature conductive join'))) = 1);
  WR3: (NOT (SELF\shape_aspect.description = 'component termination passage')) OR
       (SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PART_TEMPLATE_DEFINITION' IN
       TYPEOF (it.relating_shape_aspect)) AND
       (it.relating_shape_aspect\shape_aspect.description =
       'component termination passage template'))) = 1);
(*
  WR4: (NOT (SELF\shape_aspect.description = 'component termination passage')) OR
       (SIZEOF (QUERY (at <* associated_terminals(SELF) |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT' IN
       TYPEOF (at)) AND
       (at\shape_aspect.description =
       'component termination passage interface terminal')))) >= 0);
  WR5: (NOT (SELF\shape_aspect.description = 'component termination passage')) OR
       (SIZEOF (QUERY (at <* associated_terminals(SELF)|
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL' IN
       TYPEOF (at)) AND
       (at\shape_aspect.description =
       'component termination passage join terminal')))) >= 1);
*)
  WR6: (NOT (SELF\shape_aspect.description IN
       ['bonded conductive base blind via',
       'buried via',
       'interfacial connection',
       'non conductive base blind via',
       'plated conductive base blind via'])) OR
       (SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PART_TEMPLATE_DEFINITION' IN
       TYPEOF (it.relating_shape_aspect)) AND
       (it.relating_shape_aspect\shape_aspect.description =
       'via template'))) = 1);
END_ENTITY; -- plated_passage
(*

EXPRESS specification:

*)
ENTITY position_tolerance
  SUBTYPE OF (physical_unit_geometric_tolerance);
WHERE
  WR1: (NOT(SELF\geometric_tolerance.name = 'boundary based position')) OR
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'MODIFIED_GEOMETRIC_TOLERANCE' IN TYPEOF(SELF));
  WR2: (NOT(SELF\geometric_tolerance.name = 'boundary based position')) OR
       (SIZEOF(QUERY(gtr <* USEDIN(SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'GEOMETRIC_TOLERANCE_RELATIONSHIP.RELATING_GEOMETRIC_TOLERANCE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'GEOMETRIC_TOLERANCE_WITH_SPECIFIED_DATUM_SYSTEM' 
        IN TYPEOF(gtr.related_geometric_tolerance)) AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'SURFACE_PROFILE_TOLERANCE' 
        IN TYPEOF(gtr.related_geometric_tolerance)) AND
       (gtr.related_geometric_tolerance\geometric_tolerance.name IN ['surface profile',
        'surface profile locating', 'surface profile refinement']) AND
       (gtr\geometric_tolerance_relationship.name = 'profile control')
       )) <= 1);
  WR3: (NOT(SELF\geometric_tolerance.name = 
                              'feature relating position')) OR
       (SIZEOF(QUERY(gtr <* USEDIN(SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'GEOMETRIC_TOLERANCE_RELATIONSHIP.RELATED_GEOMETRIC_TOLERANCE') |
       (gtr\geometric_tolerance_relationship.name = 'position refining control') AND
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'POSITION_TOLERANCE' 
        IN TYPEOF(gtr.relating_geometric_tolerance))  AND
       (gtr.relating_geometric_tolerance\geometric_tolerance.name IN
       ['feature locating position', 'feature relating position'])
       )) = 1);
  WR4: (NOT(SELF\geometric_tolerance.name = 
                          'feature locating position')) OR
       (SIZEOF(QUERY(gtr <* USEDIN(SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'GEOMETRIC_TOLERANCE_RELATIONSHIP.RELATING_GEOMETRIC_TOLERANCE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'POSITION_TOLERANCE' 
        IN TYPEOF(gtr.related_geometric_tolerance))  AND    
       (gtr.related_geometric_tolerance\geometric_tolerance.name = 'feature relating position')
       AND (gtr\geometric_tolerance_relationship.name = 'position refining control')
       )) = 1);
  WR5: (NOT(SELF\geometric_tolerance.name = 
                         'feature relating position')) OR
       (SIZEOF(QUERY(gtr <* USEDIN(SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'GEOMETRIC_TOLERANCE_RELATIONSHIP.RELATING_GEOMETRIC_TOLERANCE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'POSITION_TOLERANCE' 
        IN TYPEOF(gtr.related_geometric_tolerance))  AND
       (gtr.related_geometric_tolerance\geometric_tolerance.name = 'feature relating position')
       AND (gtr\geometric_tolerance_relationship.name = 'position refining control')
       )) <= 1);
END_ENTITY; -- position_tolerance
(*

EXPRESS specification:

*)
ENTITY positional_boundary
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: SELF\shape_aspect.description IN 
    ['dimension related positional boundary',
  'profile related positional boundary'];

  WR2: SELF\shape_aspect.product_definitional = False;

  WR3: (NOT(SELF\shape_aspect.description = 
           'dimension related positional boundary'))
       OR (SIZEOF(QUERY(sar <* USEDIN(SELF, 
          'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
          'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') 
          | ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
             'POSITIONAL_BOUNDARY_MEMBER' IN 
               TYPEOF(sar.related_shape_aspect))
            AND (sar\shape_aspect_relationship.name = 'boundary member'))) >= 1);

  WR4: (NOT(SELF\shape_aspect.description = 
         'dimension related positional boundary'))
       OR (SIZEOF(QUERY(sar <*USEDIN(SELF, 
          'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
          'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') 
          | (sar.related_shape_aspect.product_definitional = True) AND
            (sar\shape_aspect_relationship.name = 'constrained feature'))) +
           SIZEOF(QUERY(sar <*USEDIN(SELF, 
          'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
          'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') 
          | ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
          'PART_TEMPLATE_DEFINITION' IN TYPEOF(sar.related_shape_aspect))
            AND (sar\shape_aspect_relationship.name = 'constrained feature'))
           ) = 1);     

  WR5: (NOT(SELF\shape_aspect.description = 
              'dimension related positional boundary'))
       OR (SIZEOF(QUERY(pd <* USEDIN(SELF,
          'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
          'PROPERTY_DEFINITION.DEFINITION')        
          | (pd\property_definition.description = 
                'dimension related positional boundary property'))) = 1);

  WR6: (NOT(SELF\shape_aspect.description = 
                  'profile related positional boundary'))
       OR (SIZEOF(QUERY(pd <* USEDIN(SELF,
          'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
          'PROPERTY_DEFINITION.DEFINITION')        
          | (pd\property_definition.description = 
                  'profile related positional boundary property'))) = 1);
   
  WR7: (NOT(SELF\shape_aspect.description = 
                     'profile related positional boundary'))
       OR (SIZEOF(QUERY(sar <* USEDIN(SELF, 
          'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
          'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') 
          | ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'POSITIONAL_BOUNDARY_MEMBER' IN TYPEOF(sar.related_shape_aspect))
            AND (sar\shape_aspect_relationship.name = 
               'positional boundary and profile boundary member'))) = 1);
END_ENTITY; -- positional_boundary
(*

EXPRESS specification:

*)
ENTITY positional_boundary_member
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: SELF\shape_aspect.product_definitional = False;

  WR2: SIZEOF(QUERY(pd <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION')        
       | (pd\property_definition.description = 'positional boundary member property'))
       ) = 1;
  WR3: SIZEOF(QUERY(sar <* USEDIN(SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') 
       | (sar\shape_aspect_relationship.name = 'boundary member') AND
         ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
          'POSITIONAL_BOUNDARY' IN TYPEOF(sar.relating_shape_aspect))
         AND (sar.relating_shape_aspect\shape_aspect.description =
         'dimension related positional boundary'))) = 1;
END_ENTITY; -- positional_boundary_member
(*

EXPRESS specification:

*)
ENTITY power_measure_with_unit
 SUBTYPE OF (measure_with_unit);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\measure_with_unit ||
       SELF\power_measure_with_unit))) = 0;
  WR2: SELF\measure_with_unit.unit_component\si_unit.name = watt;
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SI_UNIT' IN 
       TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY; -- power_measure_with_unit
(*

EXPRESS specification:

*)
ENTITY pre_defined_parallel_datum_axis_symbol_3d_2d_relationship
  SUBTYPE OF (volume_shape_intersection);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\representation ||
       SELF\representation_relationship || 
       SELF\shape_representation_relationship || 
       SELF\volume_shape_intersection || 
       SELF\pre_defined_parallel_datum_axis_symbol_3d_2d_relationship))) = 0;
END_ENTITY; -- pre_defined_parallel_datum_axis_symbol_3d_2d_relationship 
(* 

EXPRESS specification:

*)
ENTITY pre_defined_perpendicular_datum_axis_symbol_3d_2d_relationship
  SUBTYPE OF (volume_shape_intersection);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\representation ||
       SELF\representation_relationship || 
       SELF\shape_representation_relationship || 
       SELF\volume_shape_intersection || 
       SELF\pre_defined_perpendicular_datum_axis_symbol_3d_2d_relationship))) = 0;
END_ENTITY; -- pre_defined_perpendicular_datum_axis_symbol_3d_2d_relationship 
(* 

EXPRESS specification:

*)
ENTITY pre_defined_perpendicular_datum_plane_symbol_3d_2d_relationship
  SUBTYPE OF (volume_shape_intersection);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\representation ||
       SELF\representation_relationship || 
       SELF\shape_representation_relationship || 
       SELF\volume_shape_intersection || 
       SELF\pre_defined_perpendicular_datum_plane_symbol_3d_2d_relationship))) = 0;
END_ENTITY; -- pre_defined_perpendicular_datum_plane_symbol_3d_2d_relationship 
(* 

EXPRESS specification:

*)
ENTITY pressure_measure_with_unit
 SUBTYPE OF (measure_with_unit);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\measure_with_unit ||
       SELF\pressure_measure_with_unit))) = 0;
  WR2: SELF\measure_with_unit.unit_component\si_unit.name = pascal;
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SI_UNIT' IN 
       TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY; -- pressure_measure_with_unit
(*

EXPRESS specification:

*)
ENTITY primary_orientation_feature
 SUBTYPE OF (physical_unit_datum_feature);
WHERE
  WR1: SELF\shape_aspect.product_definitional = TRUE;
  WR2: SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'associated body vertical extent') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE_BODY_BOTTOM_SURFACE' IN
       TYPEOF (it.relating_shape_aspect)) 
       )) <= 1;
  WR3: SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'associated body vertical extent') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PACKAGE_BODY_TOP_SURFACE' IN
       TYPEOF (it.relating_shape_aspect)) 
       )) <= 1;
END_ENTITY; -- primary_orientation_feature
(*

EXPRESS specification:

*)
ENTITY primary_reference_terminal
  SUBTYPE OF (package_terminal);
WHERE
 WR1: SIZEOF(QUERY ( sar <* USEDIN (SELF,
      'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
      'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'precedent feaure' ))
       = 0;
 WR2: SIZEOF(QUERY ( sar <* USEDIN (SELF,
      'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
      'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'precedent feaure' ))
       <= 1;
END_ENTITY; -- primary_reference_terminal
(*

EXPRESS specification:

*)
ENTITY printed_component
  SUPERTYPE OF(layout_macro_component)
  SUBTYPE OF (component_definition);
WHERE
  WR1: SELF.frame_of_reference.name = 'layout occurrence';
  WR2: SELF\product_definition.description = 'printed component';
  WR3: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pt_occ <* QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       sa\shape_aspect.description = 'part template occurrence') |
       SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (pt_occ,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |  
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PART_TEMPLATE_DEFINITION' IN
       TYPEOF (it.relating_shape_aspect)) AND
       (it.relating_shape_aspect\shape_aspect.description IN ['printed part template', 
       'printed part cross section template', 
       'printed connector template']))) = 1)) = 1))) = 0;
  WR4: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_TERMINAL' IN
       TYPEOF (sa)) AND
       (sa\shape_aspect.description = 'printed component join terminal'))) >= 1))) = 0;
  WR5: (NOT (SELF\product_definition.description = 'printed connector component')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LAMINATE_COMPONENT_INTERFACE_TERMINAL' IN
       TYPEOF (sa)) AND
       (sa\shape_aspect.description = 
       'printed connector component interface terminal'))) >= 1))) = 0);
  WR6: (NOT (SELF\product_definition.description = 'printed connector component')) OR
       (SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pt_occ <* QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       sa\shape_aspect.description = 'part template occurrence') |
       SIZEOF (QUERY (it <* QUERY (sar <* USEDIN (pt_occ,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'instantiated template') |  
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PART_TEMPLATE_DEFINITION' IN
       TYPEOF (it.relating_shape_aspect)) AND
       (it.relating_shape_aspect\shape_aspect.description = 
       'printed connector template'))) = 1)) = 1))) = 0);
  WR7: SIZEOF(QUERY(pd <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |  
        SIZEOF(QUERY(sa <* USEDIN(pd, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') | 
        SIZEOF(QUERY(sar <* USEDIN(sa, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
        (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
         'COMPONENT_SHAPE_ASPECT' IN TYPEOF(sar.relating_shape_aspect))
        AND (sar\shape_aspect_relationship.name = 'stratum feature implementation')
        AND (sar.relating_shape_aspect.description = 'stratum feature template component'))
        )) >= 1
        )) >= 1 
        )) >= 1;
END_ENTITY; -- printed_component
(*

EXPRESS specification:

*)
ENTITY printed_component_link
  SUBTYPE OF (product_definition,product_definition_relationship);
WHERE
  WR1: SELF\product_definition_relationship.related_product_definition :<>:
       SELF\product_definition_relationship.relating_product_definition;
  WR2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN
       TYPEOF (SELF\product_definition_relationship.related_product_definition);
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN
       TYPEOF (SELF\product_definition_relationship.relating_product_definition);
  WR4: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\product_definition ||
       SELF\product_definition_relationship ||
       SELF\printed_component_link)) = 0;
  WR5: EXISTS(SELF\product_definition.name);
  WR6: SELF\product_definition.name = '';
  WR7: SELF\product_definition_relationship.name = '';
  WR8: SIZEOF(USEDIN(SELF, 
             'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
             'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')) = 1;
END_ENTITY; -- printed_component_link 
(* 

EXPRESS specification:

*)
ENTITY printed_connector_template_terminal_relationship
 SUBTYPE OF (shape_aspect, shape_aspect_relationship);
UNIQUE
  UR1: SELF\shape_aspect_relationship.relating_shape_aspect,
       SELF\shape_aspect_relationship.related_shape_aspect;
WHERE
  WR1: SIZEOF ( QUERY( sar <* USEDIN ( SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
        (( sar\shape_aspect_relationship.name = 'connector') AND
          (sar.relating_shape_aspect\shape_aspect.description = 
              'printed connector template'))
        )) = 1;
  WR2: (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_TERMINAL' IN TYPEOF 
       (SELF\shape_aspect_relationship.relating_shape_aspect)) AND
       (SELF\shape_aspect_relationship.relating_shape_aspect\shape_aspect.description 
        = 'interface terminal'));
  WR3: (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_TERMINAL' IN 
       TYPEOF (SELF\shape_aspect_relationship.related_shape_aspect)) AND
       (SELF\shape_aspect_relationship.related_shape_aspect\shape_aspect.description 
        = 'join terminal'));
  WR4: SELF\shape_aspect_relationship.relating_shape_aspect :<>:
       SELF\shape_aspect_relationship.related_shape_aspect;
END_ENTITY; -- printed_connector_template_terminal_relationship
(*

EXPRESS specification:

*)
ENTITY printed_part_cross_section_template_terminal
  SUBTYPE OF (printed_part_template_terminal);
WHERE
  WR1: 
       SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'cross section definition') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PART_TEMPLATE_DEFINITION' IN
       TYPEOF (am.relating_shape_aspect)) AND
       (am.relating_shape_aspect\shape_aspect.description = 
       'printed part cross section template'))) = 1;

  WR2: SIZEOF (QUERY (ga <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_GROUP_ASSIGNMENT.ITEMS') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_TERMINAL_CONNECTION_ZONE_CATEGORY' IN
       TYPEOF (ga.assigned_group)) AND 
       (ga.assigned_group.name IN  
                       ['area edge segment', 'curve edge segment']))
        )) = 1;
  WR3: SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'material to left of terminal') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) <= 1;
  WR4: SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'material to right of terminal') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) <= 1;
  WR5: SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'material to top of terminal') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) <= 1;
  WR6: SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'material to bottom of terminal') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) <= 1;
  WR7: NOT((SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'material to left of terminal') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) = 1) AND
       (SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'material to right of terminal') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) = 1)) 
   OR
       (SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       (sar\shape_aspect_relationship.name = 'material to right of terminal') OR
       (sar\shape_aspect_relationship.name = 'material to left of terminal')
       ) |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) = 2);
       
  WR8: NOT((SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'material to left of terminal') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) = 1) AND
       (SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'material to top of terminal') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) = 1)) 
   OR
       (SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       (sar\shape_aspect_relationship.name = 'material to top of terminal') OR
       (sar\shape_aspect_relationship.name = 'material to left of terminal')
       ) |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) = 2);
  WR9: NOT((SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'material to left of terminal') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) = 1) AND
       (SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'material to bottom of terminal') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) = 1)) 
   OR
       (SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       (sar\shape_aspect_relationship.name = 'material to bottom of terminal') OR
       (sar\shape_aspect_relationship.name = 'material to left of terminal')
       ) |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) = 2);
 WR10: NOT((SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'material to top of terminal') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) = 1) AND
       (SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'material to right of terminal') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) = 1)) 
   OR
       (SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       (sar\shape_aspect_relationship.name = 'material to right of terminal') OR
       (sar\shape_aspect_relationship.name = 'material to top of terminal')
       ) |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) = 2);
 WR11: NOT((SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'material to bottom of terminal') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) = 1) AND
       (SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'material to right of terminal') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) = 1)) 
   OR
       (SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       (sar\shape_aspect_relationship.name = 'material to right of terminal') OR
       (sar\shape_aspect_relationship.name = 'material to bottom of terminal')
       ) |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) = 2);
 WR12: NOT((SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'material to top of terminal') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) = 1) AND
       (SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'material to bottom of terminal') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) = 1)) 
   OR
       (SIZEOF (QUERY (am <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       (sar\shape_aspect_relationship.name = 'material to top of terminal') OR
       (sar\shape_aspect_relationship.name = 'material to bottom of terminal')
       ) |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_MATERIAL_LINK' IN
       TYPEOF (am.relating_shape_aspect))
       )) = 2);
END_ENTITY; -- printed_part_cross_section_template_terminal
(*

EXPRESS specification:

*)
ENTITY printed_part_template_connected_terminals_definition
  SUBTYPE OF (shape_aspect);
UNIQUE
  UR1: SELF\shape_aspect.name;
WHERE
  WR1: SIZEOF (QUERY (mct <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'member connected terminal') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_TERMINAL' IN
       TYPEOF (mct.related_shape_aspect)) AND
       (mct.related_shape_aspect\shape_aspect.description IN 
       ['interface terminal', 'join terminal']))) >= 2;
END_ENTITY; -- printed_part_template_connected_terminals_definition
(*

EXPRESS specification:

*)
ENTITY printed_part_template_link
  SUBTYPE OF (stratum_technology_link,shape_aspect_relationship);
WHERE
  WR1: SELF\shape_aspect_relationship.related_shape_aspect :<>:
       SELF\shape_aspect_relationship.relating_shape_aspect;
  WR2: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\property_definition_relationship ||
       SELF\printed_part_template_link || SELF\property_definition ||
       SELF\stratum_technology_link || SELF\shape_aspect_relationship)) = 0;
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PART_TEMPLATE_DEFINITION' IN 
    TYPEOF(SELF\shape_aspect_relationship.related_shape_aspect);
  WR4: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PART_TEMPLATE_DEFINITION' IN 
    TYPEOF(SELF\shape_aspect_relationship.relating_shape_aspect);
  WR5: SELF\shape_aspect_relationship.name = '';
  WR6: SELF\shape_aspect_relationship.description = '';
  WR7: SELF\shape_aspect_relationship.related_shape_aspect.description =
       'printed part template';
  WR8: SELF\shape_aspect_relationship.relating_shape_aspect.description =
       'printed part template';
END_ENTITY; -- printed_part_template_link
(*

EXPRESS specification:

*)
ENTITY printed_part_template_material
 SUBTYPE OF (product_definition);
WHERE
  WR1: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       SIZEOF (QUERY (tu <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION') |
       pdr\property_definition_relationship.name = 'technology usage') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'STRATUM_TECHNOLOGY' IN 
       TYPEOF (tu.relating_property_definition.definition))) = 1)) = 1;
  WR2: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sr_pdr <* QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION' IN 
       TYPEOF (pdr.used_representation)) |
       ((sr_pdr.used_representation\representation.name = 
                'physical characteristics representation')
       AND
       (SIZEOF (sr_pdr.used_representation.items) = 2 )
       AND 
      ( SIZEOF(QUERY (it <* sr_pdr.used_representation.items |
       it\representation_item.name IN ['maximum width', 
                                        'minimum width'])) = 2 ))
       )) = 1)))
       = 0;
  WR3: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\product_definition ||
       SELF\printed_part_template_material)) = 0;
 WR4: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'TEMPLATE_MATERIAL_CROSS_SECTION_BOUNDARY' IN
       TYPEOF (sa)) AND (sa.description = 'top')))) <= 1))) = 0;
 WR5: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'TEMPLATE_MATERIAL_CROSS_SECTION_BOUNDARY' IN
       TYPEOF (sa)) AND (sa.description = 'bottom')))) <= 1))) = 0;
 WR6: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'TEMPLATE_MATERIAL_CROSS_SECTION_BOUNDARY' IN
       TYPEOF (sa)) AND (sa.description = 'left')))) <= 1))) = 0;
 WR7: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (sa <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'TEMPLATE_MATERIAL_CROSS_SECTION_BOUNDARY' IN
       TYPEOF (sa)) AND (sa.description = 'right')))) <= 1))) = 0;
END_ENTITY; -- printed_part_template_material

(*

EXPRESS specification:

*)
ENTITY printed_part_template_material_link
  SUBTYPE OF (shape_aspect,shape_aspect_relationship);
UNIQUE
  UR1: SELF\shape_aspect_relationship.related_shape_aspect, 
       SELF\shape_aspect_relationship.relating_shape_aspect;
WHERE
  WR1: SELF\shape_aspect_relationship.related_shape_aspect :<>:
       SELF\shape_aspect_relationship.relating_shape_aspect;
  WR2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'TEMPLATE_MATERIAL_CROSS_SECTION_BOUNDARY' IN
       TYPEOF (SELF\shape_aspect_relationship.related_shape_aspect);
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'TEMPLATE_MATERIAL_CROSS_SECTION_BOUNDARY' IN
       TYPEOF (SELF\shape_aspect_relationship.relating_shape_aspect);
  WR4: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\shape_aspect ||
       SELF\shape_aspect_relationship ||
       SELF\printed_part_template_material_link)) = 0;
  WR5: SELF\shape_aspect.name = '';
  WR6: SELF\shape_aspect_relationship.name = '';
  WR7: SELF\shape_aspect_relationship.related_shape_aspect.of_shape :<>: 
       SELF\shape_aspect_relationship.relating_shape_aspect.of_shape;
  WR8: SELF\shape_aspect_relationship.relating_shape_aspect.description IN
       ['bottom', 'right'];
  WR9: SELF\shape_aspect_relationship.related_shape_aspect.description IN
       ['top', 'left'];
END_ENTITY; -- printed_part_template_material_link 
(* 

EXPRESS specification:

*)
ENTITY printed_part_template_terminal
  SUPERTYPE OF (printed_part_cross_section_template_terminal)
  SUBTYPE OF (shape_aspect);
WHERE
  WR1: SELF\shape_aspect.description IN ['interface terminal', 'join terminal'];
  WR2: SIZEOF (QUERY (ga <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_GROUP_ASSIGNMENT.ITEMS') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_TERMINAL_CONNECTION_ZONE_CATEGORY' IN
       TYPEOF (ga.assigned_group))) = 1;
  WR3: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar.related_shape_aspect\shape_aspect.description = 
       'connection zone')) >= 1;
  WR4: SIZEOF (QUERY (pd <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       NOT (SIZEOF (QUERY (pdr <* USEDIN (pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_REPRESENTATION' IN
       TYPEOF (pdr.used_representation))) >= 1))) = 0;
  WR5: SIZEOF (QUERY (ad <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'associated definition') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PART_TEMPLATE_DEFINITION' IN
       TYPEOF (ad.relating_shape_aspect)) AND
       ((ad.relating_shape_aspect\shape_aspect.description = 'printed part template')
       OR
       (ad.relating_shape_aspect\shape_aspect.description = 'printed connector template'))
       )) = 1;
  WR6: SIZEOF (QUERY (mct <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'member connected terminal') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRINTED_PART_TEMPLATE_CONNECTED_TERMINALS_DEFINITION' IN
       TYPEOF (mct.relating_shape_aspect))) <= 1;
END_ENTITY; -- printed_part_template_terminal
(*

EXPRESS specification:

*)
ENTITY printed_part_template_terminal_connection_zone_category
   SUBTYPE OF (group);
WHERE
   WR1: SELF\group.name IN ['area edge segment','curve edge segment',
        'surface area','surface point'];
END_ENTITY; -- printed_part_template_terminal_connection_zone_category
(*

EXPRESS specification:

*)
ENTITY probe_access_area
  SUBTYPE OF (component_shape_aspect);
WHERE
  WR1: EXISTS(SELF.of_shape.definition\product_definition.name);
  WR2: ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'COMPONENT_DEFINITION' IN
       TYPEOF (SELF.of_shape.definition)) AND
       (SELF.of_shape.definition\product_definition.name = 'interconnect module');
  WR3: SIZEOF (QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar.related_shape_aspect\shape_aspect.description =
       'connection zone')) = 1;
  WR4: SIZEOF (QUERY (pli <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'probed layout item') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'STRATUM_FEATURE' IN
       TYPEOF (pli.related_shape_aspect))) = 1;
  WR5: (NOT (SELF\shape_aspect.description = 
        'internal probe access area')) OR
       (SIZEOF (QUERY (i <* QUERY (sar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
       sar\shape_aspect_relationship.name = 'implementation') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'STRATUM_FEATURE' IN
       TYPEOF (i.relating_shape_aspect)))) = 1);
END_ENTITY; -- probe_access_area
(*

EXPRESS specification:

*)
ENTITY product_related_characterized_product_category
  SUBTYPE OF (characterized_product_category, 
              product_related_product_category);
END_ENTITY; -- product_related_characterized_product_category
(*

EXPRESS specification:

*)
ENTITY product_specific_parameter_value_assignment
  SUBTYPE OF (product_related_characterized_product_category); 
WHERE
  WR1: SIZEOF(SELF\product_related_product_category.products) = 1;
  WR2: SIZEOF(QUERY(pd <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (pd\property_definition.description = 
                                'product category parameter') AND
       (SIZEOF(QUERY(pdr <* USEDIN(pd,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       (SIZEOF (
       ['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MODEL_PARAMETER',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'MEASURE_REPRESENTATION_ITEM',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESCRIPTIVE_REPRESENTATION_ITEM'] *
       TYPEOF (pdr.used_representation)) = 1))) = 1))) = 1;
  WR3: SIZEOF(QUERY(pcr <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_CATEGORY_RELATIONSHIP.SUB_CATEGORY') |
       ((pcr\product_category_relationship.description = 
                                  'product value assignment') AND
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_RELATED_PRODUCT_CATEGORY') IN 
       TYPEOF (pcr.category))
       ))) = 1;
END_ENTITY; -- product_specific_parameter_value_assignment
(*

EXPRESS specification:

*)
ENTITY promissory_usage_in_product_model
 SUBTYPE OF (group);
WHERE
   WR1: SIZEOF( QUERY(aga <* USEDIN(SELF,
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'GROUP_ASSIGNMENT.ASSIGNED_GROUP') | 
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'APPLIED_PROMISSORY_USAGE_IN_PRODUCT_MODEL_ASSIGNMENT' IN TYPEOF(aga))
           ) >= 1;
END_ENTITY; -- promissory_usage_in_product_model
(*

EXPRESS specification:

*)
ENTITY rectangular_array_placement_group_component_definition
  SUBTYPE OF (array_placement_group_component_definition);
END_ENTITY; -- rectangular_array_placement_group_component_definition
(*

EXPRESS specification:

*)
ENTITY rectangular_array_placement_group_component_shape_aspect
  SUBTYPE OF (array_placement_group_component_shape_aspect);
END_ENTITY; -- rectangular_array_placement_group_component_shape_aspect
(*

EXPRESS specification:

*)
ENTITY rectangular_composite_array_shape_aspect
  SUBTYPE OF (composite_array_shape_aspect);
END_ENTITY; -- rectangular_composite_array_shape_aspect
(*

EXPRESS specification:

*)
ENTITY reference_packaged_part_assembly_implementation
 SUBTYPE OF (physical_unit);
WHERE
  WR1: (SIZEOF (QUERY (prpc <* 
       USEDIN (SELF.formation.of_product,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS') |
       prpc\product_category.name = 'template model')) >= 1) AND
       (SELF\product_definition.name = 'assembly module');
  WR2: (NOT (SELF.frame_of_reference.name = 'physical design')) OR
       (SIZEOF (QUERY (du <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.' +
       'RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'design usage') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ASSEMBLY_DEFINITION', 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_ASSEMBLY_DEFINITION', 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_ASSEMBLY_DEFINITION'] *
       TYPEOF (du.relating_product_definition)) = 1) AND
       (du.relating_product_definition.frame_of_reference.name = 
       'physical design usage') AND
       (du.relating_product_definition\product_definition.name =
       'assembly module') AND
       (SIZEOF (QUERY (prpc <*
       USEDIN (du.relating_product_definition.formation.of_product,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS') |
       prpc\product_category.name = 'template model')) >= 1)
       )) = 1);
END_ENTITY; -- reference_packaged_part_assembly_implementation
(*

EXPRESS specification:

*)
ENTITY reference_packaged_part_interconnect_implementation
 SUBTYPE OF (physical_unit);
WHERE
  WR1: EXISTS(SELF\product_definition.name);
  WR2: (SIZEOF (QUERY (prpc <*
       USEDIN (SELF.formation.of_product,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS') |
       prpc\product_category.name = 'template model')) >= 1) AND
       (SELF\product_definition.name = 'interconnect module');
  WR3: SIZEOF (QUERY (du <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.' +
       'RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'design usage') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_UNIT', 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EXTERNALLY_DEFINED_PHYSICAL_UNIT', 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'LIBRARY_DEFINED_PHYSICAL_UNIT'] *
       TYPEOF (du.relating_product_definition)) = 1) AND
       (du.relating_product_definition.frame_of_reference.name = 
       'physical design usage') AND
       (du.relating_product_definition\product_definition.name =
       'interconnect module') AND
       (SIZEOF (QUERY (prpc <*
       USEDIN (du.relating_product_definition.formation.of_product,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS') |
       prpc\product_category.name = 'template model')) >= 1) 
       )) <= 1;
  WR4: SELF.frame_of_reference.name = 'physical design';
END_ENTITY; -- reference_packaged_part_interconnect_implementation
(*

EXPRESS specification:

*)
ENTITY requirement_allocation_group
  SUBTYPE OF (group, property_definition_relationship);
WHERE
  WR1: (SIZEOF (QUERY (aga <* QUERY (ga <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'GROUP_ASSIGNMENT.ASSIGNED_GROUP') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_GROUP_ASSIGNMENT' IN
       TYPEOF (ga)) |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_FORMATION',
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'CONFIGURATION_ITEM'] * TYPEOF (aga.items)) = 1))) = 1);

  WR2: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REQUIREMENTS_PROPERTY' IN TYPEOF 
   (SELF\property_definition_relationship.relating_property_definition);

  WR4: NOT(SELF\property_definition_relationship.related_property_definition.description = 'test requirement') OR
       (SIZEOF (QUERY (aga <* QUERY (ga <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'GROUP_ASSIGNMENT.ASSIGNED_GROUP') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_GROUP_ASSIGNMENT' IN
       TYPEOF (ga)) |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION'] * TYPEOF (aga.items)) = 1))) >= 1);
END_ENTITY; -- requirement_allocation_group
(*

EXPRESS specification:

*)
ENTITY requirement_definition
 SUBTYPE OF (product_definition);
WHERE
  WR1: (NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_WITH_ASSOCIATED_DOCUMENTS' IN 
       TYPEOF (SELF))) OR
       (SIZEOF (QUERY (docs <* 
       SELF\product_definition_with_associated_documents.
        documentation_ids |
       docs.kind\document_type.product_data_type = 'CAD filename')) <= 1);
  WR2: SIZEOF (QUERY (adta <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'APPLIED_DATE_AND_TIME_ASSIGNMENT.ITEMS') |
       adta.role\date_time_role.name = 'creation date')) + 
       SIZEOF (QUERY (ada <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'APPLIED_DATE_ASSIGNMENT.ITEMS') |
       ada.role\date_role.name = 'creation date')) = 1;
  WR3: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_APPROVAL_ASSIGNMENT.ITEMS')) = 1;
  WR4: SIZEOF (QUERY (apoa <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_PERSON_AND_ORGANIZATION_ASSIGNMENT.ITEMS') |
       apoa.role\person_and_organization_role.name = 'creator')) +
       SIZEOF (QUERY (apoa <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_ORGANIZATION_ASSIGNMENT.ITEMS') |
       apoa.role\organization_role.name = 'creator')) >= 1;
  WR5: SIZEOF (USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_SECURITY_CLASSIFICATION_ASSIGNMENT.ITEMS')) = 1;
  WR6: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\product_definition ||
       SELF\requirement_definition))) = 0;
  WR7: SIZEOF (QUERY (prpc <* USEDIN (SELF.formation.of_product,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_RELATED_PRODUCT_CATEGORY.' +
       'PRODUCTS') |
       prpc\product_category.name = 'requirements model')) >= 1;
END_ENTITY; -- requirement_definition
(*

EXPRESS specification:

*)
ENTITY requirements_property
  SUBTYPE OF (property_definition);
WHERE
  WR1: SIZEOF (QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION') |
       pdr\property_definition_relationship.name = 'requirements property composition')) <= 1;
  WR2: SIZEOF (QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESCRIPTIVE_REPRESENTATION_ITEM' IN
       TYPEOF (it)) AND
       (it\representation_item.name = 'requirements description'))) = 1)) <= 1;
  WR3: SIZEOF (QUERY (dr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_DOCUMENT_REFERENCE.ITEMS') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'EE_SPECIFICATION' IN 
       TYPEOF (dr.assigned_document))) >= 1;
  WR4: NOT(EXISTS(SELF\property_definition.description)) OR
       (NOT (SELF\property_definition.description IN ['constraint', 
        'part based constraint']) OR
       (SIZEOF (QUERY (dc <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION') |
       pdr\property_definition_relationship.name = 'design constraint') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'RULE_DEFINITION' IN 
       TYPEOF (dc.relating_property_definition.definition))) = 1));
  WR5: NOT(EXISTS(SELF\property_definition.description)) OR
       (NOT (SELF\property_definition.description = 
          'part based constraint') OR
       (SIZEOF (QUERY (cp <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION') |
       pdr\property_definition_relationship.name = 'constraining part') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP' IN
       TYPEOF (cp.relating_property_definition.definition)) AND
       (cp.relating_property_definition.definition\product_definition_relationship.name = 
       'constraining part') AND
   (cp.relating_property_definition.definition.related_product_definition.
       frame_of_reference.name = 'design requirement'))) = 1));
  WR6: NOT(EXISTS(SELF\property_definition.description)) OR
       (NOT (SELF\property_definition.description = 
         'interface requirement') OR
       (SIZEOF (QUERY (itnha <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION') |
       pdr\property_definition_relationship.name = 'interface to next higher assembly') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION' IN
       TYPEOF (itnha.relating_property_definition.definition)) AND
    (itnha.relating_property_definition.definition.frame_of_reference.name
       = 'design requirement') AND
       (SIZEOF (QUERY (hai <* QUERY (pdr <* 
       USEDIN (itnha.relating_property_definition.definition,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'higher assembly interface') |
       SIZEOF (QUERY (pdr <* USEDIN (hai,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SPECIFIED_HIGHER_USAGE_OCCURRENCE'  
       IN TYPEOF (pdr))) = 1)) = 1))) = 1));
  WR7: SIZEOF (QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION') |
       SIZEOF (QUERY (it <* pdr.used_representation.items |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'DESCRIPTIVE_REPRESENTATION_ITEM' IN
       TYPEOF (it)) AND
       (it\representation_item.name = 'requirements name'))) = 1)) = 1;
END_ENTITY; -- requirements_property
(*

EXPRESS specification:

*)
ENTITY requirements_property_group
  SUBTYPE OF (requirements_property, group);
WHERE
  WR1: SIZEOF (QUERY (rpc <* QUERY (pdr <* USEDIN (SELF, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_RELATIONSHIP.RELATING_PROPERTY_DEFINITION') |
       pdr\property_definition_relationship.name = 'requirements property composition') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REQUIREMENTS_PROPERTY' IN 
       TYPEOF (rpc.related_property_definition))) >= 1;
END_ENTITY; -- requirements_property_group
(*

EXPRESS specification:

*)
ENTITY resistance_measure_with_unit
 SUBTYPE OF (measure_with_unit);
WHERE
  WR1: SIZEOF(TYPEOF(SELF) - (TYPEOF(SELF\measure_with_unit ||
       SELF\resistance_measure_with_unit))) = 0;
  WR2: SELF\measure_with_unit.unit_component\si_unit.name = ohm;
  WR3: 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SI_UNIT' IN 
       TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY; -- resistance_measure_with_unit
(*

EXPRESS specification:

*)
ENTITY routed_physical_component
  SUBTYPE OF (component_definition);
WHERE
  WR1: SIZEOF (QUERY (ip <* QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION') |
       pdr\product_definition_relationship.name = 'instantiated part') |
       (SIZEOF (['ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PHYSICAL_UNIT'] *
       TYPEOF (ip.relating_product_definition)) = 1) AND
       (ip.relating_product_definition.frame_of_reference.name =
       'physical design usage'))) = 1;
  WR2: SELF\product_definition.description :<>: 'laminate component';
END_ENTITY; -- routed_physical_component
(*

EXPRESS specification:

*)
ENTITY routed_printed_component
 SUBTYPE OF (printed_component);
WHERE
  WR1: SIZEOF(QUERY(pd <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       (SIZEOF(QUERY(sa <* USEDIN(pd, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT.OF_SHAPE') |
       (SIZEOF(QUERY(sar <* USEDIN(sa,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
        ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
         'PART_TEMPLATE_DEFINITION' IN TYPEOF(sar.relating_shape_aspect))
        AND (sar.relating_shape_aspect\shape_aspect.description = 
            'printed part cross section template')
        AND (sar\shape_aspect_relationship.name = 'instantiated template')
          )) = 1)
         )) = 1)
        )) = 1;
  WR2: SIZEOF(QUERY(csa <* USEDIN(SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
         'COMPONENT_SHAPE_ASPECT' IN TYPEOF(csa))      
         AND (SIZEOF(QUERY(sar <* USEDIN(csa, 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT') |
        (SIZEOF(QUERY(pdr <* USEDIN(sar,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION.DEFINITION') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
         'PRODUCT_DEFINITION_RELATIONSHIP' IN TYPEOF(pdr)) AND
        (pdr\product_definition_relationship.name = 'inter stratum extent')      
        )) = 1)
        AND (sar\shape_aspect_relationship.name = 'component extent')
        )) = 1)
        )) = 1;
END_ENTITY; -- routed_printed_component
(*

EXPRESS specification:

*)
ENTITY rule_action
  SUBTYPE OF (action);
WHERE
  WR1: SIZEOF (QUERY (aaa <* QUERY (aa <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'ACTION_ASSIGNMENT.ASSIGNED_ACTION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_ACTION_ASSIGNMENT' IN
       TYPEOF (aa)) |
       SIZEOF (QUERY (it <* aaa.items |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_FORMATION' IN 
       TYPEOF (it))
AND (it\product_definition_formation.description = 'rule version'))
)) = 1)) = 1;
  WR2: SIZEOF (QUERY (adta <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_DATE_AND_TIME_ASSIGNMENT.ITEMS') |
       adta.role\date_time_role.name = 'participant date and time')) +
       SIZEOF (QUERY (ada <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'APPLIED_DATE_ASSIGNMENT.ITEMS') |
       ada.role\date_role.name = 'participant date')) = 1;
  WR3: (NOT (SELF\action.name = 'rule justification')) OR
       (SIZEOF (QUERY (ja <* QUERY (ar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ACTION_RELATIONSHIP.RELATED_ACTION') |
       ar\action_relationship.name = 'justified action') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'RULE_ACTION' IN
       TYPEOF (ja.relating_action))) = 1);
  WR4: (NOT (SELF\action.name = 'rule modification')) OR
       (SIZEOF (QUERY (mr <* QUERY (ar <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'ACTION_RELATIONSHIP.RELATED_ACTION') |
       ar\action_relationship.name = 'modification rationale') |
       ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'RULE_ACTION' IN
       TYPEOF (mr.relating_action)) AND
       (mr.relating_action\action.name = 'rule change request'))) = 1);
  WR5: (NOT (SELF\action.name = 'rule replacement from')) OR
       (SIZEOF (QUERY (rrfa <* QUERY (aa <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'ACTION_ASSIGNMENT.ASSIGNED_ACTION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'RULE_REPLACEMENT_FROM_ASSIGNMENT' IN
       TYPEOF (aa)) |
       SIZEOF (QUERY (it <* rrfa.items |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_FORMATION' IN 
       TYPEOF (it))
AND (it\product_definition_formation.description = 'rule version'))
)) = 1)) = 1);
  WR6: (NOT (SELF\action.name = 'rule replacement to')) OR
       (SIZEOF (QUERY (rrta <* QUERY (aa <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'ACTION_ASSIGNMENT.ASSIGNED_ACTION') |
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'RULE_REPLACEMENT_TO_ASSIGNMENT' IN
       TYPEOF (aa)) |
       SIZEOF (QUERY (it <* rrta.items |
       (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PRODUCT_DEFINITION_FORMATION' IN 
       TYPEOF (it))
AND (it\product_definition_formation.description = 'rule version'))
)) = 1)) = 1);
END_ENTITY; -- rule_action
(*

EXPRESS specification:

*)
ENTITY rule_complex_clause 
 SUBTYPE OF (representation);
UNIQUE
 UR1: SELF\representation.name;
WHERE
  WR1: SIZEOF (QUERY (rr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 
       'REPRESENTATION_RELATIONSHIP.REP_2') | 
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'RULE_SIMPLE_CLAUSE' IN TYPEOF (rr.rep_1))) >= 1;
  WR2: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\representation ||
       SELF\rule_complex_clause)) = 0;
END_ENTITY; -- rule_complex_clause
(*

EXPRESS specification:

*)
ENTITY rule_conclusion_definition 
 SUBTYPE OF (representation);
WHERE
  WR1: SIZEOF (QUERY (pdr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION') |
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'RULE_DEFINITION' IN TYPEOF
       (pdr.definition.definition))) = 1;
  WR2: SIZEOF (QUERY (rr <* USEDIN (SELF,
       'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
       'REPRESENTATION_RELATIONSHIP.REP_2') |
        'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' +
        'RULE_SIMPLE_CLAUSE' IN TYPEOF 
       (rr\representation_relationship.rep_1))) >= 1;

  WR3: SIZEOF(TYPEOF(SELF) - TYPEOF(SELF\representation ||
       SELF\rule_conclusion_definition)) = 0;
END_ENTITY; -- rule_conclusion_definition
(*

EXPRESS specification:

*)
ENTITY rule_definition 
 SUBTYPE OF (product_definition);
WHERE
  WR1: SELF\product_definition.formation.description = 'rule version';
END_ENTITY; -- rule_definition
(*