Index for the electronic_assembly_interconnect_and_packaging

Index for the electronic_assembly_interconnect_and_packaging_design Schema. Index for the electronic_assembly_interconnect_and_packaging_design Schema
Interface Specifications
None are present
Constants
dummy_gri
Entities
Types
Procedures
None are present
Functions
Rules
**************************************************************************
SCHEMA electronic_assembly_interconnect_and_packaging_design;





***********************************


CONSTANT

dummy_gri : geometric_representation_item := representation_item('') || geometric_representation_item();
END_CONSTANT;





***********************************



ENTITY action;

name : label;

description : text;

chosen_method : action_method;
END_ENTITY;




ENTITY action_assignment
ABSTRACT SUPERTYPE;

assigned_action : action;
END_ENTITY;




ENTITY action_directive;

name : label;

description : text;

analysis : text;

comment : text;

requests : SET [1:?] OF versioned_action_request;
END_ENTITY;




ENTITY action_method;

name : label;

description : text;

consequence : text;

purpose : text;
END_ENTITY;




ENTITY action_method_relationship;

name : label;

description : text;

relating_method : action_method;

related_method : action_method;
END_ENTITY;




ENTITY action_relationship;

name : label;

description : text;

relating_action : action;

related_action : action;
END_ENTITY;




ENTITY action_request_assignment
ABSTRACT SUPERTYPE;

assigned_action_request : versioned_action_request;
END_ENTITY;




ENTITY action_request_solution;

method : action_method;

request : versioned_action_request;
END_ENTITY;




ENTITY action_request_status;

status : label;

assigned_request : versioned_action_request;
END_ENTITY;




ENTITY action_status;

status : label;

assigned_action : executed_action;
END_ENTITY;




ENTITY add_design_object_assignment
SUBTYPE OF (action_assignment);

items : SET [1:?] OF managed_design_object;
END_ENTITY;




ENTITY add_design_object_request_assignment
SUBTYPE OF (action_request_assignment);

items : SET [1:?] OF managed_design_object;
END_ENTITY;




ENTITY address;

internal_location : OPTIONAL label;

street_number : OPTIONAL label;

street : OPTIONAL label;

postal_box : OPTIONAL label;

town : OPTIONAL label;

region : OPTIONAL label;

postal_code : OPTIONAL label;

country : OPTIONAL label;

facsimile_number : OPTIONAL label;

telephone_number : OPTIONAL label;

electronic_mail_address : OPTIONAL label;

telex_number : OPTIONAL label;
WHERE

wr1:
((((((((((EXISTS(internal_location) OR EXISTS(street_number)) OR EXISTS(street)) OR EXISTS(postal_box)) OR EXISTS(town)) OR EXISTS(region)) OR EXISTS(postal_code)) OR EXISTS(country)) OR EXISTS(facsimile_number)) OR EXISTS(telephone_number)) OR EXISTS(electronic_mail_address)) OR EXISTS(telex_number);
END_ENTITY;




ENTITY advanced_brep_shape_representation
SUBTYPE OF (shape_representation);
WHERE

wr1:
SIZEOF(
QUERY (it <* SELF.items| NOT (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MANIFOLD_SOLID_BREP', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.FACETED_BREP', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AXIS2_PLACEMENT_3D' ] * TYPEOF(it)) = 1))) = 0;

wr2:
SIZEOF(
QUERY (it <* SELF.items| (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MANIFOLD_SOLID_BREP', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' ] * TYPEOF(it)) = 1))) > 0;

wr3:
SIZEOF(
QUERY (msb <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MANIFOLD_SOLID_BREP' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (csh <* msb_shells(msb, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN')| NOT (SIZEOF(
QUERY (fcs <* csh\connected_face_set.cfs_faces| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ADVANCED_FACE' IN TYPEOF(fcs)))) = 0))) = 0))) = 0;

wr4:
SIZEOF(
QUERY (msb <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MANIFOLD_SOLID_BREP' IN TYPEOF(it)))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ORIENTED_CLOSED_SHELL' IN TYPEOF(msb\manifold_solid_brep.outer)))) = 0;

wr5:
SIZEOF(
QUERY (brv <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.BREP_WITH_VOIDS' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (csh <* brv\brep_with_voids.voids| csh\oriented_closed_shell.orientation)) = 0))) = 0;

wr6:
SIZEOF(
QUERY (mi <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' IN TYPEOF(it)))| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ADVANCED_BREP_SHAPE_REPRESENTATION' IN TYPEOF(mi\mapped_item.mapping_source.mapped_representation)))) = 0;
END_ENTITY;




ENTITY advanced_face
SUBTYPE OF (face_surface);
WHERE

wr1:
SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ELEMENTARY_SURFACE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.B_SPLINE_SURFACE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SWEPT_SURFACE' ] * TYPEOF(face_geometry)) = 1;

wr2:
SIZEOF(
QUERY (elp_fbnds <* 
QUERY (bnds <* SELF.bounds| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_LOOP' IN TYPEOF(bnds.bound)))| NOT (SIZEOF(
QUERY (oe <* elp_fbnds.bound\path.edge_list| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_CURVE' IN TYPEOF(oe.edge_element)))) = 0))) = 0;

wr3:
SIZEOF(
QUERY (elp_fbnds <* 
QUERY (bnds <* SELF.bounds| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_LOOP' IN TYPEOF(bnds.bound)))| NOT (SIZEOF(
QUERY (oe <* elp_fbnds.bound\path.edge_list| NOT (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.LINE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CONIC', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POLYLINE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SURFACE_CURVE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.B_SPLINE_CURVE' ] * TYPEOF(oe.edge_element\edge_curve.edge_geometry)) = 1))) = 0))) = 0;

wr4:
SIZEOF(
QUERY (elp_fbnds <* 
QUERY (bnds <* SELF.bounds| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_LOOP' IN TYPEOF(bnds.bound)))| NOT (SIZEOF(
QUERY (oe <* elp_fbnds.bound\path.edge_list| NOT (((('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_POINT' IN TYPEOF(oe.edge_start)) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CARTESIAN_POINT' IN TYPEOF(oe.edge_start\vertex_point.vertex_geometry))) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_POINT' IN TYPEOF(oe.edge_end))) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CARTESIAN_POINT' IN TYPEOF(oe.edge_end\vertex_point.vertex_geometry))))) = 0))) = 0;

wr5:
SIZEOF(
QUERY (elp_fbnds <* 
QUERY (bnds <* SELF.bounds| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_LOOP' IN TYPEOF(bnds.bound)))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ORIENTED_PATH' IN TYPEOF(elp_fbnds.bound)))) = 0;

wr6:
NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SWEPT_SURFACE' IN TYPEOF(face_geometry)) OR (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.LINE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CONIC', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POLYLINE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.B_SPLINE_CURVE' ] * TYPEOF(face_geometry\swept_surface.swept_curve)) = 1);

wr7:
SIZEOF(
QUERY (vlp_fbnds <* 
QUERY (bnds <* SELF.bounds| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_LOOP' IN TYPEOF(bnds.bound)))| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_POINT' IN TYPEOF(vlp_fbnds\face_bound.bound\vertex_loop.loop_vertex)) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CARTESIAN_POINT' IN TYPEOF(vlp_fbnds\face_bound.bound\vertex_loop.loop_vertex\vertex_point.vertex_geometry))))) = 0;

wr8:
SIZEOF(
QUERY (bnd <* SELF.bounds| NOT (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_LOOP', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_LOOP' ] * TYPEOF(bnd.bound)) = 1))) = 0;

wr9:
SIZEOF(
QUERY (elp_fbnds <* 
QUERY (bnds <* SELF.bounds| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_LOOP' IN TYPEOF(bnds.bound)))| NOT (SIZEOF(
QUERY (oe <* elp_fbnds.bound\path.edge_list| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SURFACE_CURVE' IN TYPEOF(oe.edge_element\edge_curve.edge_geometry)) AND NOT (SIZEOF(
QUERY (sc_ag <* oe.edge_element\edge_curve.edge_geometry\surface_curve.associated_geometry| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PCURVE' IN TYPEOF(sc_ag)))) = 0))) = 0))) = 0;

wr10:
((NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SWEPT_SURFACE' IN TYPEOF(face_geometry)) OR NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POLYLINE' IN TYPEOF(face_geometry\swept_surface.swept_curve))) OR (SIZEOF(face_geometry\swept_surface.swept_curve\polyline.points) < 3)) AND (SIZEOF(
QUERY (elp_fbnds <* 
QUERY (bnds <* SELF.bounds| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_LOOP' IN TYPEOF(bnds.bound)))| NOT (SIZEOF(
QUERY (oe <* elp_fbnds.bound\path.edge_list| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POLYLINE' IN TYPEOF(oe.edge_element\edge_curve.edge_geometry)) AND NOT (SIZEOF(oe.edge_element\edge_curve.edge_geometry\polyline.points) < 3))) = 0))) = 0);
END_ENTITY;




ENTITY alternate_product_relationship;

name : label;

definition : text;

alternate : product;

base : product;

basis : text;
UNIQUE

ur1 : alternate, base;
WHERE

wr1:
alternate :<>: base;
END_ENTITY;




ENTITY amount_of_substance_measure_with_unit
SUBTYPE OF (measure_with_unit);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AMOUNT_OF_SUBSTANCE_UNIT' IN TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY;




ENTITY amount_of_substance_unit
SUBTYPE OF (named_unit);
WHERE

wr1:
((((((SELF\named_unit.dimensions.length_exponent = 0) AND (SELF\named_unit.dimensions.mass_exponent = 0)) AND (SELF\named_unit.dimensions.time_exponent = 0)) AND (SELF\named_unit.dimensions.electric_current_exponent = 0)) AND (SELF\named_unit.dimensions.thermodynamic_temperature_exponent = 0)) AND (SELF\named_unit.dimensions.amount_of_substance_exponent = 1)) AND (SELF\named_unit.dimensions.luminous_intensity_exponent = 0);
END_ENTITY;




ENTITY analytical_model
SUBTYPE OF (representation);
WHERE

wr1:
SIZEOF(
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION')| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CHARACTERIZED_OBJECT') ] * TYPEOF(pdr.definition.definition)) = 1))) = 0;

wr2:
SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DOCUMENT_REFERENCE.ITEMS')) = 2;

wr3:
SIZEOF(
QUERY (dr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DOCUMENT_REFERENCE.ITEMS')| (dr.assigned_document.kind.product_data_type = 'language reference manual'))) = 1;

wr4:
SIZEOF(
QUERY (it <* SELF.items| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MODEL_PARAMETER' IN TYPEOF(it)))) = 0;

wr5:
SIZEOF(
QUERY (rr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REPRESENTATION_RELATIONSHIP.REP_1')| (rr.name = 'access mechanism') AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ANALYTICAL_MODEL_PORT' IN TYPEOF(rr.rep_2)))) >= 1;
END_ENTITY;




ENTITY analytical_model_port
SUBTYPE OF (representation);
WHERE

wr1:
SIZEOF(
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION')| NOT (SIZEOF(TYPEOF(pdr.definition.definition) * [ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CHARACTERIZED_OBJECT') ]) = 1))) = 0;

wr2:
SIZEOF(
QUERY (it <* SELF.items| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'distributed property')) AND (it\descriptive_representation_item.description IN [ 'true', 'false' ]))) = 1;

wr3:
SIZEOF(
QUERY (it <* SELF.items| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'nominal signal flow direction')) AND (it\descriptive_representation_item.description IN [ 'input direction', 'output direction', 'bidirectional', 'unknown direction', 'not applicable' ]))) <= 1;

wr4:
SIZEOF(
QUERY (it <* SELF.items| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'port type')) AND (it\descriptive_representation_item.description IN [ 'string property type', 'logical property type', 'physical property type', 'boolean property type' ]))) = 1;

wr5:
SIZEOF(
QUERY (am <* 
QUERY (rr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REPRESENTATION_RELATIONSHIP.REP_2')| (rr.name = 'access mechanism'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ANALYTICAL_MODEL' IN TYPEOF(am.rep_1)))) = 1;

wr6:
SIZEOF(
QUERY (aga <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_GROUP_ASSIGNMENT.ITEMS')| (aga.assigned_group.name IN [ 'scalar port', 'digital scalar port', 'vector port', 'digital vector port', 'digital analytical model port' ]))) <= 1;

wr7:
NOT (SIZEOF(
QUERY (aga <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_GROUP_ASSIGNMENT.ITEMS')| (aga.assigned_group.name IN [ 'vector port', 'digital vector port' ]))) = 1) OR (SIZEOF(
QUERY (it <* SELF.items| ((('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'size')) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COUNT_MEASURE' IN TYPEOF(it\measure_with_unit.value_component))) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CONTEXT_DEPENDENT_UNIT' IN TYPEOF(it\measure_with_unit.unit_component)))) = 1);

wr8:
NOT (SIZEOF(
QUERY (aga <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_GROUP_ASSIGNMENT.ITEMS')| (aga.assigned_group.name IN [ 'digital scalar port', 'digital vector port', 'digital analytical model port' ]))) = 1) OR (SIZEOF(
QUERY (it <* SELF.items| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'nominal signal flow direction')) AND (it\descriptive_representation_item.description IN [ 'input direction', 'output direction', 'bidirectional', 'unknown direction' ]))) = 1);
END_ENTITY;




ENTITY analytical_representation
SUBTYPE OF (representation);
WHERE

wr1:
SIZEOF(
QUERY (rr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REPRESENTATION_RELATIONSHIP.REP_1')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PARAMETER_ASSIGNMENT_REPRESENTATION' IN TYPEOF(rr.rep_2)))) >= 1;

wr2:
SIZEOF(
QUERY (rr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REPRESENTATION_RELATIONSHIP.REP_2')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ANALYTICAL_MODEL' IN TYPEOF(rr.rep_1)))) = 1;
END_ENTITY;




ENTITY angular_dimension_with_orientation
SUBTYPE OF (dimensional_location);
WHERE

wr1:
SELF\shape_aspect_relationship.description = 'angular';
END_ENTITY;




ENTITY angular_location
SUBTYPE OF (dimensional_location);

angle_selection : angle_relator;
END_ENTITY;




ENTITY angular_size
SUBTYPE OF (dimensional_size);

angle_selection : angle_relator;
END_ENTITY;




ENTITY angularity_tolerance
SUBTYPE OF (geometric_tolerance_with_specified_datum_system);
WHERE

wr1:
SELF\geometric_tolerance.name = 'angularity';
END_ENTITY;




ENTITY annotation_curve_occurrence
SUBTYPE OF (annotation_occurrence);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CURVE' IN TYPEOF(SELF\styled_item.item);
END_ENTITY;




ENTITY annotation_fill_area
SUBTYPE OF (geometric_representation_item);

boundaries : SET [1:?] OF curve;
END_ENTITY;




ENTITY annotation_fill_area_occurrence
SUBTYPE OF (annotation_occurrence);

fill_style_target : point;
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ANNOTATION_FILL_AREA' IN TYPEOF(SELF.item);
END_ENTITY;




ENTITY annotation_occurrence
SUPERTYPE OF (ONEOF(annotation_curve_occurrence, annotation_fill_area_occurrence, annotation_text_occurrence, annotation_symbol_occurrence))
SUBTYPE OF (styled_item);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_REPRESENTATION_ITEM' IN TYPEOF(SELF);
END_ENTITY;




ENTITY annotation_symbol
SUBTYPE OF (mapped_item);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SYMBOL_REPRESENTATION_MAP' IN TYPEOF(SELF\mapped_item.mapping_source);

wr2:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SYMBOL_TARGET' IN TYPEOF(SELF\mapped_item.mapping_target);

wr3:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_REPRESENTATION_ITEM' IN TYPEOF(SELF);
END_ENTITY;




ENTITY annotation_symbol_occurrence
SUBTYPE OF (annotation_occurrence);
WHERE

wr1:
SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ANNOTATION_SYMBOL', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.DEFINED_SYMBOL' ] * TYPEOF(SELF\styled_item.item)) > 0;
END_ENTITY;




ENTITY annotation_text
SUBTYPE OF (mapped_item);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AXIS2_PLACEMENT' IN TYPEOF(SELF\mapped_item.mapping_target);

wr2:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.TEXT_STRING_REPRESENTATION' IN TYPEOF(SELF\mapped_item.mapping_source.mapped_representation);

wr3:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_REPRESENTATION_ITEM' IN TYPEOF(SELF);
END_ENTITY;




ENTITY annotation_text_character
SUBTYPE OF (mapped_item);

alignment : text_alignment;
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CHARACTER_GLYPH_SYMBOL' IN TYPEOF(SELF\mapped_item.mapping_source.mapped_representation);

wr2:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AXIS2_PLACEMENT' IN TYPEOF(SELF\mapped_item.mapping_target);

wr3:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_REPRESENTATION_ITEM' IN TYPEOF(SELF);
END_ENTITY;




ENTITY annotation_text_occurrence
SUBTYPE OF (annotation_occurrence);
WHERE

wr1:
SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.TEXT_LITERAL', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ANNOTATION_TEXT', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ANNOTATION_TEXT_CHARACTER', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.DEFINED_CHARACTER_GLYPH', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.COMPOSITE_TEXT' ] * TYPEOF(SELF\styled_item.item)) > 0;
END_ENTITY;




ENTITY apex
SUBTYPE OF (derived_shape_aspect);
END_ENTITY;




ENTITY application_context;

application : text;
INVERSE

context_elements : SET [1:?] OF application_context_element FOR frame_of_reference;
END_ENTITY;




ENTITY application_context_element
SUPERTYPE OF (ONEOF(product_context, product_definition_context, product_concept_context));

name : label;

frame_of_reference : application_context;
END_ENTITY;




ENTITY application_protocol_definition;

status : label;

application_interpreted_model_schema_name : label;

application_protocol_year : year_number;

application : application_context;
END_ENTITY;




ENTITY applied_action_assignment
SUBTYPE OF (action_assignment);

items : SET [1:?] OF action_assigned_item;
END_ENTITY;




ENTITY applied_approval_assignment
SUBTYPE OF (approval_assignment);

items : SET [1:?] OF approval_assigned_item;
END_ENTITY;




ENTITY applied_certification_assignment
SUBTYPE OF (certification_assignment);

items : SET [1:?] OF certification_assigned_item;
END_ENTITY;




ENTITY applied_classification_assignment
SUBTYPE OF (group_assignment);

items : SET [1:?] OF classification_assigned_item;
END_ENTITY;




ENTITY applied_contract_assignment
SUBTYPE OF (contract_assignment);

items : SET [1:?] OF contract_assigned_item;
END_ENTITY;




ENTITY applied_date_and_time_assignment
SUBTYPE OF (date_and_time_assignment);

items : SET [1:?] OF date_and_time_assigned_item;
WHERE

wr1:
applied_date_time_correlation(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN');

wr2:
NOT (SELF.role.name = 'participant date and time') OR (SIZEOF(
QUERY (ra <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'RULE_ACTION' IN TYPEOF(it)))| NOT (SIZEOF(USEDIN(ra, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_PERSON_AND_ORGANIZATION_ASSIGNMENT.ITEMS')) = 1))) = 0);
END_ENTITY;




ENTITY applied_date_assignment
SUBTYPE OF (date_assignment);

items : SET [1:?] OF date_assigned_item;
WHERE

wr1:
applied_date_correlation(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN');
END_ENTITY;




ENTITY applied_document_reference
SUBTYPE OF (document_reference);

items : SET [1:?] OF document_assigned_item;
END_ENTITY;




ENTITY applied_group_assignment
SUBTYPE OF (group_assignment);

items : SET [1:?] OF group_assigned_item;
END_ENTITY;




ENTITY applied_organization_assignment
SUBTYPE OF (organization_assignment);

items : SET [1:?] OF organization_assigned_item;
END_ENTITY;




ENTITY applied_person_and_organization_assignment
SUBTYPE OF (person_and_organization_assignment);

items : SET [1:?] OF person_and_organization_assigned_item;
END_ENTITY;




ENTITY applied_person_assignment
SUBTYPE OF (person_assignment);

items : SET [1:?] OF person_assigned_item;
END_ENTITY;




ENTITY applied_security_classification_assignment
SUBTYPE OF (security_classification_assignment);

items : SET [1:?] OF security_classification_assigned_item;
END_ENTITY;




ENTITY approval;

status : approval_status;

level : label;
END_ENTITY;




ENTITY approval_assignment
ABSTRACT SUPERTYPE;

assigned_approval : approval;
END_ENTITY;




ENTITY approval_date_time;

date_time : date_time_select;

dated_approval : approval;
END_ENTITY;




ENTITY approval_person_organization;

person_organization : person_organization_select;

authorized_approval : approval;

role : approval_role;
END_ENTITY;




ENTITY approval_relationship;

name : label;

description : text;

relating_approval : approval;

related_approval : approval;
END_ENTITY;




ENTITY approval_role;

role : label;
END_ENTITY;




ENTITY approval_status;

name : label;
END_ENTITY;




ENTITY area_measure_with_unit
SUBTYPE OF (measure_with_unit);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AREA_UNIT' IN TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY;




ENTITY area_unit
SUBTYPE OF (named_unit);
WHERE

wr1:
((((((SELF\named_unit.dimensions.length_exponent = 2) AND (SELF\named_unit.dimensions.mass_exponent = 0)) AND (SELF\named_unit.dimensions.time_exponent = 0)) AND (SELF\named_unit.dimensions.electric_current_exponent = 0)) AND (SELF\named_unit.dimensions.thermodynamic_temperature_exponent = 0)) AND (SELF\named_unit.dimensions.amount_of_substance_exponent = 0)) AND (SELF\named_unit.dimensions.luminous_intensity_exponent = 0);
END_ENTITY;




ENTITY array_placement_group_component_definition
SUBTYPE OF (assembly_group_component_definition);
END_ENTITY;




ENTITY array_placement_group_component_shape_aspect
SUBTYPE OF (assembly_group_component_shape_aspect);
END_ENTITY;




ENTITY assembly_bond_definition
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MATERIAL_DESIGNATION.DEFINITIONS')) = 1;

wr2:
SIZEOF(
QUERY (aga <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_GROUP_ASSIGNMENT.ITEMS')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'BOND_CATEGORY' IN TYPEOF(aga.assigned_group)))) = 1;

wr3:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CHARACTERIZED_OBJECT' IN TYPEOF(SELF.of_shape\property_definition.definition);

wr4:
SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'bonded feature 1'))) = 1;

wr5:
SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'bonded feature 2'))) = 1;
END_ENTITY;




ENTITY assembly_component_usage
SUPERTYPE OF (ONEOF(next_assembly_usage_occurrence, specified_higher_usage_occurrence, promissory_usage_occurrence))
SUBTYPE OF (product_definition_usage);

reference_designator : OPTIONAL identifier;
END_ENTITY;




ENTITY assembly_component_usage_substitute;

name : label;

definition : text;

base : assembly_component_usage;

substitute : assembly_component_usage;
UNIQUE

ur1 : base, substitute;
WHERE

wr1:
base.relating_product_definition :=: substitute.relating_product_definition;

wr2:
base :<>: substitute;
END_ENTITY;




ENTITY assembly_definition
SUBTYPE OF (physical_unit);
WHERE

wr1:
SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'assembly module'))) >= 1;

wr2:
NOT (SELF.frame_of_reference.name = 'physical design') OR (SIZEOF(
QUERY (du <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.' + 'RELATING_PRODUCT_DEFINITION')| (pdr.name = 'design usage'))| ((SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_ASSEMBLY_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_ASSEMBLY_DEFINITION') ] * TYPEOF(du)) = 1) AND (du.related_product_definition.frame_of_reference.name = 'physical design usage')) AND (SIZEOF(
QUERY (prpc <* USEDIN(du.related_product_definition.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.' + 'PRODUCTS')| (prpc\product_category.name = 'assembly module'))) >= 1))) = 1);

wr3:
NOT (SELF.frame_of_reference.name = 'physical design usage') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_MODULE_TERMINAL' IN TYPEOF(sa)) AND (sa.description = 'pca terminal'))) >= 2))) = 0);
END_ENTITY;




ENTITY assembly_group_component_definition
SUBTYPE OF (component_definition);
END_ENTITY;




ENTITY assembly_group_component_shape_aspect
SUBTYPE OF (component_shape_aspect);
END_ENTITY;




ENTITY assembly_joint
SUBTYPE OF (shape_aspect_relationship, shape_aspect);
WHERE

wr1:
('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL' IN TYPEOF(SELF.relating_shape_aspect)) AND (SELF.relating_shape_aspect.description IN [ 'assembly module component terminal', 'bare die component terminal', 'interconnect component join terminal', 'interconnect module component terminal', 'package terminal occurrence', 'packaged component join terminal' ]) OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_INTERFACE_TERMINAL' IN TYPEOF(SELF.relating_shape_aspect));

wr2:
('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL' IN TYPEOF(SELF.related_shape_aspect)) AND (SELF.related_shape_aspect.description IN [ 'assembly module component terminal', 'bare die component terminal', 'interconnect component join terminal', 'interconnect module component terminal', 'package terminal occurrence', 'packaged component join terminal' ]) OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_INTERFACE_TERMINAL' IN TYPEOF(SELF.related_shape_aspect));

wr3:
NOT (SELF\shape_aspect_relationship.name = 'assembled with bonding') OR (SIZEOF(
QUERY (pdr <* USEDIN(SELF.of_shape.definition, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_COMPONENT_USAGE' IN TYPEOF(pdr)))) >= 1);

wr4:
NOT (SELF\shape_aspect_relationship.name = 'assembled with bonding') OR (SIZEOF(
QUERY (ddu <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'default definition usage'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_BOND_DEFINITION' IN TYPEOF(ddu.relating_shape_aspect)))) = 1);

wr5:
NOT (SELF\shape_aspect_relationship.name = 'assembled with bonding') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'bond assembly position') AND (SIZEOF(
QUERY (it <* pdr.used_representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MAPPED_ITEM' IN TYPEOF(it)) AND (it.name = 'assembly position'))) = 1))) = 1))) <= 1);

wr6:
NOT (SELF\shape_aspect_relationship.name = 'assembled with fasteners') OR (SIZEOF(
QUERY (pdr <* USEDIN(SELF.of_shape.definition, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_COMPONENT_USAGE' IN TYPEOF(pdr)))) >= 1);
END_ENTITY;




ENTITY assembly_module_terminal
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SIZEOF(
QUERY (prpc <* USEDIN(SELF.of_shape.definition\product_definition.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'assembly module'))) >= 1;

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_REPRESENTATION' IN TYPEOF(pdr.used_representation)))) >= 1))) = 0;

wr3:
SIZEOF(
QUERY (mct <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'member connected terminal'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_CONNECTED_TERMINALS_DEFINITION' IN TYPEOF(mct.relating_shape_aspect)))) <= 1;

wr4:
NOT (SELF\shape_aspect.description = 'pca terminal') OR (SIZEOF(TYPEOF(SELF.of_shape.definition) * [ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_ASSEMBLY_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_ASSEMBLY_DEFINITION') ]) >= 1) AND (SELF.of_shape.definition\product_definition.frame_of_reference.name = 'physical design usage');

wr5:
SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.related_shape_aspect.description = 'connection zone'))) = 1;
END_ENTITY;




ENTITY auxiliary_characteristic_dimension_representation
SUBTYPE OF (dimensional_characteristic_representation);
END_ENTITY;




ENTITY axis1_placement
SUBTYPE OF (placement);

axis : OPTIONAL direction;
DERIVE

z : direction := NVL(normalise(axis), dummy_gri || direction([ 0, 0, 1 ]));
WHERE

wr1:
SELF\geometric_representation_item.dim = 3;
END_ENTITY;




ENTITY axis2_placement_2d
SUBTYPE OF (placement);

ref_direction : OPTIONAL direction;
DERIVE

p : LIST [2:2] OF direction := build_2axes(ref_direction);
WHERE

wr1:
SELF\geometric_representation_item.dim = 2;
END_ENTITY;




ENTITY axis2_placement_3d
SUBTYPE OF (placement);

axis : OPTIONAL direction;

ref_direction : OPTIONAL direction;
DERIVE

p : LIST [3:3] OF direction := build_axes(axis, ref_direction);
WHERE

wr1:
SELF\placement.location.dim = 3;

wr2:
NOT EXISTS(axis) OR (axis.dim = 3);

wr3:
NOT EXISTS(ref_direction) OR (ref_direction.dim = 3);

wr4:
(NOT EXISTS(axis) OR NOT EXISTS(ref_direction)) OR (cross_product(axis, ref_direction).magnitude > 0);
END_ENTITY;




ENTITY b_spline_curve
SUPERTYPE OF (ONEOF(uniform_curve, b_spline_curve_with_knots, quasi_uniform_curve, bezier_curve) ANDOR rational_b_spline_curve)
SUBTYPE OF (bounded_curve);

degree : INTEGER;

control_points_list : LIST [2:?] OF cartesian_point;

curve_form : b_spline_curve_form;

closed_curve : LOGICAL;

self_intersect : LOGICAL;
DERIVE

upper_index_on_control_points : INTEGER := SIZEOF(control_points_list) - 1;

control_points : ARRAY [0:upper_index_on_control_points] OF cartesian_point := list_to_array(control_points_list, 0, upper_index_on_control_points);
WHERE

wr1:
((('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.UNIFORM_CURVE' IN TYPEOF(SELF)) OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.QUASI_UNIFORM_CURVE' IN TYPEOF(SELF))) OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.BEZIER_CURVE' IN TYPEOF(SELF))) OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.B_SPLINE_CURVE_WITH_KNOTS' IN TYPEOF(SELF));
END_ENTITY;




ENTITY b_spline_curve_with_knots
SUBTYPE OF (b_spline_curve);

knot_multiplicities : LIST [2:?] OF INTEGER;

knots : LIST [2:?] OF parameter_value;

knot_spec : knot_type;
DERIVE

upper_index_on_knots : INTEGER := SIZEOF(knots);
WHERE

wr1:
constraints_param_b_spline(degree, upper_index_on_knots, upper_index_on_control_points, knot_multiplicities, knots);

wr2:
SIZEOF(knot_multiplicities) = upper_index_on_knots;
END_ENTITY;




ENTITY b_spline_surface
SUPERTYPE OF (ONEOF(b_spline_surface_with_knots, uniform_surface, quasi_uniform_surface, bezier_surface) ANDOR rational_b_spline_surface)
SUBTYPE OF (bounded_surface);

u_degree : INTEGER;

v_degree : INTEGER;

control_points_list : LIST [2:?] OF LIST [2:?] OF cartesian_point;

surface_form : b_spline_surface_form;

u_closed : LOGICAL;

v_closed : LOGICAL;

self_intersect : LOGICAL;
DERIVE

u_upper : INTEGER := SIZEOF(control_points_list) - 1;

v_upper : INTEGER := SIZEOF(control_points_list[1]) - 1;

control_points : ARRAY [0:u_upper] OF ARRAY [0:v_upper] OF cartesian_point := make_array_of_array(control_points_list, 0, u_upper, 0, v_upper);
WHERE

wr1:
((('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.UNIFORM_SURFACE' IN TYPEOF(SELF)) OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.QUASI_UNIFORM_SURFACE' IN TYPEOF(SELF))) OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.BEZIER_SURFACE' IN TYPEOF(SELF))) OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.B_SPLINE_SURFACE_WITH_KNOTS' IN TYPEOF(SELF));
END_ENTITY;




ENTITY b_spline_surface_with_knots
SUBTYPE OF (b_spline_surface);

u_multiplicities : LIST [2:?] OF INTEGER;

v_multiplicities : LIST [2:?] OF INTEGER;

u_knots : LIST [2:?] OF parameter_value;

v_knots : LIST [2:?] OF parameter_value;

knot_spec : knot_type;
DERIVE

knot_u_upper : INTEGER := SIZEOF(u_knots);

knot_v_upper : INTEGER := SIZEOF(v_knots);
WHERE

wr1:
constraints_param_b_spline(SELF\b_spline_surface.u_degree, knot_u_upper, SELF\b_spline_surface.u_upper, u_multiplicities, u_knots);

wr2:
constraints_param_b_spline(SELF\b_spline_surface.v_degree, knot_v_upper, SELF\b_spline_surface.v_upper, v_multiplicities, v_knots);

wr3:
SIZEOF(u_multiplicities) = knot_u_upper;

wr4:
SIZEOF(v_multiplicities) = knot_v_upper;
END_ENTITY;




ENTITY bare_die
SUBTYPE OF (physical_unit);
WHERE

wr1:
SIZEOF(
QUERY (ifdu <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.' + 'RELATED_PRODUCT_DEFINITION')| (pdr.name = 'implemented function'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FUNCTIONAL_UNIT' IN TYPEOF(ifdu.relating_product_definition)) AND (ifdu.relating_product_definition.frame_of_reference.name = 'functional design usage'))) = 1;

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (dut <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')| (pdr.name = 'device unit technology'))| (dut.relating_property_definition.name = 'unit technology'))) = 1))) = 1;

wr3:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'BARE_DIE_TERMINAL' IN TYPEOF(sa)))) >= 2))) = 0;

wr4:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sr_pdr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_REPRESENTATION' IN TYPEOF(pdr)))| (sr_pdr.used_representation.name = 'seating plane'))) = 1))) = 0;
END_ENTITY;




ENTITY bare_die_terminal
SUBTYPE OF (minimally_defined_bare_die_terminal);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'BARE_DIE' IN TYPEOF(SELF.of_shape.definition);

wr2:
SIZEOF(
QUERY (eca <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'external connection area'))| (eca.related_shape_aspect.description = 'connection zone'))) = 1;

wr3:
SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MATERIAL_DESIGNATION.DEFINITIONS')) = 1;
END_ENTITY;




ENTITY bezier_curve
SUBTYPE OF (b_spline_curve);
END_ENTITY;




ENTITY bezier_surface
SUBTYPE OF (b_spline_surface);
END_ENTITY;




ENTITY block
SUBTYPE OF (geometric_representation_item);

position : axis2_placement_3d;

x : positive_length_measure;

y : positive_length_measure;

z : positive_length_measure;
END_ENTITY;




ENTITY bond_category
SUBTYPE OF (group, externally_defined_item);
WHERE

wr1:
SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DOCUMENT_REFERENCE.ITEMS')) = 1;
END_ENTITY;




ENTITY boolean_result
SUBTYPE OF (geometric_representation_item);

operator : boolean_operator;

first_operand : boolean_operand;

second_operand : boolean_operand;
END_ENTITY;




ENTITY boundary_curve
SUBTYPE OF (composite_curve_on_surface);
WHERE

wr1:
SELF\composite_curve_on_surface\composite_curve.closed_curve;
END_ENTITY;




ENTITY bounded_curve
SUPERTYPE OF (ONEOF(polyline, b_spline_curve, trimmed_curve, bounded_pcurve, bounded_surface_curve, composite_curve))
SUBTYPE OF (curve);
END_ENTITY;




ENTITY bounded_pcurve
SUBTYPE OF (pcurve, bounded_curve);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.BOUNDED_CURVE' IN TYPEOF(SELF\pcurve.reference_to_curve.items[1]);
END_ENTITY;




ENTITY bounded_surface
SUPERTYPE OF (ONEOF(b_spline_surface, rectangular_trimmed_surface, curve_bounded_surface, rectangular_composite_surface))
SUBTYPE OF (surface);
END_ENTITY;




ENTITY bounded_surface_curve
SUBTYPE OF (surface_curve, bounded_curve);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.BOUNDED_CURVE' IN TYPEOF(SELF\surface_curve.curve_3d);
END_ENTITY;




ENTITY box_domain;

corner : cartesian_point;

xlength : positive_length_measure;

ylength : positive_length_measure;

zlength : positive_length_measure;
WHERE

wr1:
SIZEOF(
QUERY (item <* USEDIN(SELF, '')| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.BOXED_HALF_SPACE' IN TYPEOF(item)))) = 0;
END_ENTITY;




ENTITY boxed_half_space
SUBTYPE OF (half_space_solid);

enclosure : box_domain;
END_ENTITY;




ENTITY brep_with_voids
SUBTYPE OF (manifold_solid_brep);

voids : SET [1:?] OF oriented_closed_shell;
END_ENTITY;




ENTITY bus_structural_definition
SUBTYPE OF (product_definition);
UNIQUE

ur1 : id;
WHERE

wr1:
SIZEOF(
QUERY (bec <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION')| (pdr.name = 'bus composition element'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'NETWORK_NODE_DEFINITION' IN TYPEOF(bec.related_product_definition)) AND (bec.related_product_definition.frame_of_reference.name = 'functional network design') OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'BUS_STRUCTURAL_DEFINITION' IN TYPEOF(bec.related_product_definition)))) >= 1;

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATING_PROPERTY_DEFINITION')| (pdr.name = 'functional unit network terminal definition bus assignment'))) <= 1))) <= 1;
END_ENTITY;




ENTITY calendar_date
SUBTYPE OF (date);

day_component : day_in_month_number;

month_component : month_in_year_number;
WHERE

wr1:
valid_calendar_date(SELF);
END_ENTITY;




ENTITY cartesian_point
SUBTYPE OF (point);

coordinates : LIST [1:3] OF length_measure;
END_ENTITY;




ENTITY cartesian_transformation_operator
SUPERTYPE OF (ONEOF(cartesian_transformation_operator_2d, cartesian_transformation_operator_3d))
SUBTYPE OF (geometric_representation_item, functionally_defined_transformation);

axis1 : OPTIONAL direction;

axis2 : OPTIONAL direction;

local_origin : cartesian_point;

scale : OPTIONAL REAL;
DERIVE

scl : REAL := NVL(scale, 1);
WHERE

wr1:
scl > 0;
END_ENTITY;




ENTITY cartesian_transformation_operator_2d
SUBTYPE OF (cartesian_transformation_operator);
DERIVE

u : LIST [2:2] OF direction := base_axis(2, SELF\cartesian_transformation_operator.axis1, SELF\cartesian_transformation_operator.axis2, ?);
WHERE

wr1:
SELF\cartesian_transformation_operator.dim = 2;
END_ENTITY;




ENTITY cartesian_transformation_operator_3d
SUBTYPE OF (cartesian_transformation_operator);

axis3 : OPTIONAL direction;
DERIVE

u : LIST [3:3] OF direction := base_axis(3, SELF\cartesian_transformation_operator.axis1, SELF\cartesian_transformation_operator.axis2, axis3);
WHERE

wr1:
SELF\cartesian_transformation_operator.dim = 3;
END_ENTITY;




ENTITY centre_of_symmetry
SUBTYPE OF (derived_shape_aspect);
WHERE

wr1:
SIZEOF(
QUERY (sadr <* deriving_relationships| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SYMMETRIC_SHAPE_ASPECT' IN TYPEOF(sadr.related_shape_aspect)))) = 0;
END_ENTITY;




ENTITY certification;

name : label;

purpose : text;

kind : certification_type;
END_ENTITY;




ENTITY certification_assignment
ABSTRACT SUPERTYPE;

assigned_certification : certification;
END_ENTITY;




ENTITY certification_type;

description : label;
END_ENTITY;




ENTITY change
SUBTYPE OF (action_assignment);

items : SET [1:?] OF work_item;
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DIRECTED_ACTION' IN TYPEOF(SELF.assigned_action);

wr2:
unique_version_change_order(SELF.assigned_action, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN');
END_ENTITY;




ENTITY change_from_design_object_assignment
SUBTYPE OF (action_assignment);

items : SET [1:?] OF managed_design_object;
END_ENTITY;




ENTITY change_from_design_object_request_assignment
SUBTYPE OF (action_request_assignment);

items : SET [1:?] OF managed_design_object;
END_ENTITY;




ENTITY change_request
SUBTYPE OF (action_request_assignment);

items : SET [1:?] OF change_request_item;
END_ENTITY;




ENTITY change_to_design_object_assignment
SUBTYPE OF (action_assignment);

items : SET [1:?] OF managed_design_object;
END_ENTITY;




ENTITY change_to_design_object_request_assignment
SUBTYPE OF (action_request_assignment);

items : SET [1:?] OF managed_design_object;
END_ENTITY;




ENTITY character_glyph_font_usage;

character : character_glyph_symbol;

font : text_font;
END_ENTITY;




ENTITY character_glyph_style_outline;

outline_style : curve_style;
END_ENTITY;




ENTITY character_glyph_style_stroke;

stroke_style : curve_style;
END_ENTITY;




ENTITY character_glyph_symbol
SUBTYPE OF (symbol_representation);

character_box : planar_extent;

baseline_ratio : ratio_measure;
DERIVE

box_height : length_measure := character_box.size_in_y;
WHERE

wr1:
(0 <= baseline_ratio) AND (baseline_ratio <= 1);

wr2:
item_in_context(SELF.character_box, SELF\representation.context_of_items);

wr3:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POSITIVE_LENGTH_MEASURE' IN TYPEOF(SELF.box_height);
END_ENTITY;




ENTITY character_glyph_symbol_outline
SUBTYPE OF (character_glyph_symbol);

outlines : SET [1:?] OF annotation_fill_area;
WHERE

wr1:
SELF.outlines <= SELF\representation.items;
END_ENTITY;




ENTITY characterized_object;

name : label;

description : text;
END_ENTITY;




ENTITY characterized_product_category
SUBTYPE OF (characterized_object, product_category);
WHERE

wr1:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (pd.description = 'product category values') AND (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PARAMETER_ASSIGNMENT_REPRESENTATION' IN TYPEOF(pdr.used_representation)))) >= 1))) = 1;

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (pd.description = 'product category parameters') AND (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (ri <* pdr.used_representation.items| NOT (SIZEOF(TYPEOF(ri) * [ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MODEL_PARAMETER') ]) = 1))) = 0))) >= 1))) = 1;

wr3:
SELF\characterized_object.name = SELF\product_category.name;
END_ENTITY;




ENTITY circle
SUBTYPE OF (conic);

radius : positive_length_measure;
END_ENTITY;




ENTITY circular_runout_tolerance
SUBTYPE OF (geometric_tolerance_with_specified_datum_system);
WHERE

wr1:
SELF\geometric_tolerance.name = 'circular runout';
END_ENTITY;




ENTITY closed_shell
SUBTYPE OF (connected_face_set);
END_ENTITY;




ENTITY colour;
END_ENTITY;




ENTITY colour_rgb
SUBTYPE OF (colour_specification);

red : REAL;

green : REAL;

blue : REAL;
WHERE

wr1:
(0 <= red) AND (red <= 1);

wr2:
(0 <= green) AND (green <= 1);

wr3:
(0 <= blue) AND (blue <= 1);
END_ENTITY;




ENTITY colour_specification
SUBTYPE OF (colour);

name : label;
END_ENTITY;




ENTITY component_definition
SUPERTYPE OF (ONEOF(printed_component, packaged_component) ANDOR thermal_component)
SUBTYPE OF (product_definition);
WHERE

wr1:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sr_pdr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_REPRESENTATION' IN TYPEOF(pdr.used_representation)))| (sr_pdr.used_representation.name = 'planar projected shape'))) <= 1))) = 0;

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sr_pdr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_REPRESENTATION' IN TYPEOF(pdr.used_representation)))| (sr_pdr.used_representation.name = '3d bound volume shape'))) <= 1))) = 0;

wr3:
NOT (SELF\product_definition.description = 'bare die component') OR (SIZEOF(
QUERY (ip <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'instantiated part'))| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'BARE_DIE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_BARE_DIE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_BARE_DIE') ] * TYPEOF(ip.relating_product_definition)) = 1) AND (ip.relating_product_definition.frame_of_reference.name = 'physical design usage'))) = 1);

wr4:
NOT ((SELF.frame_of_reference.name = 'physical occurrence') AND (SIZEOF(
QUERY (pc1 <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (pc1\product_category.name = 'assembly module'))) >= 1)) OR (SIZEOF(
QUERY (ip <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'instantiated part'))| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_UNIT' IN TYPEOF(ip.relating_product_definition)) AND (ip.relating_product_definition.frame_of_reference.name = 'physical design usage')) AND (SIZEOF(
QUERY (pc2 <* USEDIN(ip.relating_product_definition.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (pc2\product_category.name = 'assembly module'))) >= 1))) = 1);

wr5:
NOT ((SELF.frame_of_reference.name = 'physical occurrence') AND (SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'assembly module'))) >= 1)) OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL' IN TYPEOF(sa)) AND (sa.description = 'assembly module component terminal'))) >= 2))) >= 1);

wr6:
NOT ((SELF.frame_of_reference.name = 'physical occurrence') AND (SIZEOF(
QUERY (pc1 <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (pc1\product_category.name = 'interconnect module'))) >= 1)) OR (SIZEOF(
QUERY (ip <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'instantiated part'))| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_UNIT' IN TYPEOF(ip.relating_product_definition)) AND (ip.relating_product_definition.frame_of_reference.name = 'physical design usage')) AND (SIZEOF(
QUERY (pc2 <* USEDIN(ip.relating_product_definition.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (pc2\product_category.name = 'interconnect module'))) >= 1))) = 1);

wr7:
NOT ((SELF.frame_of_reference.name = 'physical occurrence') AND (SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'interconnect module'))) >= 1)) OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL' IN TYPEOF(sa)) AND (sa.description = 'interconnect module component terminal'))) >= 2))) >= 1);

wr8:
((NOT (SELF\product_definition.description = 'mating connector') OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_WITH_ASSOCIATED_DOCUMENTS' IN TYPEOF(SELF)) AND (SIZEOF(
QUERY (doc <* SELF\product_definition_with_associated_documents.documentation_ids| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EE_SPECIFICATION' IN TYPEOF(doc)))) = 1)) OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pt_occ <* 
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| (sa.description = 'part template occurrence'))| (SIZEOF(
QUERY (it <* 
QUERY (sar <* USEDIN(pt_occ, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated template'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_TEMPLATE_DEFINITION' IN TYPEOF(it.relating_shape_aspect)) AND (it.relating_shape_aspect.description = 'printed connector template'))) = 1))) = 1))) = 0)) OR (SIZEOF(
QUERY (ip <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'instantiated part'))| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_PACKAGED_PART') ] * TYPEOF(ip.relating_product_definition)) = 1) AND (ip.relating_product_definition.description = 'packaged connector'))) = 1);

wr9:
NOT (SELF\product_definition.description = 'mating connector') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'mating connector placement'))) = 1))) = 1);

wr10:
NOT (SELF\product_definition.description = 'mating connector') OR (SIZEOF(
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'NEXT_ASSEMBLY_USAGE_OCCURRENCE' IN TYPEOF(pdr)))) = 0) AND (SIZEOF(
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'NEXT_ASSEMBLY_USAGE_OCCURRENCE' IN TYPEOF(pdr)))) = 0);

wr11:
SIZEOF(
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'instantiated part') AND (SELF.formation :=: pdr.relating_product_definition.formation))) = 1;

wr12:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sr_pdr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_REPRESENTATION' IN TYPEOF(pdr.used_representation)))| ((sr_pdr.used_representation.name = 'part template non planar 2d shape') OR (sr_pdr.used_representation.name = 'non planar 2d shape')) OR (sr_pdr.used_representation.name = 'open shell based surface'))) <= 1))) = 0;
END_ENTITY;




ENTITY component_functional_terminal
SUBTYPE OF (shape_aspect);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_FUNCTIONAL_UNIT' IN TYPEOF(SELF.of_shape.definition);

wr2:
SIZEOF(
QUERY (it <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated terminal'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FUNCTIONAL_UNIT_TERMINAL_DEFINITION' IN TYPEOF(it.relating_shape_aspect)))) = 1;

wr3:
SIZEOF(
QUERY (futba <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')| (pdr.name = 'functional unit terminal bus assignment'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'BUS_STRUCTURAL_DEFINITION' IN TYPEOF(futba.relating_property_definition.definition)))) <= 1;

wr4:
SIZEOF(
QUERY (futna <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')| (pdr.name = 'functional unit terminal node assignment'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'NETWORK_NODE_DEFINITION' IN TYPEOF(futna.relating_property_definition.definition)))) <= 1;
END_ENTITY;




ENTITY component_functional_unit
SUBTYPE OF (product_definition);
WHERE

wr1:
SELF.frame_of_reference.name = 'functional occurrence';

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_FUNCTIONAL_TERMINAL' IN TYPEOF(sa)))) >= 1))) >= 1;

wr3:
SIZEOF(
QUERY (ifu <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'instantiated functional unit'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FUNCTIONAL_UNIT' IN TYPEOF(ifu.relating_product_definition)))) = 1;

wr4:
SIZEOF(
QUERY (nc <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'network composition'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FUNCTIONAL_UNIT' IN TYPEOF(nc.relating_product_definition)) AND (nc.relating_product_definition.frame_of_reference.name = 'functional network design'))) = 1;
END_ENTITY;




ENTITY component_interface_terminal
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SELF\shape_aspect.description IN [ 'interconnect component interface terminal', 'packaged connector component interface terminal' ];

wr2:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_DEFINITION' IN TYPEOF(SELF.of_shape.definition);

wr3:
SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated feature'))) <= 1;

wr4:
SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'design usage'))) <= 1;

wr5:
NOT (SELF\shape_aspect.description = 'packaged connector component interface terminal') OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTERFACE_COMPONENT_DEFINITION' IN TYPEOF(SELF.of_shape.definition));

wr6:
NOT (SELF\shape_aspect.description = 'packaged connector component interface terminal') OR (SELF.of_shape.definition\product_definition.frame_of_reference.name = 'physical occurrence');

wr7:
NOT (SELF\shape_aspect.description = 'interconnect component interface terminal') OR (SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.related_shape_aspect.description = 'connection zone'))) = 1) AND NOT (SELF.of_shape.definition\product_definition.description IN [ 'assembly module component', 'bare die component', 'interconnect module component', 'laminate component', 'packaged component' ]);

wr8:
NOT (SELF\shape_aspect.description = 'packaged connector component interface terminal') OR SELF.product_definitional;

wr9:
NOT (SELF\shape_aspect.description = 'packaged connector component interface terminal') OR (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_COMPONENT' IN TYPEOF(SELF.of_shape.definition)) AND (SELF.of_shape.definition\product_definition.description = 'packaged connector component')) AND (SELF.of_shape.definition\product_definition.frame_of_reference.name = 'physical occurrence');

wr10:
NOT (SELF\shape_aspect.description = 'packaged connector component interface terminal') OR (SIZEOF(
QUERY (i_f <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated feature'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART_TERMINAL' IN TYPEOF(i_f.relating_shape_aspect)) AND (i_f.relating_shape_aspect.description = 'interface terminal'))) = 1);
END_ENTITY;




ENTITY component_location
SUBTYPE OF (representation);
WHERE

wr1:
SIZEOF(
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'placement fixed'))) = 1;

wr2:
SIZEOF(
QUERY (ms <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'mounting style'))| NOT (ms\descriptive_representation_item.description IN [ 'normal', 'reversed' ]))) = 0;

wr3:
NOT (SELF.context_of_items\geometric_representation_context.coordinate_space_dimension = 2) OR (SIZEOF(
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CARTESIAN_TRANSFORMATION_OPERATOR_2D' IN TYPEOF(it)))) = 1);

wr4:
NOT (SELF.context_of_items\geometric_representation_context.coordinate_space_dimension = 3) OR (SIZEOF(
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'AXIS2_PLACEMENT_3D' IN TYPEOF(it)))) = 1);
END_ENTITY;




ENTITY component_shape_aspect
SUPERTYPE OF (ONEOF(land, inter_stratum_feature) ANDOR thermal_component_shape_aspect)
SUBTYPE OF (shape_aspect);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_DEFINITION' IN TYPEOF(SELF.of_shape.definition);

wr2:
(SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTER_STRATUM_FEATURE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROBE_ACCESS_AREA'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND') ] * TYPEOF(SELF)) = 1) OR (SELF\shape_aspect.description IN [ 'component feature', 'component termination passage interface terminal', 'land interface terminal', 'non functional land interface terminal', 'printed connector component interface terminal', 'laminate component', 'laminate text component', 'conductive interconnect element with pre defined transitions', 'conductive interconnect element with user defined single transition', 'routed interconnect component', 'special symbol laminate component', 'primary stratum indicator symbol', 'stratum feature template component', 'interconnect module component surface feature' ]);

wr3:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sr_pdr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_REPRESENTATION' IN TYPEOF(pdr.used_representation)))| (sr_pdr.used_representation.name = 'planar projected shape'))) <= 1))) = 0;

wr4:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sr_pdr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_REPRESENTATION' IN TYPEOF(pdr.used_representation)))| (sr_pdr.used_representation.name = '3d bound volume shape'))) <= 1))) = 0;

wr5:
NOT (SELF\shape_aspect.description IN [ 'component feature', 'component termination passage interface terminal', 'land interface terminal', 'non functional land interface terminal', 'printed connector component interface terminal' ]) OR (SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'design usage'))) <= 1);

wr6:
NOT (SELF\shape_aspect.description IN [ 'laminate text component', 'special symbol laminate component', 'primary stratum indicator symbol', 'stratum feature template component' ]) OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_DEFINITION' IN TYPEOF(SELF.of_shape.definition)) AND (SIZEOF(
QUERY (prpc <* USEDIN(SELF.of_shape.definition\product_definition.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'interconnect module'))) >= 1);

wr7:
SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated feature'))) <= 2;

wr8:
NOT (SELF.description = 'component termination passage interface terminal') OR (SIZEOF(
QUERY (ac <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'associated component'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PLATED_PASSAGE' IN TYPEOF(ac.relating_shape_aspect)) AND (ac.relating_shape_aspect.description = 'component termination passage'))) = 1);

wr9:
NOT (SELF\shape_aspect.description = 'component termination passage interface terminal') OR (SIZEOF(
QUERY (i_f <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated feature'))| (i_f.relating_shape_aspect.description = 'component termination passage template interface terminal'))) = 1);

wr10:
NOT (SELF\shape_aspect.description = 'laminate text component') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (dri <* 
QUERY (it <* pdr.used_representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(it)))| (dri.name = 'message'))) = 1))) = 1))) = 1);

wr11:
NOT (SELF\shape_aspect.description = 'laminate text component') OR (SIZEOF(
QUERY (it <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated template'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_TEXT_TEMPLATE_DEFINITION' IN TYPEOF(it.relating_shape_aspect)))) = 1);

wr12:
NOT (SELF\shape_aspect.description IN [ 'laminate text component', 'stratum feature template component' ]) OR (SIZEOF(
QUERY (sfi <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'stratum feature implementation'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_FEATURE' IN TYPEOF(sfi.relating_shape_aspect)))) = 1);

wr13:
NOT (SELF\shape_aspect.description IN [ 'land interface terminal', 'non functional land interface terminal' ]) OR (SIZEOF(
QUERY (i_f <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated feature'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND_TEMPLATE_TERMINAL' IN TYPEOF(i_f.relating_shape_aspect)) AND (i_f.related_shape_aspect.description = 'interface terminal'))) = 1);

wr14:
NOT (SELF\shape_aspect.description = 'land interface terminal') OR (SIZEOF(
QUERY (ac <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'associated component'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND' IN TYPEOF(ac.relating_shape_aspect)) AND (ac.related_shape_aspect.description IN [ 'functional land', 'via dependent land', 'via and contact size dependent land', 'component termination passage dependent land', 'contact size dependent land', 'component termination passage and contact size dependent land' ]))) = 1);

wr15:
NOT (SELF\shape_aspect.description = 'non functional land interface terminal') OR (SIZEOF(
QUERY (ac <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'associated component'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND' IN TYPEOF(ac.relating_shape_aspect)) AND (ac.related_shape_aspect.description IN [ 'non functional land', 'via dependent non functional land', 'via and contact size dependent non functional land', 'component termination passage dependent non functional land', 'contact size dependent non functional land', 'component termination passage and contact size ' + 'dependent non functional land', 'unsupported passage dependent non functional land' ]))) = 1);

wr16:
NOT (SELF\shape_aspect.description IN [ 'conductive interconnect element with pre defined transitions', 'conductive interconnect element with ' + 'user defined single transition' ]) OR (SIZEOF(
QUERY (cc <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'composed conductor'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_FEATURE' IN TYPEOF(cc.related_shape_aspect)))) = 1);

wr17:
NOT (SELF\shape_aspect.description IN [ 'conductive interconnect element with pre defined transitions', 'conductive interconnect element with user ' + 'defined single transition' ]) OR (SIZEOF(
QUERY (ac <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'associated component'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL' IN TYPEOF(ac.related_shape_aspect)) AND (ac.related_shape_aspect.description = 'conductive interconnect element terminal'))) = 2);

wr18:
NOT (SELF\shape_aspect.description = 'printed connector component interface terminal') OR SELF.product_definitional;

wr19:
NOT (SELF\shape_aspect.description = 'printed connector component interface terminal') OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRINTED_COMPONENT' IN TYPEOF(SELF.of_shape.definition)) AND (SELF.of_shape.definition\product_definition.description = 'printed connector component');

wr20:
NOT (SELF\shape_aspect.description = 'printed connector component interface terminal') OR (SIZEOF(
QUERY (i_f <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated feature'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRINTED_PART_TEMPLATE_TERMINAL' IN TYPEOF(i_f.relating_shape_aspect)) AND (i_f.relating_shape_aspect.description = 'interface terminal'))) = 1);

wr21:
NOT (SELF\shape_aspect.description = 'routed interconnect component') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')) >= 1))) = 1);

wr22:
NOT (SELF\shape_aspect.description IN [ 'special symbol laminate component', 'primary stratum indicator symbol' ]) OR (SIZEOF(
QUERY (it <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated template'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_TEMPLATE_DEFINITION' IN TYPEOF(it.relating_shape_aspect)) AND (it.related_shape_aspect.description = 'special symbol part template'))) = 1);

wr23:
NOT (SELF\shape_aspect.description = 'stratum feature template component') OR (SIZEOF(
QUERY (it <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated template'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_TEMPLATE_DEFINITION' IN TYPEOF(it.relating_shape_aspect)) AND (it.relating_shape_aspect.description = 'stratum feature template') OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND_PHYSICAL_TEMPLATE' IN TYPEOF(it.relating_shape_aspect)))) = 1);
END_ENTITY;




ENTITY component_terminal
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SELF\shape_aspect.description IN [ 'assembly module component terminal', 'bare die component terminal', 'component termination passage join terminal', 'conductive interconnect element terminal', 'interconnect component join terminal', 'interconnect module component terminal', 'land join terminal', 'minimally defined component terminal', 'non functional land join terminal', 'packaged component join terminal', 'printed component join terminal', 'package terminal occurrence', 'via terminal' ];

wr2:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_DEFINITION' IN TYPEOF(SELF.of_shape.definition);

wr3:
SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated feature'))) <= 1;

wr4:
SIZEOF(
QUERY (at <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'associated terminals'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_CONNECTIVITY_DEFINITION' IN TYPEOF(at.relating_shape_aspect)))) <= 1;

wr5:
SIZEOF(
QUERY (cr <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'connectivity requirement'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_NETWORK' IN TYPEOF(cr.relating_shape_aspect)))) <= 1;

wr6:
SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'design usage'))) <= 1;

wr7:
NOT (SELF\shape_aspect.description IN [ 'assembly module component terminal', 'bare die component terminal', 'package terminal occurrence', 'packaged component join terminal', 'printed component join terminal' ]) OR SELF.product_definitional;

wr8:
NOT (SELF\shape_aspect.description = 'assembly module component terminal') OR (SELF.of_shape.definition.frame_of_reference.name = 'physical occurrence') AND (SIZEOF(
QUERY (prpc <* USEDIN(SELF.of_shape.definition\product_definition.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'assembly module'))) >= 1);

wr9:
NOT (SELF\shape_aspect.description = 'assembly module component terminal') OR (SIZEOF(
QUERY (i_f <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated feature'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_MODULE_TERMINAL' IN TYPEOF(i_f.relating_shape_aspect)))) = 1);

wr10:
NOT (SELF\shape_aspect.description = 'bare die component terminal') OR (SELF.of_shape.definition\product_definition.description = 'bare die component');

wr11:
NOT (SELF\shape_aspect.description = 'bare die component terminal') OR (SIZEOF(
QUERY (i_f <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated feature'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'BARE_DIE_TERMINAL' IN TYPEOF(i_f.relating_shape_aspect)))) = 1);

wr12:
NOT (SELF\shape_aspect.description = 'component termination passage join terminal') OR (SIZEOF(
QUERY (ac <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'associated component'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PLATED_PASSAGE' IN TYPEOF(ac.relating_shape_aspect)) AND (ac.relating_shape_aspect.description = 'component termination passage'))) = 1);

wr13:
NOT (SELF\shape_aspect.description = 'component termination passage join terminal') OR (SIZEOF(
QUERY (i_f <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated feature'))| (i_f.relating_shape_aspect.description = 'component termination passage template join terminal'))) = 1);

wr14:
NOT (SELF\shape_aspect.description = 'conductive interconnect element terminal') OR (SIZEOF(
QUERY (ac <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'associated component'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_SHAPE_ASPECT' IN TYPEOF(ac.relating_shape_aspect)) AND ((ac.relating_shape_aspect.description = 'conductive interconnect element with pre defined transitions') OR (ac.relating_shape_aspect.description = 'conductive interconnect element with user defined single transition')))) = 1);

wr15:
NOT (SELF\shape_aspect.description IN [ 'conductive interconnect element terminal', 'interconnect component join terminal', 'printed component join terminal' ]) OR (SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.related_shape_aspect.name = 'connection zone'))) = 1);

wr16:
NOT (SELF\shape_aspect.description = 'interconnect module component terminal') OR (SELF.of_shape.definition\product_definition.frame_of_reference.name = 'physical occurrence') AND (SIZEOF(
QUERY (prpc <* USEDIN(SELF.of_shape.definition\product_definition.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'interconnect module'))) >= 1);

wr17:
NOT (SELF\shape_aspect.description = 'interconnect module component terminal') OR (SIZEOF(
QUERY (i_f <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated feature'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTERCONNECT_MODULE_TERMINAL' IN TYPEOF(i_f.relating_shape_aspect)) AND (SIZEOF(
QUERY (pc <* USEDIN(i_f.relating_shape_aspect.of_shape.definition\product_definition.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (pc\product_category.name = 'interconnect module'))) > 0))) = 1);

wr18:
NOT (SELF\shape_aspect.description IN [ 'land join terminal', 'non functional land join terminal' ]) OR (SIZEOF(
QUERY (i_f <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated feature'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND_TEMPLATE_TERMINAL' IN TYPEOF(i_f.relating_shape_aspect)) AND (i_f.related_shape_aspect.description = 'join terminal'))) = 1);

wr19:
NOT (SELF\shape_aspect.description = 'land join terminal') OR (SIZEOF(
QUERY (ac <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'associated component'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND' IN TYPEOF(ac.relating_shape_aspect)) AND (ac.related_shape_aspect.description IN [ 'functional land', 'via dependent land', 'via and contact size dependent land', 'component termination passage dependent land', 'contact size dependent land', 'component termination passage and contact size dependent land' ]))) = 1);

wr20:
NOT (SELF\shape_aspect.description = 'minimally defined terminal') OR (SIZEOF(
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'part terminal external reference'))) = 1);

wr21:
NOT (SELF\shape_aspect.description = 'non functional land join terminal') OR (SIZEOF(
QUERY (ac <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'associated component'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND' IN TYPEOF(ac.relating_shape_aspect)) AND (ac.related_shape_aspect.description IN [ 'non functional land', 'via dependent non functional land', 'via and contact size dependent non functional land', 'component termination passage dependent non functional land', 'contact size dependent non functional land', 'component termination passage and contact size ' + 'dependent non functional land', 'unsupported passage dependent non functional land' ]))) = 1);

wr22:
NOT (SELF\shape_aspect.description = 'package terminal occurrence') OR (SIZEOF(
QUERY (ud <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'usage definition'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE_TERMINAL' IN TYPEOF(ud.relating_shape_aspect)))) = 1);

wr23:
NOT (SELF\shape_aspect.description IN [ 'package terminal occurrence', 'packaged component join terminal' ]) OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_COMPONENT' IN TYPEOF(SELF.of_shape.definition)) AND (SELF.of_shape.definition\product_definition.frame_of_reference.name = 'physical occurrence');

wr24:
NOT (SELF\shape_aspect.description = 'packaged component join terminal') OR (SIZEOF(
QUERY (i_f <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated feature'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART_TERMINAL' IN TYPEOF(i_f.relating_shape_aspect)) AND (i_f.relating_shape_aspect.description = 'join terminal'))) = 1);

wr25:
NOT (SELF\shape_aspect.description = 'packaged component join terminal') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2))) <= 2))) <= 1))) <= 1);

wr26:
NOT (SELF\shape_aspect.description = 'packaged component join terminal') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (lmwu <* 
QUERY (it <* pdr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2))| (lmwu.name = 'maximum wire length'))) <= 1))) <= 1))) <= 1);

wr27:
NOT (SELF\shape_aspect.description = 'packaged component join terminal') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (lmwu <* 
QUERY (it <* pdr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2))| (lmwu.name = 'minimum wire length'))) <= 1))) <= 1))) <= 1);

wr28:
NOT (SELF\shape_aspect.description = 'printed component join terminal') OR (SELF.of_shape.definition\product_definition.frame_of_reference.name = 'physical occurrence') AND (SIZEOF(
QUERY (prpc <* USEDIN(SELF.of_shape.definition\product_definition.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'interconnect module'))) >= 1);

wr29:
NOT (SELF\shape_aspect.description = 'printed component join terminal') OR (SIZEOF(
QUERY (i_f <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated feature'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRINTED_PART_TEMPLATE_TERMINAL' IN TYPEOF(i_f.relating_shape_aspect)) AND (i_f.relating_shape_aspect.description = 'join terminal'))) = 1);

wr30:
NOT (SELF\shape_aspect.description = 'printed component join terminal') OR (SIZEOF(
QUERY (i <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (pdr.name = 'implementation'))| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTER_STRATUM_FEATURE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_FEATURE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_SHAPE_ASPECT') ] * TYPEOF(i.relating_shape_aspect)) >= 1) OR (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_DEFINITION' IN TYPEOF(i.relating_shape_aspect.of_shape.definition)) AND (i.relating_shape_aspect.of_shape.definition\product_definition.frame_of_reference.name = 'physical occurrence')) AND (SIZEOF(
QUERY (pc <* USEDIN(i.relating_shape_aspect.of_shape.definition\product_definition.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (pc\product_category.name = 'interconnect module'))) >= 1))) = 1);

wr31:
NOT (SELF\shape_aspect.description = 'via terminal') OR (SIZEOF(
QUERY (ac <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'associated component'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PLATED_PASSAGE' IN TYPEOF(ac.relating_shape_aspect)) AND (ac.relating_shape_aspect.description IN [ 'buried via', 'interfacial connection', 'bonded conductive base blind via', 'non conductive base blind via', 'plated conductive base blind via' ]))) = 1);

wr32:
NOT (SELF\shape_aspect.description = 'via terminal') OR (SIZEOF(
QUERY (i_f <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated feature'))| (i_f.relating_shape_aspect.description = 'via template terminal'))) = 1);

wr33:
NOT (SELF\shape_aspect.description = 'interconnect component join terminal') OR (SELF.of_shape.definition\product_definition.frame_of_reference.name = 'physical occurrence') AND NOT (SELF.of_shape.definition\product_definition.description IN [ 'assembly module component', 'bare die component', 'interconnect moduled component', 'laminate component', 'packaged component' ]);

wr34:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (dri <* pdr.used_representation.items| (dri.name = 'global swappable') AND (dri.description IN [ 'true', 'false' ]))) = 1))) = 1))) <= 1;

wr35:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (dri <* pdr.used_representation.items| (dri.name = 'local swappable') AND (dri.description IN [ 'true', 'false' ]))) = 1))) = 1))) <= 1;

wr36:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (dri <* pdr.used_representation.items| (dri.name = 'swap code'))) = 1))) = 1))) <= 1;
END_ENTITY;




ENTITY composite_array_shape_aspect
SUBTYPE OF (composite_shape_aspect);
END_ENTITY;




ENTITY composite_curve
SUBTYPE OF (bounded_curve);

segments : LIST [1:?] OF composite_curve_segment;

self_intersect : LOGICAL;
DERIVE

n_segments : INTEGER := SIZEOF(segments);

closed_curve : LOGICAL := segments[n_segments].transition <> discontinuous;
WHERE

wr1:
NOT closed_curve AND (SIZEOF(
QUERY (temp <* segments| (temp.transition = discontinuous))) = 1) OR closed_curve AND (SIZEOF(
QUERY (temp <* segments| (temp.transition = discontinuous))) = 0);
END_ENTITY;




ENTITY composite_curve_on_surface
SUPERTYPE OF (boundary_curve)
SUBTYPE OF (composite_curve);
DERIVE

basis_surface : SET [0:2] OF surface := get_basis_surface(SELF);
WHERE

wr1:
SIZEOF(basis_surface) > 0;

wr2:
constraints_composite_curve_on_surface(SELF);
END_ENTITY;




ENTITY composite_curve_segment;

transition : transition_code;

same_sense : BOOLEAN;

parent_curve : curve;
INVERSE

using_curves : BAG [1:?] OF composite_curve FOR segments;
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.BOUNDED_CURVE' IN TYPEOF(parent_curve);

wr2:
SIZEOF(
QUERY (cc <* SELF.using_curves| (SIZEOF(
QUERY (rep <* using_representations(cc)| NOT item_in_context(SELF.parent_curve, rep.context_of_items))) > 0))) = 0;
END_ENTITY;




ENTITY composite_group_shape_aspect
SUBTYPE OF (composite_shape_aspect);
END_ENTITY;




ENTITY composite_shape_aspect
SUBTYPE OF (shape_aspect);
INVERSE

component_relationships : SET [2:?] OF shape_aspect_relationship FOR relating_shape_aspect;
END_ENTITY;




ENTITY composite_unit_shape_aspect
SUBTYPE OF (composite_shape_aspect);
END_ENTITY;




ENTITY concentricity_tolerance
SUBTYPE OF (geometric_tolerance_with_specified_datum_system);
WHERE

wr1:
SELF\geometric_tolerance.name = 'concentricity';
END_ENTITY;




ENTITY configuration_design;

configuration : configuration_item;

design : product_definition_formation;
UNIQUE

ur1 : configuration, design;
END_ENTITY;




ENTITY configuration_effectivity
SUBTYPE OF (product_definition_effectivity);

configuration : configuration_design;
UNIQUE

ur1 : configuration, usage, id;
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PRODUCT_DEFINITION_USAGE' IN TYPEOF(SELF\product_definition_effectivity.usage);
END_ENTITY;




ENTITY configuration_item;

id : identifier;

name : label;

description : OPTIONAL text;

item_concept : product_concept;

purpose : OPTIONAL label;
UNIQUE

ur1 : id;
END_ENTITY;




ENTITY conic
SUPERTYPE OF (ONEOF(circle, ellipse, hyperbola, parabola))
SUBTYPE OF (curve);

position : axis2_placement;
END_ENTITY;




ENTITY conical_surface
SUBTYPE OF (elementary_surface);

radius : length_measure;

semi_angle : plane_angle_measure;
WHERE

wr1:
radius >= 0;
END_ENTITY;




ENTITY connected_edge_set
SUBTYPE OF (topological_representation_item);

ces_edges : SET [1:?] OF edge;
END_ENTITY;




ENTITY connected_face_set
SUPERTYPE OF (ONEOF(closed_shell, open_shell))
SUBTYPE OF (topological_representation_item);

cfs_faces : SET [1:?] OF face;
END_ENTITY;




ENTITY connectivity_sub_structure
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL' IN TYPEOF(sar.related_shape_aspect)) OR (sar.related_shape_aspect.description = 'topological junction'))) > 1;
END_ENTITY;




ENTITY context_dependent_shape_representation;

representation_relation : shape_representation_relationship;

represented_product_relation : product_definition_shape;
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PRODUCT_DEFINITION_RELATIONSHIP' IN TYPEOF(SELF.represented_product_relation.definition);
END_ENTITY;




ENTITY context_dependent_unit
SUBTYPE OF (named_unit);

name : label;
END_ENTITY;




ENTITY contract;

name : label;

purpose : text;

kind : contract_type;
END_ENTITY;




ENTITY contract_assignment
ABSTRACT SUPERTYPE;

assigned_contract : contract;
END_ENTITY;




ENTITY contract_type;

description : label;
END_ENTITY;




ENTITY conversion_based_unit
SUBTYPE OF (named_unit);

name : label;

conversion_factor : measure_with_unit;
END_ENTITY;




ENTITY coordinated_representation_item
SUBTYPE OF (representation, representation_item);
WHERE

wr1:
SIZEOF(
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION')| (SIZEOF(USEDIN(pdr, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DATA_ENVIRONMENT.ELEMENTS')) <= 1))) <= 1;

wr2:
SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DOCUMENT_REFERENCE.ITEMS')) = 1;

wr3:
NOT (SELF\representation_item.name = 'tolerance') OR (SIZEOF(
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM' IN TYPEOF(it)))) >= 1);

wr4:
NOT (SELF\representation_item.name = 'plus minus tolerance') OR (SIZEOF(
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM' IN TYPEOF(it)))) = 3);

wr5:
NOT (SELF\representation_item.name = 'symmetrical tolerance') OR (SIZEOF(
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM' IN TYPEOF(it)))) = 2);

wr6:
NOT (SELF\representation_item.name = 'plus minus tolerance') OR ((SIZEOF(
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'basic value'))) = 1) AND (SIZEOF(
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'plus value'))) = 1)) AND (SIZEOF(
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'minus value'))) = 1);

wr7:
NOT (SELF\representation_item.name = 'symmetrical tolerance') OR (SIZEOF(
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'basic value'))) = 1) AND (SIZEOF(
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'deviation value'))) = 1);
END_ENTITY;




ENTITY coordinated_universal_time_offset;

hour_offset : hour_in_day;

minute_offset : OPTIONAL minute_in_hour;

sense : ahead_or_behind;
END_ENTITY;




ENTITY csg_shape_representation
SUBTYPE OF (shape_representation);
WHERE

wr1:
SELF.context_of_items\geometric_representation_context.coordinate_space_dimension = 3;

wr2:
SIZEOF(
QUERY (it <* SELF.items| NOT (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CSG_SOLID', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EXTRUDED_AREA_SOLID', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.REVOLVED_AREA_SOLID', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SOLID_REPLICA', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AXIS2_PLACEMENT_3D' ] * TYPEOF(it)) = 1))) = 0;

wr3:
SIZEOF(
QUERY (it <* SELF.items| (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CSG_SOLID', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EXTRUDED_AREA_SOLID', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.REVOLVED_AREA_SOLID', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SOLID_REPLICA', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' ] * TYPEOF(it)) = 1))) >= 1;

wr4:
SIZEOF(
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' IN TYPEOF(it)) AND NOT (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CSG_SHAPE_REPRESENTATION', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.FACETED_BREP_SHAPE_REPRESENTATION', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ADVANCED_BREP_SHAPE_REPRESENTATION' ] * TYPEOF(it\mapped_item.mapping_source.mapped_representation)) = 1))) = 0;
END_ENTITY;




ENTITY csg_solid
SUBTYPE OF (solid_model);

tree_root_expression : csg_select;
END_ENTITY;




ENTITY curve
SUPERTYPE OF (ONEOF(line, conic, pcurve, surface_curve, offset_curve_2d, offset_curve_3d, curve_replica))
SUBTYPE OF (geometric_representation_item);
END_ENTITY;




ENTITY curve_bounded_surface
SUBTYPE OF (bounded_surface);

basis_surface : surface;

boundaries : SET [1:?] OF boundary_curve;

implicit_outer : BOOLEAN;
WHERE

wr1:
NOT (implicit_outer AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.OUTER_BOUNDARY_CURVE' IN TYPEOF(boundaries)));

wr2:
NOT implicit_outer OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.BOUNDED_SURFACE' IN TYPEOF(basis_surface));

wr3:
SIZEOF(
QUERY (temp <* boundaries| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.OUTER_BOUNDARY_CURVE' IN TYPEOF(temp)))) <= 1;

wr4:
SIZEOF(
QUERY (temp <* boundaries| (temp\composite_curve_on_surface.basis_surface[1] <> SELF.basis_surface))) = 0;
END_ENTITY;




ENTITY curve_dimension
SUBTYPE OF (dimensional_size);
WHERE

wr1:
SELF\dimensional_size.name <> 'angular';
END_ENTITY;




ENTITY curve_replica
SUBTYPE OF (curve);

parent_curve : curve;

transformation : cartesian_transformation_operator;
WHERE

wr1:
transformation.dim = parent_curve.dim;

wr2:
acyclic_curve_replica(SELF, parent_curve);
END_ENTITY;




ENTITY curve_style;

name : label;

curve_font : curve_font_or_scaled_curve_font_select;

curve_width : size_select;

curve_colour : colour;
END_ENTITY;




ENTITY curve_style_font;

name : label;

pattern_list : LIST [1:?] OF curve_style_font_pattern;
END_ENTITY;




ENTITY curve_style_font_and_scaling;

name : label;

curve_font : curve_style_font_select;

curve_font_scaling : REAL;
END_ENTITY;




ENTITY curve_style_font_pattern;

visible_segment_length : positive_length_measure;

invisible_segment_length : positive_length_measure;
END_ENTITY;




ENTITY curve_style_with_ends_and_corners
SUBTYPE OF (curve_style);

curve_ends : squared_or_rounded;

curve_corners : squared_or_rounded;
END_ENTITY;




ENTITY curve_style_with_extension
SUBTYPE OF (curve_style);

curve_extensions : length_measure;
END_ENTITY;




ENTITY cylindrical_surface
SUBTYPE OF (elementary_surface);

radius : positive_length_measure;
END_ENTITY;




ENTITY data_environment;

name : label;

description : text;

elements : SET [1:?] OF property_definition_representation;
END_ENTITY;




ENTITY date
SUPERTYPE OF (calendar_date);

year_component : year_number;
END_ENTITY;




ENTITY date_and_time;

date_component : date;

time_component : local_time;
END_ENTITY;




ENTITY date_and_time_assignment
ABSTRACT SUPERTYPE;

assigned_date_and_time : date_and_time;

role : date_time_role;
END_ENTITY;




ENTITY date_assignment
ABSTRACT SUPERTYPE;

assigned_date : date;

role : date_role;
END_ENTITY;




ENTITY date_role;

name : label;
END_ENTITY;




ENTITY date_time_role;

name : label;
END_ENTITY;




ENTITY dated_effectivity
SUBTYPE OF (effectivity);

effectivity_start_date : date_and_time;

effectivity_end_date : OPTIONAL date_and_time;
END_ENTITY;




ENTITY datum_reference_frame
SUBTYPE OF (shape_aspect);
END_ENTITY;




ENTITY datum_system
SUBTYPE OF (shape_aspect);
END_ENTITY;




ENTITY datum_system_based_dimensional_location
SUBTYPE OF (dimensional_location);
END_ENTITY;




ENTITY definitional_representation
SUBTYPE OF (representation);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PARAMETRIC_REPRESENTATION_CONTEXT' IN TYPEOF(SELF\representation.context_of_items);
END_ENTITY;




ENTITY degenerate_pcurve
SUBTYPE OF (point);

basis_surface : surface;

reference_to_curve : definitional_representation;
WHERE

wr1:
SIZEOF(reference_to_curve\representation.items) = 1;

wr2:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CURVE' IN TYPEOF(reference_to_curve\representation.items[1]);

wr3:
reference_to_curve\representation.items[1]\geometric_representation_item.dim = 2;
END_ENTITY;




ENTITY degenerate_toroidal_surface
SUBTYPE OF (toroidal_surface);

select_outer : BOOLEAN;
WHERE

wr1:
major_radius < minor_radius;
END_ENTITY;




ENTITY delete_design_object_assignment
SUBTYPE OF (action_assignment);

items : SET [1:?] OF managed_design_object;
END_ENTITY;




ENTITY delete_design_object_request_assignment
SUBTYPE OF (action_request_assignment);

items : SET [1:?] OF managed_design_object;
END_ENTITY;




ENTITY derived_shape_aspect
SUPERTYPE OF (ONEOF(apex, centre_of_symmetry, geometric_alignment, geometric_intersection, extension, tangent))
SUBTYPE OF (shape_aspect);
INVERSE

deriving_relationships : SET [1:?] OF shape_aspect_relationship FOR relating_shape_aspect;
END_ENTITY;




ENTITY derived_unit;

elements : SET [1:?] OF derived_unit_element;
WHERE

wr1:
(SIZEOF(elements) > 1) OR (SIZEOF(elements) = 1) AND (elements[1].exponent <> 1);
END_ENTITY;




ENTITY derived_unit_element;

unit : named_unit;

exponent : REAL;
END_ENTITY;




ENTITY descriptive_representation_item
SUBTYPE OF (representation_item);

description : text;
END_ENTITY;




ENTITY design_make_from_relationship
SUBTYPE OF (product_definition_relationship);
WHERE

wr1:
SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_UNIT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FUNCTIONAL_UNIT') ] * TYPEOF(SELF.relating_product_definition)) = 1;

wr2:
SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_UNIT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FUNCTIONAL_UNIT') ] * TYPEOF(SELF.related_product_definition)) = 1;

wr3:
SIZEOF(
QUERY (pds <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_SHAPE.DEFINITION' IN TYPEOF(pds)))) = 0;
END_ENTITY;




ENTITY design_object
SUBTYPE OF (characterized_object);
WHERE

wr1:
SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DOCUMENT_REFERENCE.ITEMS')) = 1;
END_ENTITY;




ENTITY device_terminal_map
SUBTYPE OF (shape_aspect, shape_aspect_relationship);
UNIQUE

ur1 : related_shape_aspect, relating_shape_aspect;
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART_TERMINAL' IN TYPEOF(SELF.relating_shape_aspect);
END_ENTITY;




ENTITY dimensional_characteristic_representation;

dimension : dimensional_characteristic;

representation : shape_dimension_representation;
END_ENTITY;




ENTITY dimensional_exponents;

length_exponent : REAL;

mass_exponent : REAL;

time_exponent : REAL;

electric_current_exponent : REAL;

thermodynamic_temperature_exponent : REAL;

amount_of_substance_exponent : REAL;

luminous_intensity_exponent : REAL;
END_ENTITY;




ENTITY dimensional_location
SUPERTYPE OF (ONEOF(angular_location, dimensional_location_with_path))
SUBTYPE OF (shape_aspect_relationship);
END_ENTITY;




ENTITY dimensional_location_with_direction
SUBTYPE OF (dimensional_location);
WHERE

wr1:
SELF\shape_aspect_relationship.description = 'linear';
END_ENTITY;




ENTITY dimensional_location_with_path
SUBTYPE OF (dimensional_location);

path : shape_aspect;
END_ENTITY;




ENTITY dimensional_size
SUPERTYPE OF (angular_size);

applies_to : shape_aspect;

name : label;
WHERE

wr1:
applies_to.product_definitional = TRUE;
END_ENTITY;




ENTITY dimensional_size_property
SUBTYPE OF (dimensional_size, property_definition);
END_ENTITY;




ENTITY directed_action
SUBTYPE OF (executed_action);

directive : action_directive;
END_ENTITY;




ENTITY directed_dimensional_location
SUBTYPE OF (dimensional_location);
END_ENTITY;




ENTITY direction
SUBTYPE OF (geometric_representation_item);

direction_ratios : LIST [2:3] OF REAL;
WHERE

wr1:
SIZEOF(
QUERY (tmp <* direction_ratios| (tmp <> 0))) > 0;
END_ENTITY;




ENTITY discrete_shield
SUBTYPE OF (component_definition);
WHERE

wr1:
SELF.frame_of_reference.name = 'physical occurrence';

wr2:
SIZEOF(
QUERY (si <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'shielded item'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_DEFINITION' IN TYPEOF(si.relating_product_definition)))) >= 1;
END_ENTITY;




ENTITY document;

id : identifier;

name : label;

description : text;

kind : document_type;
UNIQUE

ur1 : id;
END_ENTITY;




ENTITY document_reference
ABSTRACT SUPERTYPE;

assigned_document : document;

source : label;
END_ENTITY;




ENTITY document_relationship;

name : label;

description : text;

relating_document : document;

related_document : document;
END_ENTITY;




ENTITY document_type;

product_data_type : label;
END_ENTITY;




ENTITY document_usage_constraint;

source : document;

subject_element : label;

subject_element_value : text;
END_ENTITY;




ENTITY document_with_class
SUBTYPE OF (document);

class : identifier;
END_ENTITY;




ENTITY edge
SUPERTYPE OF (ONEOF(edge_curve, oriented_edge))
SUBTYPE OF (topological_representation_item);

edge_start : vertex;

edge_end : vertex;
END_ENTITY;




ENTITY edge_based_2d_wireframe_shape_representation
SUBTYPE OF (shape_representation);
WHERE

wr1:
SIZEOF(
QUERY (it <* SELF\representation.items| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EDGE_BASED_WIREFRAME_MODEL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MAPPED_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'AXIS2_PLACEMENT_2D') ] * TYPEOF(it)) = 1))) = 0;

wr2:
SIZEOF(
QUERY (it <* SELF\representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EDGE_BASED_WIREFRAME_MODEL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MAPPED_ITEM') ] * TYPEOF(it)) = 1))) >= 1;

wr3:
SIZEOF(
QUERY (ebwm <* 
QUERY (it <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EDGE_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (eb <* ebwm\edge_based_wireframe_model.ebwm_boundary| NOT (SIZEOF(
QUERY (edges <* eb.ces_edges| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EDGE_CURVE' IN TYPEOF(edges)))) = 0))) = 0))) = 0;

wr4:
SIZEOF(
QUERY (ebwm <* 
QUERY (it <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EDGE_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (eb <* ebwm\edge_based_wireframe_model.ebwm_boundary| NOT (SIZEOF(
QUERY (pline_edges <* 
QUERY (edges <* eb.ces_edges| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'POLYLINE' IN TYPEOF(edges\edge_curve.edge_geometry)))| NOT (SIZEOF(pline_edges\edge_curve.edge_geometry\polyline.points) > 2))) = 0))) = 0))) = 0;

wr5:
SIZEOF(
QUERY (ebwm <* 
QUERY (it <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EDGE_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (eb <* ebwm\edge_based_wireframe_model.ebwm_boundary| NOT (SIZEOF(
QUERY (edges <* eb.ces_edges| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'VERTEX_POINT' IN TYPEOF(edges.edge_start)) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'VERTEX_POINT' IN TYPEOF(edges.edge_end))))) = 0))) = 0))) = 0;

wr6:
SIZEOF(
QUERY (ebwm <* 
QUERY (it <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EDGE_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (eb <* ebwm\edge_based_wireframe_model.ebwm_boundary| NOT (SIZEOF(
QUERY (edges <* eb.ces_edges| NOT valid_2d_wireframe_edge_curve(edges\edge_curve.edge_geometry, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN'))) = 0))) = 0))) = 0;

wr7:
SIZEOF(
QUERY (ebwm <* 
QUERY (it <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EDGE_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (eb <* ebwm\edge_based_wireframe_model.ebwm_boundary| NOT (SIZEOF(
QUERY (edges <* eb.ces_edges| NOT (valid_wireframe_vertex_point(edges.edge_start\vertex_point.vertex_geometry, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN') AND valid_wireframe_vertex_point(edges.edge_end\vertex_point.vertex_geometry, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN')))) = 0))) = 0))) = 0;

wr8:
SIZEOF(
QUERY (ebwm <* 
QUERY (it <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EDGE_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (eb <* ebwm\edge_based_wireframe_model.ebwm_boundary| NOT (SIZEOF(
QUERY (con_edges <* 
QUERY (edges <* eb.ces_edges| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CONIC' IN TYPEOF(edges\edge_curve.edge_geometry)))| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'AXIS2_PLACEMENT_2D' IN TYPEOF(con_edges\edge_curve.edge_geometry\conic.position)))) = 0))) = 0))) = 0;

wr9:
SIZEOF(
QUERY (mi <* 
QUERY (it <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MAPPED_ITEM' IN TYPEOF(it)))| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EDGE_BASED_2D_WIREFRAME_SHAPE_REPRESENTATION' IN TYPEOF(mi\mapped_item.mapping_source.mapped_representation)))) = 0;

wr10:
SELF\representation.context_of_items\geometric_representation_context.coordinate_space_dimension = 2;
END_ENTITY;




ENTITY edge_based_wireframe_model
SUBTYPE OF (geometric_representation_item);

ebwm_boundary : SET [1:?] OF connected_edge_set;
END_ENTITY;




ENTITY edge_based_wireframe_shape_representation
SUBTYPE OF (shape_representation);
WHERE

wr1:
SIZEOF(
QUERY (it <* SELF.items| NOT (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_BASED_WIREFRAME_MODEL', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AXIS2_PLACEMENT_3D' ] * TYPEOF(it)) = 1))) = 0;

wr2:
SIZEOF(
QUERY (it <* SELF.items| (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_BASED_WIREFRAME_MODEL', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' ] * TYPEOF(it)) = 1))) >= 1;

wr3:
SIZEOF(
QUERY (ebwm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (eb <* ebwm\edge_based_wireframe_model.ebwm_boundary| NOT (SIZEOF(
QUERY (edges <* eb.ces_edges| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_CURVE' IN TYPEOF(edges)))) = 0))) = 0))) = 0;

wr4:
SIZEOF(
QUERY (ebwm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (eb <* ebwm\edge_based_wireframe_model.ebwm_boundary| NOT (SIZEOF(
QUERY (pline_edges <* 
QUERY (edges <* eb.ces_edges| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POLYLINE' IN TYPEOF(edges\edge_curve.edge_geometry)))| NOT (SIZEOF(pline_edges\edge_curve.edge_geometry\polyline.points) > 2))) = 0))) = 0))) = 0;

wr5:
SIZEOF(
QUERY (ebwm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (eb <* ebwm\edge_based_wireframe_model.ebwm_boundary| NOT (SIZEOF(
QUERY (edges <* eb.ces_edges| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_POINT' IN TYPEOF(edges.edge_start)) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_POINT' IN TYPEOF(edges.edge_end))))) = 0))) = 0))) = 0;

wr6:
SIZEOF(
QUERY (ebwm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (eb <* ebwm\edge_based_wireframe_model.ebwm_boundary| NOT (SIZEOF(
QUERY (edges <* eb.ces_edges| NOT valid_wireframe_edge_curve(edges\edge_curve.edge_geometry))) = 0))) = 0))) = 0;

wr7:
SIZEOF(
QUERY (ebwm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (eb <* ebwm\edge_based_wireframe_model.ebwm_boundary| NOT (SIZEOF(
QUERY (edges <* eb.ces_edges| NOT (valid_wireframe_vertex_point(edges.edge_start\vertex_point.vertex_geometry, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_BASED_WIREFRAME_MODEL') AND valid_wireframe_vertex_point(edges.edge_end\vertex_point.vertex_geometry, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_BASED_WIREFRAME_MODEL')))) = 0))) = 0))) = 0;

wr8:
SIZEOF(
QUERY (mi <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' IN TYPEOF(it)))| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EDGE_BASED_WIREFRAME_SHAPE_REPRESENTATION' IN TYPEOF(mi\mapped_item.mapping_source.mapped_representation)))) = 0;

wr9:
SELF.context_of_items\geometric_representation_context.coordinate_space_dimension = 3;
END_ENTITY;




ENTITY edge_curve
SUBTYPE OF (edge, geometric_representation_item);

edge_geometry : curve;

same_sense : BOOLEAN;
END_ENTITY;




ENTITY edge_loop
SUBTYPE OF (loop, path);
DERIVE

ne : INTEGER := SIZEOF(SELF\path.edge_list);
WHERE

wr1:
SELF\path.edge_list[1].edge_start :=: SELF\path.edge_list[ne].edge_end;
END_ENTITY;




ENTITY ee_specification
SUBTYPE OF (document);
WHERE

wr1:
SIZEOF(
QUERY (apoa <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_PERSON_AND_ORGANIZATION_ASSIGNMENT.ITEMS')| (apoa.role.name = 'document source'))) + SIZEOF(
QUERY (apoa <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_ORGANIZATION_ASSIGNMENT.ITEMS')| (apoa.role.name = 'document source'))) >= 1;

wr2:
SELF\document.kind.product_data_type IN [ 'assembly technology specification', 'design specification', 'fabrication technology specification', 'interface specification', 'language reference manual', 'lead form specification', 'material specification', 'process specification', 'surface finish specification', 'test specification' ];
END_ENTITY;




ENTITY effectivity
SUPERTYPE OF (ONEOF(serial_numbered_effectivity, dated_effectivity, lot_effectivity));

id : identifier;
END_ENTITY;




ENTITY electric_current_measure_with_unit
SUBTYPE OF (measure_with_unit);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ELECTRIC_CURRENT_UNIT' IN TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY;




ENTITY electric_current_unit
SUBTYPE OF (named_unit);
WHERE

wr1:
((((((SELF\named_unit.dimensions.length_exponent = 0) AND (SELF\named_unit.dimensions.mass_exponent = 0)) AND (SELF\named_unit.dimensions.time_exponent = 0)) AND (SELF\named_unit.dimensions.electric_current_exponent = 1)) AND (SELF\named_unit.dimensions.thermodynamic_temperature_exponent = 0)) AND (SELF\named_unit.dimensions.amount_of_substance_exponent = 0)) AND (SELF\named_unit.dimensions.luminous_intensity_exponent = 0);
END_ENTITY;




ENTITY electrical_network
SUBTYPE OF (functional_unit);
END_ENTITY;




ENTITY elementary_surface
SUPERTYPE OF (ONEOF(plane, cylindrical_surface, conical_surface, spherical_surface, toroidal_surface))
SUBTYPE OF (surface);

position : axis2_placement_3d;
END_ENTITY;




ENTITY ellipse
SUBTYPE OF (conic);

semi_axis_1 : positive_length_measure;

semi_axis_2 : positive_length_measure;
END_ENTITY;




ENTITY evaluated_degenerate_pcurve
SUBTYPE OF (degenerate_pcurve);

equivalent_point : cartesian_point;
END_ENTITY;




ENTITY executed_action
SUBTYPE OF (action);
END_ENTITY;




ENTITY expanded_uncertainty
SUBTYPE OF (standard_uncertainty);

coverage_factor : REAL;
END_ENTITY;




ENTITY extension
SUBTYPE OF (derived_shape_aspect);
WHERE

wr1:
SIZEOF(SELF\derived_shape_aspect.deriving_relationships) = 1;
END_ENTITY;




ENTITY external_definition
SUBTYPE OF (characterized_object, externally_defined_item);
WHERE

wr1:
SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DOCUMENT_REFERENCE.ITEMS')) = 1;
END_ENTITY;




ENTITY external_source;

source_id : source_item;
END_ENTITY;




ENTITY external_source_relationship;

name : label;

description : text;

relating_source : external_source;

related_source : external_source;
END_ENTITY;




ENTITY externally_defined_assembly_definition
SUBTYPE OF (externally_defined_physical_unit);
WHERE

wr1:
SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'assembly module'))) >= 1;

wr2:
NOT (SELF.frame_of_reference.name = 'physical design usage') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_MODULE_TERMINAL' IN TYPEOF(sa)) AND (sa.description = 'pca terminal'))) >= 2))) = 0);
END_ENTITY;




ENTITY externally_defined_bare_die
SUBTYPE OF (externally_defined_physical_unit);
WHERE

wr1:
SIZEOF(
QUERY (ifdu <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.' + 'RELATED_PRODUCT_DEFINITION')| (pdr.name = 'implemented function'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FUNCTIONAL_UNIT' IN TYPEOF(ifdu.relating_product_definition)) AND (ifdu.relating_product_definition.frame_of_reference.name = 'functional design usage'))) = 1;

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (dut <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')| (pdr.name = 'device unit technology'))| (dut.relating_property_definition.name = 'unit technology'))) = 1))) = 1;

wr3:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'BARE_DIE_TERMINAL' IN TYPEOF(sa)))) >= 2))) = 0;
END_ENTITY;




ENTITY externally_defined_curve_font
SUBTYPE OF (externally_defined_item);
END_ENTITY;




ENTITY externally_defined_functional_unit
SUBTYPE OF (functional_unit, externally_defined_item);
END_ENTITY;




ENTITY externally_defined_hatch_style
SUBTYPE OF (externally_defined_item, geometric_representation_item);
END_ENTITY;




ENTITY externally_defined_interconnect_definition
SUBTYPE OF (externally_defined_physical_unit);
WHERE

wr1:
SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'interconnect module'))) >= 1;
END_ENTITY;




ENTITY externally_defined_item;

item_id : source_item;

source : external_source;
END_ENTITY;




ENTITY externally_defined_package
SUBTYPE OF (externally_defined_physical_unit);
WHERE

wr1:
SELF.frame_of_reference.name = 'physical design usage';

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'registered case style'))) >= 1))) = 0;

wr3:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sr_pdr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_REPRESENTATION' IN TYPEOF(pdr)))| (sr_pdr.used_representation.name = 'seating plane'))) = 1))) = 0;

wr4:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE_BODY' IN TYPEOF(sa)))) <= 1))) = 0;

wr5:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE_TERMINAL' IN TYPEOF(sa)))) >= 1))) = 0;

wr6:
NOT (SELF\product_definition.description = 'as installed package') OR (SIZEOF(
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'package preparation') AND (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_PACKAGE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_PACKAGE') ] * TYPEOF(pdr.relating_product_definition)) = 1))) = 1);
END_ENTITY;




ENTITY externally_defined_packaged_connector
SUBTYPE OF (externally_defined_packaged_part);
END_ENTITY;




ENTITY externally_defined_packaged_part
SUPERTYPE OF (externally_defined_packaged_connector)
SUBTYPE OF (externally_defined_physical_unit);
WHERE

wr1:
NOT (SELF.frame_of_reference.name = 'physical design usage') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART_TERMINAL' IN TYPEOF(sa)))) >= 2))) = 0);

wr2:
NOT (SELF.frame_of_reference.name = 'physical design usage') OR (SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MATERIAL_DESIGNATION.DEFINITIONS')) = 1);

wr3:
NOT (SELF.frame_of_reference.name = 'physical design usage') OR (SIZEOF(
QUERY (ifu <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'implemented function'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FUNCTIONAL_UNIT' IN TYPEOF(ifu.relating_product_definition)) AND (ifu.relating_product_definition.frame_of_reference.name = 'functional design usage'))) = 1);

wr4:
NOT (SELF.frame_of_reference.name = 'physical design usage') OR (SIZEOF(
QUERY (upkg <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION')| (pdr.name = 'used package'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE' IN TYPEOF(upkg.related_product_definition)))) = 1);

wr5:
NOT (SELF\product_definition.description = 'as installed packaged part') OR (SIZEOF(
QUERY (bpp <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'base packaged part'))| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_PACKAGED_PART') ] * TYPEOF(bpp.relating_product_definition)) = 1) AND (bpp.relating_product_definition.frame_of_reference.name = 'physical design usage'))) >= 1);

wr6:
NOT (SELF\product_definition.description = 'as installed packaged part') OR (SIZEOF(
QUERY (upkg <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'used package'))| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_PACKAGED_PART') ] * TYPEOF(upkg.relating_product_definition)) = 1))) >= 1);
END_ENTITY;




ENTITY externally_defined_physical_unit
SUPERTYPE OF (library_defined_physical_unit ANDOR ONEOF(externally_defined_package, externally_defined_packaged_part, externally_defined_bare_die, externally_defined_assembly_definition, externally_defined_interconnect_definition))
SUBTYPE OF (physical_unit, externally_defined_item);
END_ENTITY;




ENTITY externally_defined_representation_item
SUBTYPE OF (externally_defined_item, representation_item);
WHERE

wr1:
SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DOCUMENT_REFERENCE.ITEMS')) = 1;
END_ENTITY;




ENTITY externally_defined_symbol
SUBTYPE OF (externally_defined_item);
END_ENTITY;




ENTITY externally_defined_text_font
SUBTYPE OF (externally_defined_item);
END_ENTITY;




ENTITY externally_defined_tile
SUBTYPE OF (externally_defined_item);
END_ENTITY;




ENTITY externally_defined_tile_style
SUBTYPE OF (externally_defined_item, geometric_representation_item);
END_ENTITY;




ENTITY extruded_area_solid
SUBTYPE OF (swept_area_solid);

extruded_direction : direction;

depth : positive_length_measure;
WHERE

wr1:
dot_product(SELF\swept_area_solid.swept_area.basis_surface\elementary_surface.position.p[3], extruded_direction) <> 0;
END_ENTITY;




ENTITY fabrication_joint
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SIZEOF(
QUERY (ff <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'fabrication features'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL' IN TYPEOF(ff.related_shape_aspect)) AND (ff.related_shape_aspect.description IN [ 'via terminal', 'printed component join terminal', 'non functional land join terminal', 'land join terminal', 'conductive interconnect element terminal', 'component termination passage join terminal' ]))) = 2;

wr2:
SIZEOF(
QUERY (ajm <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'auxiliary joint material'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND' IN TYPEOF(ajm.related_shape_aspect)) OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_SHAPE_ASPECT' IN TYPEOF(ajm.related_shape_aspect)) AND (ajm.related_shape_aspect.description = 'stratum feature template component'))) <= 1;
END_ENTITY;




ENTITY face
SUPERTYPE OF (ONEOF(face_surface, oriented_face))
SUBTYPE OF (topological_representation_item);

bounds : SET [1:?] OF face_bound;
WHERE

wr1:
NOT mixed_loop_type_set(list_to_set(list_face_loops(SELF)));

wr2:
SIZEOF(
QUERY (temp <* bounds| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.FACE_OUTER_BOUND' IN TYPEOF(temp)))) <= 1;
END_ENTITY;




ENTITY face_bound
SUBTYPE OF (topological_representation_item);

bound : loop;

orientation : BOOLEAN;
END_ENTITY;




ENTITY face_outer_bound
SUBTYPE OF (face_bound);
END_ENTITY;




ENTITY face_surface
SUBTYPE OF (face, geometric_representation_item);

face_geometry : surface;

same_sense : BOOLEAN;
END_ENTITY;




ENTITY faceted_brep
SUBTYPE OF (manifold_solid_brep);
END_ENTITY;




ENTITY faceted_brep_shape_representation
SUBTYPE OF (shape_representation);
WHERE

wr1:
SIZEOF(
QUERY (it <* SELF.items| NOT (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.FACETED_BREP', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AXIS2_PLACEMENT_3D' ] * TYPEOF(it)) = 1))) = 0;

wr2:
SIZEOF(
QUERY (it <* SELF.items| (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.FACETED_BREP', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' ] * TYPEOF(it)) = 1))) > 0;

wr3:
SIZEOF(
QUERY (fbrep <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.FACETED_BREP' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (csh <* msb_shells(fbrep, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN')| NOT (SIZEOF(
QUERY (fcs <* csh.cfs_faces| NOT ((('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.FACE_SURFACE' IN TYPEOF(fcs)) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PLANE' IN TYPEOF(fcs\face_surface.face_geometry))) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CARTESIAN_POINT' IN TYPEOF(fcs\face_surface.face_geometry\elementary_surface.position.location))))) = 0))) = 0))) = 0;

wr4:
SIZEOF(
QUERY (fbrep <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.FACETED_BREP' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (csh <* msb_shells(fbrep, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN')| NOT (SIZEOF(
QUERY (fcs <* csh.cfs_faces| NOT (SIZEOF(
QUERY (bnds <* fcs.bounds| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.FACE_OUTER_BOUND' IN TYPEOF(bnds)))) = 1))) = 0))) = 0))) = 0;

wr5:
SIZEOF(
QUERY (msb <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MANIFOLD_SOLID_BREP' IN TYPEOF(it)))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ORIENTED_CLOSED_SHELL' IN TYPEOF(msb\manifold_solid_brep.outer)))) = 0;

wr6:
SIZEOF(
QUERY (brv <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.BREP_WITH_VOIDS' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (csh <* brv\brep_with_voids.voids| csh\oriented_closed_shell.orientation)) = 0))) = 0;

wr7:
SIZEOF(
QUERY (mi <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' IN TYPEOF(it)))| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.FACETED_BREP_SHAPE_REPRESENTATION' IN TYPEOF(mi\mapped_item.mapping_source.mapped_representation)))) = 0;
END_ENTITY;




ENTITY fiducial
SUBTYPE OF (component_shape_aspect);
WHERE

wr1:
('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_DEFINITION' IN TYPEOF(SELF.of_shape.definition)) AND (SIZEOF(
QUERY (prpc <* USEDIN(SELF.of_shape.definition.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'interconnect module'))) >= 1);
END_ENTITY;




ENTITY fiducial_part_feature
SUBTYPE OF (part_tooling_feature);
END_ENTITY;




ENTITY fiducial_stratum_feature
SUBTYPE OF (stratum_feature);
END_ENTITY;




ENTITY fill_area_style;

name : label;

fill_styles : SET [1:?] OF fill_style_select;
WHERE

wr1:
SIZEOF(
QUERY (fill_style <* SELF.fill_styles| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FILL_AREA_STYLE_COLOUR' IN TYPEOF(fill_style)))) <= 1;
END_ENTITY;




ENTITY fill_area_style_colour;

name : label;

fill_colour : colour;
END_ENTITY;




ENTITY fill_area_style_hatching
SUBTYPE OF (geometric_representation_item);

hatch_line_appearance : curve_style;

start_of_next_hatch_line : one_direction_repeat_factor;

point_of_reference_hatch_line : cartesian_point;

pattern_start : cartesian_point;

hatch_line_angle : plane_angle_measure;
END_ENTITY;




ENTITY fill_area_style_tile_coloured_region
SUBTYPE OF (geometric_representation_item);

closed_curve : curve_or_annotation_curve_occurrence;

region_colour : colour;
END_ENTITY;




ENTITY fill_area_style_tile_curve_with_style
SUBTYPE OF (geometric_representation_item);

styled_curve : annotation_curve_occurrence;
END_ENTITY;




ENTITY fill_area_style_tile_symbol_with_style
SUBTYPE OF (geometric_representation_item);

symbol : annotation_symbol_occurrence;
END_ENTITY;




ENTITY fill_area_style_tiles
SUBTYPE OF (geometric_representation_item);

tiling_pattern : two_direction_repeat_factor;

tiles : SET [1:?] OF fill_area_style_tile_shape_select;

tiling_scale : positive_ratio_measure;
END_ENTITY;




ENTITY functional_terminal_group
SUBTYPE OF (group);
WHERE

wr1:
SIZEOF(
QUERY (aga <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GROUP_ASSIGNMENT.ASSIGNED_GROUP')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_GROUP_ASSIGNMENT' IN TYPEOF(aga)) AND (SIZEOF(
QUERY (dri <* aga.items| (dri.name = 'functional group type'))) = 1))) = 1;
END_ENTITY;




ENTITY functional_unit
SUPERTYPE OF ((externally_defined_functional_unit ANDOR electrical_network) ANDOR thermal_network)
SUBTYPE OF (product_definition);
WHERE

wr1:
SELF.frame_of_reference.name IN [ 'functional design usage', 'functional network design' ];

wr2:
NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_WITH_ASSOCIATED_DOCUMENTS' IN TYPEOF(SELF)) OR (SIZEOF(
QUERY (docs <* SELF\product_definition_with_associated_documents.documentation_ids| (docs.kind.product_data_type = 'CAD filename'))) <= 1);

wr3:
SIZEOF(
QUERY (adta <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DATE_AND_TIME_ASSIGNMENT.ITEMS')| (adta.role.name = 'creation date'))) + SIZEOF(
QUERY (ada <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DATE_ASSIGNMENT.ITEMS')| (ada.role.name = 'creation date'))) = 1;

wr4:
SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_APPROVAL_ASSIGNMENT.ITEMS')) = 1;

wr5:
SIZEOF(
QUERY (apoa <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_PERSON_AND_ORGANIZATION_ASSIGNMENT.ITEMS')| (apoa.role.name = 'creator'))) + SIZEOF(
QUERY (apoa <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_ORGANIZATION_ASSIGNMENT.ITEMS')| (apoa.role.name = 'creator'))) >= 1;

wr6:
SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_SECURITY_CLASSIFICATION_ASSIGNMENT.ITEMS')) = 1;

wr7:
NOT (SELF.frame_of_reference.name = 'functional network design') OR (SIZEOF(
QUERY (du <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.' + 'RELATED_PRODUCT_DEFINITION')| (pdr.name = 'design usage'))| (du.relating_product_definition.frame_of_reference.name = 'functional design usage'))) = 1);
END_ENTITY;




ENTITY functional_unit_terminal_definition
SUBTYPE OF (shape_aspect);
WHERE

wr1:
('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FUNCTIONAL_UNIT' IN TYPEOF(SELF.of_shape.definition)) AND (SELF.of_shape.definition\product_definition.frame_of_reference.name = 'functional design usage');

wr2:
SIZEOF(
QUERY (pds <* 
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION' IN TYPEOF(pd)))| (SIZEOF(
QUERY (funtdba <* 
QUERY (pdr <* USEDIN(pds, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')| (pdr.name = 'functional unit network terminal definition bus assignment'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'BUS_STRUCTURAL_DEFINITION' IN TYPEOF(funtdba.relating_property_definition.definition)))) <= 1))) = 1;

wr3:
SIZEOF(
QUERY (pds <* 
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION' IN TYPEOF(pd)))| (SIZEOF(
QUERY (funtdna <* 
QUERY (pdr <* USEDIN(pds, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')| (pdr.name = 'functional unit network terminal definition node assignment'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'NETWORK_NODE_DEFINITION' IN TYPEOF(funtdna.relating_property_definition.definition)))) <= 1))) = 1;
END_ENTITY;




ENTITY functionally_defined_transformation;

name : label;

description : text;
END_ENTITY;




ENTITY geometric_alignment
SUBTYPE OF (derived_shape_aspect);
WHERE

wr1:
SIZEOF(SELF\derived_shape_aspect.deriving_relationships) > 1;
END_ENTITY;




ENTITY geometric_curve_set
SUBTYPE OF (geometric_set);
WHERE

wr1:
SIZEOF(
QUERY (temp <* SELF\geometric_set.elements| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SURFACE' IN TYPEOF(temp)))) = 0;
END_ENTITY;




ENTITY geometric_intersection
SUBTYPE OF (derived_shape_aspect);
WHERE

wr1:
SIZEOF(SELF\derived_shape_aspect.deriving_relationships) > 1;
END_ENTITY;




ENTITY geometric_representation_context
SUBTYPE OF (representation_context);

coordinate_space_dimension : dimension_count;
END_ENTITY;




ENTITY geometric_representation_item
SUPERTYPE OF (ONEOF(point, direction, vector, placement, cartesian_transformation_operator, curve, surface, edge_curve, face_surface, poly_loop, vertex_point, solid_model, boolean_result, sphere, right_circular_cone, right_circular_cylinder, torus, block, right_angular_wedge, half_space_solid, shell_based_surface_model, shell_based_wireframe_model, edge_based_wireframe_model, geometric_set))
SUBTYPE OF (representation_item);
DERIVE

dim : dimension_count := dimension_of(SELF);
WHERE

wr1:
SIZEOF(
QUERY (using_rep <* using_representations(SELF)| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_REPRESENTATION_CONTEXT' IN TYPEOF(using_rep.context_of_items)))) = 0;
END_ENTITY;




ENTITY geometric_set
SUPERTYPE OF (geometric_curve_set)
SUBTYPE OF (geometric_representation_item);

elements : SET [1:?] OF geometric_set_select;
END_ENTITY;




ENTITY geometric_tolerance;

name : label;

description : text;

magnitude : measure_with_unit;

toleranced_shape_aspect : shape_aspect;
WHERE

wr1:
magnitude.value_component >= 0;
END_ENTITY;




ENTITY geometric_tolerance_group
SUBTYPE OF (property_definition);
WHERE

wr1:
SELF\property_definition.description IN [ 'separate requirement', 'simultaneous requirement' ];
END_ENTITY;




ENTITY geometric_tolerance_relationship;

name : label;

description : text;

relating_geometric_tolerance : geometric_tolerance;

related_geometric_tolerance : geometric_tolerance;
END_ENTITY;




ENTITY geometric_tolerance_with_specified_datum_system
SUBTYPE OF (physical_unit_geometric_tolerance);
END_ENTITY;




ENTITY geometrically_bounded_2d_wireframe_representation
SUBTYPE OF (shape_representation);
WHERE

wr1:
SELF.context_of_items\geometric_representation_context.coordinate_space_dimension = 2;

wr2:
SIZEOF(
QUERY (item <* SELF.items| NOT (SIZEOF(TYPEOF(item) * [ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_CURVE_SET', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AXIS2_PLACEMENT_2D', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' ]) = 1))) = 0;

wr3:
SIZEOF(
QUERY (item <* SELF.items| (SIZEOF(TYPEOF(item) * [ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_CURVE_SET', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' ]) = 1))) >= 1;

wr4:
SIZEOF(
QUERY (mi <* 
QUERY (item <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' IN TYPEOF(item)))| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GEOMETRICALLY_BOUNDED_2D_WIREFRAME_REPRESENTATION' IN TYPEOF(mi\mapped_item.mapping_source.mapped_representation)))) = 0;

wr5:
SIZEOF(
QUERY (gcs <* 
QUERY (item <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_CURVE_SET' IN TYPEOF(item)))| NOT (SIZEOF(
QUERY (elem <* gcs\geometric_set.elements| NOT (SIZEOF(TYPEOF(elem) * [ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.B_SPLINE_CURVE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CIRCLE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.COMPOSITE_CURVE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ELLIPSE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.OFFSET_CURVE_2D', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POINT', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POLYLINE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.TRIMMED_CURVE' ]) = 1))) = 0))) = 0;

wr6:
SIZEOF(
QUERY (gcs <* 
QUERY (item <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_CURVE_SET' IN TYPEOF(item)))| NOT (SIZEOF(
QUERY (crv <* 
QUERY (elem <* gcs\geometric_set.elements| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CURVE' IN TYPEOF(elem)))| NOT valid_basis_curve_in_2d_wireframe(crv, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN'))) = 0))) = 0;

wr7:
SIZEOF(
QUERY (gcs <* 
QUERY (item <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_CURVE_SET' IN TYPEOF(item)))| NOT (SIZEOF(
QUERY (pnt <* 
QUERY (elem <* gcs\geometric_set.elements| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POINT' IN TYPEOF(elem)))| NOT (SIZEOF(TYPEOF(pnt) * [ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CARTESIAN_POINT', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POINT_ON_CURVE' ]) = 1))) = 0))) = 0;

wr8:
SIZEOF(
QUERY (gcs <* 
QUERY (item <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_CURVE_SET' IN TYPEOF(item)))| NOT (SIZEOF(
QUERY (pl <* 
QUERY (elem <* gcs\geometric_set.elements| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POLYLINE' IN TYPEOF(elem)))| NOT (SIZEOF(pl\polyline.points) > 2))) = 0))) = 0;
END_ENTITY;




ENTITY geometrically_bounded_surface_shape_representation
SUBTYPE OF (shape_representation);
WHERE

wr1:
SIZEOF(
QUERY (it <* SELF.items| NOT (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_SET', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AXIS2_PLACEMENT_3D' ] * TYPEOF(it)) = 1))) = 0;

wr2:
SIZEOF(
QUERY (it <* SELF.items| (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_SET', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' ] * TYPEOF(it)) = 1))) > 0;

wr3:
SIZEOF(
QUERY (mi <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' IN TYPEOF(it)))| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GEOMETRICALLY_BOUNDED_SURFACE_SHAPE_REPRESENTATION' IN TYPEOF(mi\mapped_item.mapping_source.mapped_representation)))) = 0;

wr4:
SIZEOF(
QUERY (gs <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_SET' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (pnt <* 
QUERY (gsel <* gs\geometric_set.elements| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POINT' IN TYPEOF(gsel)))| NOT gbsf_check_point(pnt))) = 0))) = 0;

wr5:
SIZEOF(
QUERY (gs <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_SET' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (cv <* 
QUERY (gsel <* gs\geometric_set.elements| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CURVE' IN TYPEOF(gsel)))| NOT gbsf_check_curve(cv))) = 0))) = 0;

wr6:
SIZEOF(
QUERY (gs <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_SET' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (sf <* 
QUERY (gsel <* gs\geometric_set.elements| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SURFACE' IN TYPEOF(gsel)))| NOT gbsf_check_surface(sf))) = 0))) = 0;

wr7:
SIZEOF(
QUERY (gs <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_SET' IN TYPEOF(it)))| (SIZEOF(
QUERY (gsel <* gs\geometric_set.elements| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SURFACE' IN TYPEOF(gsel)))) > 0))) > 0;
END_ENTITY;




ENTITY geometrically_bounded_wireframe_shape_representation
SUBTYPE OF (shape_representation);
WHERE

wr1:
SIZEOF(
QUERY (it <* SELF.items| NOT (SIZEOF(TYPEOF(it) * [ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_CURVE_SET', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AXIS2_PLACEMENT_3D', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' ]) = 1))) = 0;

wr2:
SIZEOF(
QUERY (it <* SELF.items| (SIZEOF(TYPEOF(it) * [ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_CURVE_SET', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' ]) = 1))) >= 1;

wr3:
SIZEOF(
QUERY (gcs <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_CURVE_SET' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (crv <* 
QUERY (elem <* gcs\geometric_set.elements| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CURVE' IN TYPEOF(elem)))| NOT valid_geometrically_bounded_wf_curve(crv))) = 0))) = 0;

wr4:
SIZEOF(
QUERY (gcs <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_CURVE_SET' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (pnts <* 
QUERY (elem <* gcs\geometric_set.elements| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POINT' IN TYPEOF(elem)))| NOT valid_geometrically_bounded_wf_point(pnts))) = 0))) = 0;

wr5:
SIZEOF(
QUERY (gcs <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_CURVE_SET' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (cnc <* 
QUERY (elem <* gcs\geometric_set.elements| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CONIC' IN TYPEOF(elem)))| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AXIS2_PLACEMENT_3D' IN TYPEOF(cnc\conic.position)))) = 0))) = 0;

wr6:
SIZEOF(
QUERY (gcs <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_CURVE_SET' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (pline <* 
QUERY (elem <* gcs\geometric_set.elements| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POLYLINE' IN TYPEOF(elem)))| NOT (SIZEOF(pline\polyline.points) > 2))) = 0))) = 0;

wr7:
SIZEOF(
QUERY (mi <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' IN TYPEOF(it)))| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GEOMETRICALLY_BOUNDED_WIREFRAME_SHAPE_REPRESENTATION' IN TYPEOF(mi\mapped_item.mapping_source.mapped_representation)))) = 0;
END_ENTITY;




ENTITY global_uncertainty_assigned_context
SUBTYPE OF (representation_context);

uncertainty : SET [1:?] OF uncertainty_measure_with_unit;
END_ENTITY;




ENTITY global_unit_assigned_context
SUBTYPE OF (representation_context);

units : SET [1:?] OF unit;
END_ENTITY;




ENTITY group;

name : label;

description : text;
END_ENTITY;




ENTITY group_assignment
ABSTRACT SUPERTYPE;

assigned_group : group;
END_ENTITY;




ENTITY group_product_definition
SUBTYPE OF (component_definition);
WHERE

wr1:
SELF.frame_of_reference.name = 'design requirement';

wr2:
NOT (SELF.description = 'placement group') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REQUIREMENTS_PROPERTY' IN TYPEOF(pd)))) >= 1);
END_ENTITY;




ENTITY group_relationship;

name : label;

description : text;

relating_group : group;

related_group : group;
END_ENTITY;




ENTITY group_shape_aspect
SUBTYPE OF (shape_aspect);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GROUP_PRODUCT_DEFINITION' IN TYPEOF(SELF.of_shape.definition);

wr2:
NOT (SELF\shape_aspect.description = 'interconnect module constraint region') OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GROUP_PRODUCT_DEFINITION' IN TYPEOF(SELF.of_shape.definition)) AND (SIZEOF(
QUERY (gm <* 
QUERY (pdr <* USEDIN(SELF.of_shape.definition, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION')| (pdr.name = 'group member'))| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_UNIT' IN TYPEOF(gm.related_product_definition)) AND (gm.related_product_definition.frame_of_reference.name = 'physical design')) AND (SIZEOF(
QUERY (prpc <* USEDIN(gm.related_product_definition.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'interconnect module'))) >= 1))) = 1);

wr3:
NOT (SELF\shape_aspect.description = 'interconnect module constraint region') OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GROUP_PRODUCT_DEFINITION' IN TYPEOF(SELF.of_shape.definition)) AND (SIZEOF(
QUERY (gm <* 
QUERY (pdr <* USEDIN(SELF.of_shape.definition, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION')| (pdr.name = 'group member'))| (SIZEOF(
QUERY (cp <* 
QUERY (pdr <* USEDIN(gm.related_product_definition, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION')| (pdr.name = 'composed product'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM' IN TYPEOF(cp.related_product_definition)) AND (SIZEOF(
QUERY (pdr <* USEDIN(cp.related_product_definition, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION')| (pdr.name = 'inter stratum extent'))) + SIZEOF(
QUERY (pdr <* USEDIN(cp.related_product_definition, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'inter stratum extent'))) >= 1))) >= 1))) = 1);

wr4:
NOT (SELF\shape_aspect.description = 'interconnect module constraint region') OR (SIZEOF(
QUERY (co <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'constrained object'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTERCONNECT_MODULE_DESIGN_OBJECT_CATEGORY' IN TYPEOF(co.related_shape_aspect.of_shape.definition)) AND (co.related_shape_aspect.of_shape.definition.description IN [ 'cutout category', 'file area category', 'inter stratum feature', 'stratum feature', 'via category' ]))) = 1);

wr5:
NOT (SELF\shape_aspect.description = 'interconnect module constraint region') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'design specific purpose'))) = 1))) = 1))) = 0);

wr6:
NOT (SELF\shape_aspect.description = 'interconnect module constraint region') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'keepout')) AND (it.description IN [ 'true', 'false' ]))) = 1))) = 1))) = 0);

wr7:
NOT (SELF\shape_aspect.description = 'interconnect module constraint region') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_REPRESENTATION' IN TYPEOF(pdr.used_representation)))) = 1))) = 1);

wr8:
NOT (SELF\shape_aspect.description IN [ 'interconnect module constraint region', 'termination constraint', 'placement group' ]) OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REQUIREMENTS_PROPERTY' IN TYPEOF(pd)))) = 1);

wr9:
NOT (SELF\shape_aspect.description = 'termination constraint') OR (SIZEOF(
QUERY (ctm <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'constrained termination member'))| (ctm.related_shape_aspect.description = 'mating connector termination'))) >= 2);
END_ENTITY;




ENTITY grouped_requirements_property
SUBTYPE OF (group, requirements_property);
WHERE

wr1:
NOT (SELF\group.name = 'item restricted requirements property') OR (SIZEOF(
QUERY (aga <* 
QUERY (ga <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GROUP_ASSIGNMENT.ASSIGNED_GROUP')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_GROUP_ASSIGNMENT' IN TYPEOF(ga)))| (SIZEOF(aga.items) = 1))) = 1);

wr2:
NOT (SELF\group.name = 'layout spacing requirements property') OR (SIZEOF(
QUERY (aga <* 
QUERY (ga <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GROUP_ASSIGNMENT.ASSIGNED_GROUP')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_GROUP_ASSIGNMENT' IN TYPEOF(ga)))| (SIZEOF(aga.items) = 2) AND (SIZEOF(
QUERY (rp <* 
QUERY (it <* aga.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REQUIREMENTS_PROPERTY' IN TYPEOF(it)))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESIGN_OBJECT' IN TYPEOF(rp.definition)) AND (rp.definition.name IN [ 'component feature category', 'assembly component category', 'cutout category', 'fill area category', 'inter stratum feature category', 'stratum feature category', 'via category', 'altered package category' ]))) = 1))) = 1);

wr3:
NOT (SELF\group.name = 'layout spacing requirements property') OR (SIZEOF(
QUERY (aga <* 
QUERY (ga <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GROUP_ASSIGNMENT.ASSIGNED_GROUP')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_GROUP_ASSIGNMENT' IN TYPEOF(ga)))| (SIZEOF(aga.items) = 2) AND (SIZEOF(
QUERY (rp <* 
QUERY (it <* aga.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REQUIREMENTS_PROPERTY' IN TYPEOF(it)))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESIGN_OBJECT' IN TYPEOF(rp.definition)) AND (rp.definition.description = 'dependent design object category'))) = 1))) = 1);

wr4:
NOT (SELF\group.name = 'layout spacing requirements property') OR (SIZEOF(
QUERY (aga <* 
QUERY (ga <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GROUP_ASSIGNMENT.ASSIGNED_GROUP')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_GROUP_ASSIGNMENT' IN TYPEOF(ga)))| (SIZEOF(aga.items) = 2) AND (SIZEOF(
QUERY (rp <* 
QUERY (it <* aga.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REQUIREMENTS_PROPERTY' IN TYPEOF(it)))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESIGN_OBJECT' IN TYPEOF(rp.definition)) AND (rp.definition.description = 'reference design object category'))) = 1))) = 1);
END_ENTITY;




ENTITY half_space_solid
SUBTYPE OF (geometric_representation_item);

base_surface : surface;

agreement_flag : BOOLEAN;
END_ENTITY;




ENTITY hyperbola
SUBTYPE OF (conic);

semi_axis : positive_length_measure;

semi_imag_axis : positive_length_measure;
END_ENTITY;




ENTITY integral_shield
SUBTYPE OF (component_shape_aspect);
END_ENTITY;




ENTITY inter_stratum_feature
SUBTYPE OF (component_shape_aspect);
WHERE

wr1:
SELF.description IN [ 'bonded conductive base blind via', 'buried via', 'component termination passage', 'interfacial connection', 'non conductive base blind via', 'plated conductive base blind via', 'plated cutout', 'plated cutout edge segment', 'plated interconnect module edge segment', 'plated interconnect module edge', 'unsupported passage', 'cutout', 'physical connectivity interrupting cutout', 'dielectric material passage', 'cutout edge segment', 'interconnect module edge segment', 'interconnect module edge' ];

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'feature of size')) AND (it.description IN [ 'true', 'false' ]))) = 1))) = 1))) = 0;

wr3:
SIZEOF(
QUERY (it <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated template'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_TEMPLATE_DEFINITION' IN TYPEOF(it.relating_shape_aspect)) AND (it.relating_shape_aspect.description IN [ 'inter stratum feature template', 'via template', 'component termination passage template', 'unsupported passage template' ]))) = 1;

wr4:
NOT (SELF.description = 'cutout edge segment') OR (SIZEOF(
QUERY (cc <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'composed cutout'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTER_STRATUM_FEATURE' IN TYPEOF(cc.relating_shape_aspect)) AND ((cc.relating_shape_aspect.description = 'cutout') OR (cc.relating_shape_aspect.description = 'physical connectivity interrupting cutout')))) = 1);

wr5:
NOT (SELF.description = 'interconnect module edge segment') OR (SIZEOF(
QUERY (ce <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'composed edge'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTER_STRATUM_FEATURE' IN TYPEOF(ce.relating_shape_aspect)) AND (ce.relating_shape_aspect.description = 'interconnect module edge'))) = 1);

wr6:
NOT (SELF.description = 'dielectric material passage') OR (SIZEOF(
QUERY (pp <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'precedent passage'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTER_STRATUM_FEATURE' IN TYPEOF(pp.relating_shape_aspect)) AND ((pp.relating_shape_aspect.description = 'cutout') OR (pp.relating_shape_aspect.description = 'physical connectivity interrupting cutout')))) = 1);

wr7:
(NOT (SELF.description = 'dielectric material passage') OR (SIZEOF(
QUERY (rp <* 
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REQUIREMENTS_PROPERTY' IN TYPEOF(pd)))| (rp.name = 'feature material'))) <= 1)) OR (SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MATERIAL_DESIGNATION.DEFINITIONS')) <= 1);

wr8:
NOT (SELF.description = 'physical connectivity interrupting cutout') OR (SIZEOF(
QUERY (ice <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'interrupted connectivity elements'))| (ice.relating_shape_aspect.name = 'conductive interconnect element'))) >= 1);

wr9:
NOT (SELF.description = 'unsupported passage') OR (SIZEOF(
QUERY (it <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated template'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_TEMPLATE_DEFINITION' IN TYPEOF(it.relating_shape_aspect)) AND (it.relating_shape_aspect.description = 'unsupported passage template'))) = 1);
END_ENTITY;




ENTITY interconnect_definition
SUBTYPE OF (physical_unit);
WHERE

wr1:
SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'interconnect module'))) >= 1;

wr2:
NOT (SELF.frame_of_reference.name = 'physical design') OR (SIZEOF(
QUERY (du <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.' + 'RELATING_PRODUCT_DEFINITION')| (pdr.name = 'design usage'))| ((SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTERCONNECT_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_INTERCONNECT_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_INTERCONNECT_DEFINITION') ] * TYPEOF(du)) = 1) AND (du.related_product_definition.frame_of_reference.name = 'physical design usage')) AND (SIZEOF(
QUERY (prpc <* USEDIN(du.related_product_definition.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.' + 'PRODUCTS')| (prpc\product_category.name = 'interconnect module'))) >= 1))) = 1);
END_ENTITY;




ENTITY interconnect_module_design_object_category
SUBTYPE OF (characterized_object);
WHERE

wr1:
SELF\characterized_object.description IN [ 'cutout category', 'fill area category', 'inter stratum feature category', 'stratum feature category', 'via category' ];
END_ENTITY;




ENTITY interconnect_module_stratum_based_terminal
SUBTYPE OF (interconnect_module_terminal);
END_ENTITY;




ENTITY interconnect_module_terminal
SUBTYPE OF (shape_aspect);
WHERE

wr1:
(('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_UNIT' IN TYPEOF(SELF.of_shape.definition)) AND (SELF.of_shape.definition\product_definition.frame_of_reference.name = 'physical design usage')) AND (SIZEOF(
QUERY (prpc <* USEDIN(SELF.of_shape.definition.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'interconnect module'))) >= 1);

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_REPRESENTATION' IN TYPEOF(pdr.used_representation)))) >= 1))) >= 1;

wr3:
SIZEOF(
QUERY (mct <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'member connected terminal'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_CONNECTED_TERMINALS_DEFINITION' IN TYPEOF(mct.relating_shape_aspect)))) <= 1;

wr5:
SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.related_shape_aspect.description = 'connection zone'))) = 1;
END_ENTITY;




ENTITY interface_component_definition
SUBTYPE OF (component_definition);
WHERE

wr1:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_INTERFACE_TERMINAL' IN TYPEOF(sa)) AND (sa.description IN [ 'interconnect component interface terminal', 'packaged connector component interface terminal' ]))) >= 1))) >= 1;
END_ENTITY;




ENTITY interface_mounted_join
SUBTYPE OF (shape_aspect_relationship, shape_aspect);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_INTERFACE_TERMINAL' IN TYPEOF(SELF.related_shape_aspect);

wr2:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL' IN TYPEOF(SELF.relating_shape_aspect);
END_ENTITY;




ENTITY interfaced_group_component_definition
SUBTYPE OF (assembly_group_component_definition);
WHERE

wr1:
SIZEOF(
QUERY (gc <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION')| (pdr.name = 'group component'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTERFACE_COMPONENT_DEFINITION' IN TYPEOF(gc.related_product_definition)))) >= 1;
END_ENTITY;




ENTITY intersection_curve
SUBTYPE OF (surface_curve);
WHERE

wr1:
SIZEOF(SELF\surface_curve.associated_geometry) = 2;

wr2:
associated_surface(SELF\surface_curve.associated_geometry[1]) <> associated_surface(SELF\surface_curve.associated_geometry[2]);
END_ENTITY;




ENTITY item_defined_transformation;

name : label;

description : text;

transform_item_1 : representation_item;

transform_item_2 : representation_item;
END_ENTITY;




ENTITY join_shape_aspect
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SIZEOF(
QUERY (cp <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'connected point'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAYER_CONNECTION_POINT' IN TYPEOF(cp.related_shape_aspect)))) >= 2;

wr2:
SIZEOF(
QUERY (nt <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'network topology'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_NETWORK' IN TYPEOF(nt.relating_shape_aspect)))) = 1;

wr3:
NOT (SELF.name = 'intra stratum join') OR (SIZEOF(
QUERY (ji <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'join implementation'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_FEATURE' IN TYPEOF(ji.related_shape_aspect)) AND (ji.related_shape_aspect.description = 'conductor'))) <= 1);

wr4:
NOT (SELF.name = 'intra stratum join') OR (SIZEOF(
QUERY (ji <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'join implementation'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_FEATURE' IN TYPEOF(ji.related_shape_aspect)) AND (ji.related_shape_aspect.description = 'connected filled area'))) <= 1);

wr5:
NOT (SELF.name = 'inter stratum join') OR (SIZEOF(
QUERY (ji <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'join implementation'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_CONCEPT_RELATIONSHIP' IN TYPEOF(ji.related_shape_aspect)) AND (ji.related_shape_aspect\shape_aspect.description = 'physical network supporting stratum feature conductive join') OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PLATED_INTER_STRATUM_FEATURE' IN TYPEOF(ji.related_shape_aspect)))) <= 1);
END_ENTITY;




ENTITY land
SUBTYPE OF (component_shape_aspect);
WHERE

wr1:
('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_DEFINITION' IN TYPEOF(SELF.of_shape.definition)) AND (SIZEOF(
QUERY (prpc <* USEDIN(SELF.of_shape.definition.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'interconnect module'))) >= 1);

wr2:
SIZEOF(
QUERY (i_f <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated template'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND_PHYSICAL_TEMPLATE' IN TYPEOF(i_f.relating_shape_aspect)))) = 1;

wr3:
SIZEOF(
QUERY (aud <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'alternate usage definition'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND_PHYSICAL_TEMPLATE' IN TYPEOF(aud.relating_shape_aspect)))) <= 1;

wr4:
SIZEOF(
QUERY (sfi <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'stratum feature implementation'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_FEATURE' IN TYPEOF(sfi.relating_shape_aspect)))) = 1;

wr5:
NOT (SELF\shape_aspect.description IN [ 'functional land', 'via dependent land', 'via and contact size dependent land', 'component termination passage dependent land', 'contact size dependent land', 'component termination passage and contact size dependent land' ]) OR (SIZEOF(
QUERY (ac <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'associated component'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_SHAPE_ASPECT' IN TYPEOF(ac.related_shape_aspect)) AND (ac.related_shape_aspect.description = 'land interface terminal'))) = 1);

wr6:
NOT (SELF\shape_aspect.description IN [ 'functional land', 'via dependent land', 'via and contact size dependent land', 'component termination passage dependent land', 'contact size dependent land', 'component termination passage and contact size dependent land' ]) OR (SIZEOF(
QUERY (ac <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'associated component'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL' IN TYPEOF(ac.related_shape_aspect)) AND (ac.related_shape_aspect.description = 'land join terminal'))) >= 1);

wr7:
NOT (SELF\shape_aspect.description IN [ 'non functional land', 'via dependent non functional land', 'via and contact size dependent non functional land', 'component termination passage dependent non functional land', 'contact size dependent non functional land', 'component termination passage and contact size ' + 'dependent non functional land', 'unsupported passage dependent non functional land' ]) OR (SIZEOF(
QUERY (ac <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'associated component'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_SHAPE_ASPECT' IN TYPEOF(ac.related_shape_aspect)) AND (ac.related_shape_aspect.description = 'non functional land interface terminal'))) = 1);

wr8:
NOT (SELF\shape_aspect.description IN [ 'non functional land', 'via dependent non functional land', 'via and contact size dependent non functional land', 'component termination passage dependent non functional land', 'contact size dependent non functional land', 'component termination passage and contact size ' + 'dependent non functional land', 'unsupported passage dependent non functional land' ]) OR (SIZEOF(
QUERY (ac <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'associated component'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL' IN TYPEOF(ac.related_shape_aspect)) AND (ac.related_shape_aspect.description = 'non functional land join terminal'))) >= 1);

wr9:
NOT (SELF\shape_aspect.description IN [ 'component termination passage and contact size dependent land', 'component termination passage and contact size dependent' + 'non functional land', 'component termination passage dependent land', 'component termination passage dependent non functional land' ]) OR (SIZEOF(
QUERY (rp <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'reference passage'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PLATED_PASSAGE' IN TYPEOF(rp.relating_shape_aspect)) AND (rp.related_shape_aspect.description = 'component termination passage'))) = 1);

wr10:
NOT (SELF\shape_aspect.description IN [ 'via and contact size dependent land', 'via and contact size dependent non functional land', 'via dependent land', 'via dependent non functional land' ]) OR (SIZEOF(
QUERY (rv <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'reference via'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PLATED_PASSAGE' IN TYPEOF(rv.relating_shape_aspect)) AND (rv.related_shape_aspect.description IN [ 'buried via', 'interfacial connection', 'bonded conductive base blind via', 'non conductive base blind via', 'plated conductive base blind via' ]))) = 1);

wr11:
NOT (SELF\shape_aspect.description = 'unsupported passage dependent non functional land') OR (SIZEOF(
QUERY (rp <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'reference passage'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTER_STRATUM_FEATURE' IN TYPEOF(rp.relating_shape_aspect)) AND (rp.relating_shape_aspect.description = 'unsupported passage'))) = 1);

wr12:
NOT (SELF\shape_aspect.description IN [ 'component termination passage dependent land', 'component termination passage dependent non functional land' ]) OR (SIZEOF(
QUERY (it <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated template'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND_PHYSICAL_TEMPLATE' IN TYPEOF(it.relating_shape_aspect)) AND (it.related_shape_aspect.description = 'default component termination passage based'))) = 1);

wr13:
NOT (SELF\shape_aspect.description IN [ 'component termination passage and contact size dependent land', 'component termination passage and contact size dependent ' + 'non functional land' ]) OR (SIZEOF(
QUERY (it <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated template'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND_PHYSICAL_TEMPLATE' IN TYPEOF(it.relating_shape_aspect)) AND (it.related_shape_aspect.description = 'default attachment size and component termination ' + 'passage based'))) = 1);

wr14:
NOT (SELF\shape_aspect.description IN [ 'contact size dependent land', 'contact size dependent non functional land' ]) OR (SIZEOF(
QUERY (it <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated template'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND_PHYSICAL_TEMPLATE' IN TYPEOF(it.relating_shape_aspect)) AND (it.related_shape_aspect.description = 'default attachment size based'))) = 1);

wr15:
NOT (SELF\shape_aspect.description IN [ 'via and contact size dependent land', 'via and contact size dependent non functional land' ]) OR (SIZEOF(
QUERY (it <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated template'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND_PHYSICAL_TEMPLATE' IN TYPEOF(it.relating_shape_aspect)) AND (it.related_shape_aspect.description = 'default attachment size and via based'))) = 1);

wr16:
NOT (SELF\shape_aspect.description IN [ 'via dependent land', 'via dependent non functional land' ]) OR (SIZEOF(
QUERY (it <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated template'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND_PHYSICAL_TEMPLATE' IN TYPEOF(it.relating_shape_aspect)) AND (it.related_shape_aspect.description = 'default via based'))) = 1);

wr17:
NOT (SELF\shape_aspect.description = 'unsupported passage dependent ' + 'non functional land') OR (SIZEOF(
QUERY (it <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated template'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND_PHYSICAL_TEMPLATE' IN TYPEOF(it.relating_shape_aspect)) AND (it.relating_shape_aspect.description = 'default unsupported passage based'))) = 1);
END_ENTITY;




ENTITY land_physical_template
SUBTYPE OF (part_template_definition);
WHERE

wr1:
SIZEOF(
QUERY (ada <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DOCUMENT_REFERENCE.ITEMS')| (SIZEOF(
QUERY (duc <* USEDIN(ada.assigned_document, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DOCUMENT_USAGE_CONSTRAINT.SOURCE')| (duc.subject_element = 'pre defined classification code'))) = 1))) <= 1;

wr2:
SIZEOF(
QUERY (am <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'access mechanism'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND_TEMPLATE_TERMINAL' IN TYPEOF(am.related_shape_aspect)))) >= 2;

wr3:
NOT (SELF.description IN [ 'default attachment size based', 'default attachment size and component termination passage based', 'default attachment size and via based' ]) OR (SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'minimum attachment region size') AND (sar.related_shape_aspect.description = 'connection zone'))) = 1);

wr4:
NOT (SELF.description IN [ 'default attachment size based', 'default attachment size and component termination passage based', 'default attachment size and via based' ]) OR (SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'maximum attachment region size') AND (sar.related_shape_aspect.description = 'connection zone'))) = 1);

wr5:
NOT (SELF.description IN [ 'default component termination passage based', 'default attachment size and component termination passage based' ]) OR (SIZEOF(
QUERY (tu <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'technology usage'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PASSAGE_TECHNOLOGY' IN TYPEOF(tu.related_shape_aspect)) AND (tu.related_shape_aspect.description = 'default component termination passage definition'))) = 1);

wr6:
NOT (SELF.description IN [ 'default attachment size and component termination passage based', 'default attachment size based', 'default attachment size and via based', 'default component termination passage based', 'default via based', 'default unsupported passage based' ]) OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (tu <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')| (pdr.name = 'technology usage'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_TECHNOLOGY' IN TYPEOF(tu.relating_property_definition.definition)))) = 1))) = 1);

wr7:
NOT (SELF.description IN [ 'default attachment size and component termination passage based', 'default attachment size and via based', 'default component termination passage based', 'default via based', 'default unsupported passage based' ]) OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2))) = 2))) = 1))) = 0);

wr8:
NOT (SELF.description IN [ 'default attachment size and component termination passage based', 'default attachment size and via based', 'default component termination passage based', 'default via based', 'default unsupported passage based' ]) OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'minimum standard fabrication allowance'))) = 1))) = 1))) = 0);

wr9:
NOT (SELF.description IN [ 'default attachment size and component termination passage based', 'default attachment size and via based', 'default component termination passage based', 'default via based', 'default unsupported passage based' ]) OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'minimum annular ring'))) = 1))) = 1))) = 0);

wr10:
NOT (SELF.description IN [ 'default attachment size and component termination passage based', 'default attachment size and via based', 'default component termination passage based', 'default via based', 'default unsupported passage based' ]) OR (SIZEOF(
QUERY (tu <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'technology usage'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PASSAGE_TECHNOLOGY' IN TYPEOF(tu.related_shape_aspect)))) = 1);

wr11:
NOT (SELF.description IN [ 'default via based', 'default attachment size and via based' ]) OR (SIZEOF(
QUERY (tu <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'technology usage'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PASSAGE_TECHNOLOGY' IN TYPEOF(tu.related_shape_aspect)) AND (tu.related_shape_aspect.description = 'default via definition'))) = 1);

wr12:
NOT (SELF.description = 'default unsupported passage') OR (SIZEOF(
QUERY (tu <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'technology usage'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PASSAGE_TECHNOLOGY' IN TYPEOF(tu.related_shape_aspect)) AND (tu.related_shape_aspect.description = 'default unsupported passage definition'))) = 1);
END_ENTITY;




ENTITY land_template_terminal
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SELF.description IN [ 'interface terminal', 'join terminal' ];

wr2:
SIZEOF(
QUERY (tcz <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'terminal connection zone') AND (sar.description IN [ 'edge curve', 'edge point', 'surface area', 'surface point' ]))| (tcz.related_shape_aspect.description = 'connection zone'))) >= 1;

wr3:
SIZEOF(
QUERY (tcz <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'terminal connection zone'))| NOT (SIZEOF(
QUERY (tcz_1 <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'terminal connection zone')) - tcz| NOT (tcz.description = tcz_1.description))) = 0))) = 0;
END_ENTITY;




ENTITY layer
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SIZEOF(
QUERY (ada <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DOCUMENT_REFERENCE.ITEMS')| (SIZEOF(
QUERY (duc <* USEDIN(ada.assigned_document, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DOCUMENT_USAGE_CONSTRAINT.SOURCE')| (duc.subject_element = 'layer definition'))) = 1))) <= 1;

wr2:
('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP' IN TYPEOF(SELF.of_shape.definition)) AND (SELF.of_shape.definition.name = 'inter stratum extent');
END_ENTITY;




ENTITY layer_connection_point
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SIZEOF(
QUERY (prpc <* USEDIN(SELF.of_shape.definition.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'design layer'))) >= 1;

wr2:
SIZEOF(
QUERY (cp <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'connected point'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'JOIN_SHAPE_ASPECT' IN TYPEOF(cp.relating_shape_aspect)))) >= 1;

wr3:
NOT (SELF\shape_aspect.description = 'dependently located') OR (SIZEOF(
QUERY (ado <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'associated design object'))| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTER_STRATUM_FEATURE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTERCONNECT_MODULE_TERMINAL') ] * TYPEOF(ado.relating_shape_aspect)) = 1))) = 1);

wr4:
NOT (SELF\shape_aspect.description = 'explicitly located') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_REPRESENTATION' IN TYPEOF(pdr.used_representation)) AND (pdr.used_representation.name = 'connection point location')) AND (SIZEOF(
QUERY (it <* pdr.used_representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CARTESIAN_POINT' IN TYPEOF(it)))) = 1))) = 1))) = 0);
END_ENTITY;




ENTITY length_measure_with_unit
SUBTYPE OF (measure_with_unit);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.LENGTH_UNIT' IN TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY;




ENTITY length_unit
SUBTYPE OF (named_unit);
WHERE

wr1:
((((((SELF\named_unit.dimensions.length_exponent = 1) AND (SELF\named_unit.dimensions.mass_exponent = 0)) AND (SELF\named_unit.dimensions.time_exponent = 0)) AND (SELF\named_unit.dimensions.electric_current_exponent = 0)) AND (SELF\named_unit.dimensions.thermodynamic_temperature_exponent = 0)) AND (SELF\named_unit.dimensions.amount_of_substance_exponent = 0)) AND (SELF\named_unit.dimensions.luminous_intensity_exponent = 0);
END_ENTITY;




ENTITY library_defined_assembly_definition
SUBTYPE OF (library_defined_physical_unit);
WHERE

wr1:
SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'assembly module'))) >= 1;

wr2:
NOT (SELF.frame_of_reference.name = 'physical design usage') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_MODULE_TERMINAL' IN TYPEOF(sa)) AND (sa.description = 'pca terminal'))) >= 2))) = 0);
END_ENTITY;




ENTITY library_defined_bare_die
SUBTYPE OF (library_defined_physical_unit);
WHERE

wr1:
SIZEOF(
QUERY (ifdu <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.' + 'RELATED_PRODUCT_DEFINITION')| (pdr.name = 'implemented function'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FUNCTIONAL_UNIT' IN TYPEOF(ifdu.relating_product_definition)) AND (ifdu.relating_product_definition.frame_of_reference.name = 'functional design usage'))) = 1;

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (dut <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')| (pdr.name = 'device unit technology'))| (dut.relating_property_definition.name = 'unit technology'))) = 1))) = 1;

wr3:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'BARE_DIE_TERMINAL' IN TYPEOF(sa)))) >= 2))) = 0;
END_ENTITY;




ENTITY library_defined_functional_unit
SUBTYPE OF (externally_defined_functional_unit);
WHERE

wr1:
SIZEOF(
QUERY (esr <* USEDIN(SELF.source, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNAL_SOURCE_RELATIONSHIP.RELATING_SOURCE')| (esr.name = 'revision'))) = 0;
END_ENTITY;




ENTITY library_defined_interconnect_definition
SUBTYPE OF (library_defined_physical_unit);
WHERE

wr1:
SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'interconnect module'))) >= 1;
END_ENTITY;




ENTITY library_defined_model
SUBTYPE OF (externally_defined_item, analytical_model, product_definition);
WHERE

wr1:
SIZEOF(
QUERY (esr <* USEDIN(SELF.source, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNAL_SOURCE_RELATIONSHIP.RELATING_SOURCE')| (esr.name = 'revision'))) = 1;
END_ENTITY;




ENTITY library_defined_package
SUBTYPE OF (library_defined_physical_unit);
WHERE

wr1:
SELF.frame_of_reference.name = 'physical design usage';

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'registered case style'))) >= 1))) = 0;

wr3:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sr_pdr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_REPRESENTATION' IN TYPEOF(pdr)))| (sr_pdr.used_representation.name = 'seating plane'))) = 1))) = 0;

wr4:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE_BODY' IN TYPEOF(sa)))) <= 1))) = 0;

wr5:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE_TERMINAL' IN TYPEOF(sa)))) >= 1))) = 0;

wr6:
NOT (SELF.description = 'as installed package') OR (SIZEOF(
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'package preparation') AND (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_PACKAGE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_PACKAGE') ] * TYPEOF(pdr.relating_product_definition)) = 1))) = 1);
END_ENTITY;




ENTITY library_defined_packaged_connector
SUBTYPE OF (library_defined_packaged_part);
END_ENTITY;




ENTITY library_defined_packaged_part
SUBTYPE OF (library_defined_physical_unit);
WHERE

wr1:
NOT (SELF.frame_of_reference.name = 'physical design usage') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART_TERMINAL' IN TYPEOF(sa)))) >= 2))) = 0);

wr2:
NOT (SELF.frame_of_reference.name = 'physical design usage') OR (SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MATERIAL_DESIGNATION.DEFINITIONS')) = 1);

wr3:
NOT (SELF.frame_of_reference.name = 'physical design usage') OR (SIZEOF(
QUERY (ifu <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'implemented function'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FUNCTIONAL_UNIT' IN TYPEOF(ifu.relating_product_definition)) AND (ifu.relating_product_definition.frame_of_reference.name = 'functional design usage'))) = 1);

wr4:
NOT (SELF.frame_of_reference.name = 'physical design usage') OR (SIZEOF(
QUERY (upkg <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION')| (pdr.name = 'used package'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE' IN TYPEOF(upkg.related_product_definition)))) = 1);

wr5:
NOT (SELF.description = 'as installed packaged part') OR (SIZEOF(
QUERY (bpp <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'base packaged part'))| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_PACKAGED_PART') ] * TYPEOF(bpp.relating_product_definition)) = 1) AND (bpp.relating_product_definition.frame_of_reference.name = 'physical design usage'))) >= 1);

wr6:
NOT (SELF.description = 'as installed packaged part') OR (SIZEOF(
QUERY (upkg <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'used package'))| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_PACKAGED_PART') ] * TYPEOF(upkg.relating_product_definition)) = 1))) >= 1);
END_ENTITY;




ENTITY library_defined_physical_unit
SUPERTYPE OF (ONEOF(library_defined_package, library_defined_assembly_definition, library_defined_interconnect_definition, library_defined_packaged_part, library_defined_bare_die))
SUBTYPE OF (externally_defined_physical_unit);
WHERE

wr1:
SIZEOF(
QUERY (esr <* USEDIN(SELF.source, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNAL_SOURCE_RELATIONSHIP.RELATING_SOURCE')| (esr.name = 'revision'))) = 0;
END_ENTITY;




ENTITY line
SUBTYPE OF (curve);

pnt : cartesian_point;

dir : vector;
WHERE

wr1:
dir.dim = pnt.dim;
END_ENTITY;




ENTITY linear_profile_tolerance
SUBTYPE OF (physical_unit_geometric_tolerance);
END_ENTITY;




ENTITY local_time;

hour_component : hour_in_day;

minute_component : OPTIONAL minute_in_hour;

second_component : OPTIONAL second_in_minute;

zone : coordinated_universal_time_offset;
WHERE

wr1:
valid_time(SELF);
END_ENTITY;




ENTITY loop
SUPERTYPE OF (ONEOF(vertex_loop, edge_loop, poly_loop))
SUBTYPE OF (topological_representation_item);
END_ENTITY;




ENTITY lot_effectivity
SUBTYPE OF (effectivity);

effectivity_lot_id : identifier;

effectivity_lot_size : measure_with_unit;
END_ENTITY;




ENTITY luminous_intensity_measure_with_unit
SUBTYPE OF (measure_with_unit);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.LUMINOUS_INTENSITY_UNIT' IN TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY;




ENTITY luminous_intensity_unit
SUBTYPE OF (named_unit);
WHERE

wr1:
((((((SELF\named_unit.dimensions.length_exponent = 0) AND (SELF\named_unit.dimensions.mass_exponent = 0)) AND (SELF\named_unit.dimensions.time_exponent = 0)) AND (SELF\named_unit.dimensions.electric_current_exponent = 0)) AND (SELF\named_unit.dimensions.thermodynamic_temperature_exponent = 0)) AND (SELF\named_unit.dimensions.amount_of_substance_exponent = 0)) AND (SELF\named_unit.dimensions.luminous_intensity_exponent = 1);
END_ENTITY;




ENTITY make_from_connectivity_relationship
SUBTYPE OF (shape_aspect_relationship);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_CONNECTIVITY_DEFINITION' IN TYPEOF(SELF.relating_shape_aspect);

wr2:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_CONNECTIVITY_DEFINITION' IN TYPEOF(SELF.related_shape_aspect);
END_ENTITY;




ENTITY make_from_feature_relationship
SUBTYPE OF (shape_aspect_relationship);
WHERE

wr1:
SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_INTERFACE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_SHAPE_ASPECT') ] * TYPEOF(SELF.relating_shape_aspect)) = 1;

wr2:
SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_INTERFACE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_SHAPE_ASPECT') ] * TYPEOF(SELF.related_shape_aspect)) = 1;

wr3:
NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_SHAPE_ASPECT' IN TYPEOF(SELF.relating_shape_aspect)) OR (SELF.relating_shape_aspect.description IN [ 'component feature', 'component termination passage interface terminal', 'land or non functional land interface terminal', 'printed connector component interface terminal' ]);

wr4:
NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_SHAPE_ASPECT' IN TYPEOF(SELF.related_shape_aspect)) OR (SELF.related_shape_aspect.description IN [ 'component feature', 'component termination passage interface terminal', 'land or non functional land interface terminal', 'printed connector component interface terminal' ]);
END_ENTITY;




ENTITY make_from_usage_option
SUBTYPE OF (product_definition_usage);

ranking : INTEGER;

ranking_rationale : text;

quantity : measure_with_unit;
WHERE

wr1:
ranking > 0;
END_ENTITY;




ENTITY manifold_solid_brep
SUBTYPE OF (solid_model);

outer : closed_shell;
END_ENTITY;




ENTITY manifold_surface_shape_representation
SUBTYPE OF (shape_representation);
WHERE

wr1:
SIZEOF(
QUERY (it <* SELF.items| NOT (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_SURFACE_MODEL', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AXIS2_PLACEMENT_3D' ] * TYPEOF(it)) = 1))) = 0;

wr2:
SIZEOF(
QUERY (it <* SELF.items| (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_SURFACE_MODEL', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' ] * TYPEOF(it)) = 1))) > 0;

wr3:
SIZEOF(
QUERY (mi <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' IN TYPEOF(it)))| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MANIFOLD_SURFACE_SHAPE_REPRESENTATION' IN TYPEOF(mi\mapped_item.mapping_source.mapped_representation)))) = 0;

wr4:
SIZEOF(
QUERY (sbsm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_SURFACE_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (sh <* sbsm\shell_based_surface_model.sbsm_boundary| NOT (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.OPEN_SHELL', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ORIENTED_CLOSED_SHELL', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CLOSED_SHELL' ] * TYPEOF(sh)) = 1))) = 0))) = 0;

wr5:
SIZEOF(
QUERY (sbsm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_SURFACE_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (cfs <* sbsm\shell_based_surface_model.sbsm_boundary| NOT (SIZEOF(
QUERY (fa <* cfs\connected_face_set.cfs_faces| NOT (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.FACE_SURFACE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ORIENTED_FACE' ] * TYPEOF(fa)) = 1))) = 0))) = 0))) = 0;

wr6:
SIZEOF(
QUERY (sbsm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_SURFACE_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (cfs <* sbsm\shell_based_surface_model.sbsm_boundary| NOT (SIZEOF(
QUERY (f_sf <* 
QUERY (fa <* cfs\connected_face_set.cfs_faces| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.FACE_SURFACE' IN TYPEOF(fa)))| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ADVANCED_FACE' IN TYPEOF(f_sf)) OR (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.B_SPLINE_SURFACE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ELEMENTARY_SURFACE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.OFFSET_SURFACE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SURFACE_REPLICA', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SWEPT_SURFACE' ] * TYPEOF(f_sf\face_surface.face_geometry)) = 1)))) = 0))) = 0))) = 0;

wr7:
SIZEOF(
QUERY (sbsm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_SURFACE_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (cfs <* sbsm\shell_based_surface_model.sbsm_boundary| NOT (SIZEOF(
QUERY (fa <* cfs\connected_face_set.cfs_faces| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ADVANCED_FACE' IN TYPEOF(fa)) OR msf_surface_check(fa\face_surface.face_geometry)))) = 0))) = 0))) = 0;

wr8:
SIZEOF(
QUERY (sbsm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_SURFACE_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (cfs <* sbsm\shell_based_surface_model.sbsm_boundary| NOT (SIZEOF(
QUERY (fa <* cfs\connected_face_set.cfs_faces| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ADVANCED_FACE' IN TYPEOF(fa)) OR (SIZEOF(
QUERY (bnds <* fa.bounds| NOT (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_LOOP', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_LOOP' ] * TYPEOF(bnds.bound)) = 1))) = 0)))) = 0))) = 0))) = 0;

wr9:
SIZEOF(
QUERY (sbsm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_SURFACE_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (cfs <* sbsm\shell_based_surface_model.sbsm_boundary| NOT (SIZEOF(
QUERY (fa <* cfs\connected_face_set.cfs_faces| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ADVANCED_FACE' IN TYPEOF(fa)) OR (SIZEOF(
QUERY (elp_fbnds <* 
QUERY (bnds <* fa.bounds| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_LOOP' IN TYPEOF(bnds.bound)))| NOT (SIZEOF(
QUERY (oe <* elp_fbnds\path.edge_list| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_CURVE' IN TYPEOF(oe.edge_element)))) = 0))) = 0)))) = 0))) = 0))) = 0;

wr10:
SIZEOF(
QUERY (sbsm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_SURFACE_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (cfs <* sbsm\shell_based_surface_model.sbsm_boundary| NOT (SIZEOF(
QUERY (fa <* cfs\connected_face_set.cfs_faces| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ADVANCED_FACE' IN TYPEOF(fa)) OR (SIZEOF(
QUERY (elp_fbnds <* 
QUERY (bnds <* fa.bounds| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_LOOP' IN TYPEOF(bnds.bound)))| NOT (SIZEOF(
QUERY (oe_cv <* 
QUERY (oe <* elp_fbnds\path.edge_list| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_CURVE' IN TYPEOF(oe.edge_element)))| NOT (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.B_SPLINE_CURVE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CONIC', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CURVE_REPLICA', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.LINE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.OFFSET_CURVE_3D', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PCURVE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POLYLINE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SURFACE_CURVE' ] * TYPEOF(oe_cv.edge_element\edge_curve.edge_geometry)) = 1))) = 0))) = 0)))) = 0))) = 0))) = 0;

wr11:
SIZEOF(
QUERY (sbsm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_SURFACE_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (cfs <* sbsm\shell_based_surface_model.sbsm_boundary| NOT (SIZEOF(
QUERY (fa <* cfs\connected_face_set.cfs_faces| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ADVANCED_FACE' IN TYPEOF(fa)) OR (SIZEOF(
QUERY (elp_fbnds <* 
QUERY (bnds <* fa.bounds| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_LOOP' IN TYPEOF(bnds.bound)))| NOT (SIZEOF(
QUERY (oe <* elp_fbnds\path.edge_list| NOT msf_curve_check(oe.edge_element\edge_curve.edge_geometry))) = 0))) = 0)))) = 0))) = 0))) = 0;

wr12:
SIZEOF(
QUERY (sbsm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_SURFACE_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (cfs <* sbsm\shell_based_surface_model.sbsm_boundary| NOT (SIZEOF(
QUERY (fa <* cfs\connected_face_set.cfs_faces| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ADVANCED_FACE' IN TYPEOF(fa)) OR (SIZEOF(
QUERY (elp_fbnds <* 
QUERY (bnds <* fa.bounds| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_LOOP' IN TYPEOF(bnds.bound)))| NOT (SIZEOF(
QUERY (oe <* elp_fbnds\path.edge_list| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_POINT' IN TYPEOF(oe.edge_element.edge_start)) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_POINT' IN TYPEOF(oe.edge_element.edge_end))))) = 0))) = 0)))) = 0))) = 0))) = 0;

wr13:
SIZEOF(
QUERY (sbsm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_SURFACE_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (cfs <* sbsm\shell_based_surface_model.sbsm_boundary| NOT (SIZEOF(
QUERY (fa <* cfs\connected_face_set.cfs_faces| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ADVANCED_FACE' IN TYPEOF(fa)) OR (SIZEOF(
QUERY (elp_fbnds <* 
QUERY (bnds <* fa.bounds| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_LOOP' IN TYPEOF(bnds.bound)))| NOT (SIZEOF(
QUERY (oe <* elp_fbnds\path.edge_list| NOT ((SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CARTESIAN_POINT', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.DEGENERATE_PCURVE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POINT_ON_CURVE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POINT_ON_SURFACE' ] * TYPEOF(oe.edge_element.edge_start\vertex_point.vertex_geometry)) = 1) AND (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CARTESIAN_POINT', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.DEGENERATE_PCURVE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POINT_ON_CURVE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POINT_ON_SURFACE' ] * TYPEOF(oe.edge_element.edge_end\vertex_point.vertex_geometry)) = 1)))) = 0))) = 0)))) = 0))) = 0))) = 0;

wr14:
SIZEOF(
QUERY (sbsm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_SURFACE_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (cfs <* sbsm\shell_based_surface_model.sbsm_boundary| NOT (SIZEOF(
QUERY (fa <* cfs\connected_face_set.cfs_faces| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ADVANCED_FACE' IN TYPEOF(fa)) OR (SIZEOF(
QUERY (vlp_fbnds <* 
QUERY (bnds <* fa.bounds| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_LOOP' IN TYPEOF(bnds.bound)))| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_POINT' IN TYPEOF(vlp_fbnds\vertex_loop.loop_vertex)))) = 0)))) = 0))) = 0))) = 0;

wr15:
SIZEOF(
QUERY (sbsm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_SURFACE_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (cfs <* sbsm\shell_based_surface_model.sbsm_boundary| NOT (SIZEOF(
QUERY (fa <* cfs\connected_face_set.cfs_faces| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ADVANCED_FACE' IN TYPEOF(fa)) OR (SIZEOF(
QUERY (vlp_fbnds <* 
QUERY (bnds <* fa.bounds| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_LOOP' IN TYPEOF(bnds.bound)))| NOT (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CARTESIAN_POINT', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.DEGENERATE_PCURVE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POINT_ON_CURVE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POINT_ON_SURFACE' ] * TYPEOF(vlp_fbnds\vertex_loop.loop_vertex\vertex_point.vertex_geometry)) = 1))) = 0)))) = 0))) = 0))) = 0;
END_ENTITY;




ENTITY mapped_item
SUBTYPE OF (representation_item);

mapping_source : representation_map;

mapping_target : representation_item;
WHERE

wr1:
acyclic_mapped_representation(using_representations(SELF), [ SELF ]);
END_ENTITY;




ENTITY mass_measure_with_unit
SUBTYPE OF (measure_with_unit);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MASS_UNIT' IN TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY;




ENTITY mass_unit
SUBTYPE OF (named_unit);
WHERE

wr1:
((((((SELF\named_unit.dimensions.length_exponent = 0) AND (SELF\named_unit.dimensions.mass_exponent = 1)) AND (SELF\named_unit.dimensions.time_exponent = 0)) AND (SELF\named_unit.dimensions.electric_current_exponent = 0)) AND (SELF\named_unit.dimensions.thermodynamic_temperature_exponent = 0)) AND (SELF\named_unit.dimensions.amount_of_substance_exponent = 0)) AND (SELF\named_unit.dimensions.luminous_intensity_exponent = 0);
END_ENTITY;




ENTITY material_designation;

name : label;

definitions : SET [1:?] OF characterized_definition;
END_ENTITY;




ENTITY material_designation_characterization;

name : label;

description : text;

designation : material_designation;

property : characterized_material_property;
END_ENTITY;




ENTITY material_electrical_conductivity_category
SUBTYPE OF (group);
WHERE

wr1:
SELF.name IN [ 'conductive', 'non conductive', 'resistive', 'semi conductive' ];
END_ENTITY;




ENTITY material_property
SUBTYPE OF (property_definition);
UNIQUE

ur1 : name, definition;
WHERE

wr1:
('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CHARACTERIZED_OBJECT' IN TYPEOF(SELF\property_definition.definition)) OR (SIZEOF(bag_to_set(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')) - 
QUERY (temp <* bag_to_set(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MATERIAL_PROPERTY_REPRESENTATION' IN TYPEOF(temp)))) = 0);
END_ENTITY;




ENTITY material_property_representation
SUBTYPE OF (property_definition_representation);

dependent_environment : data_environment;
END_ENTITY;




ENTITY measure_qualification;

name : label;

description : text;

qualified_measure : measure_with_unit;

qualifiers : SET [1:?] OF value_qualifier;
WHERE

wr1:
SIZEOF(
QUERY (temp <* qualifiers| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PRECISION_QUALIFIER' IN TYPEOF(temp)))) < 2;
END_ENTITY;




ENTITY measure_representation_item
SUBTYPE OF (representation_item, measure_with_unit);
END_ENTITY;




ENTITY measure_with_unit
SUPERTYPE OF (ONEOF(length_measure_with_unit, mass_measure_with_unit, time_measure_with_unit, electric_current_measure_with_unit, thermodynamic_temperature_measure_with_unit, amount_of_substance_measure_with_unit, luminous_intensity_measure_with_unit, plane_angle_measure_with_unit, solid_angle_measure_with_unit, area_measure_with_unit, volume_measure_with_unit, ratio_measure_with_unit));

value_component : measure_value;

unit_component : unit;
WHERE

wr1:
valid_units(SELF);
END_ENTITY;




ENTITY minimally_defined_bare_die_terminal
SUPERTYPE OF (bare_die_terminal)
SUBTYPE OF (shape_aspect);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'BARE_DIE' IN TYPEOF(SELF.of_shape.definition);

wr2:
SIZEOF(
QUERY (eca <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'external connection area'))| (eca.related_shape_aspect.description = 'connection zone'))) <= 1;

wr3:
SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MATERIAL_DESIGNATION.DEFINITIONS')) <= 1;

wr4:
SIZEOF(
QUERY (mct <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'member connected terminal'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_CONNECTED_TERMINALS_DEFINITION' IN TYPEOF(mct.relating_shape_aspect)))) <= 1;
END_ENTITY;




ENTITY model_parameter
SUBTYPE OF (representation_item);
WHERE

wr1:
SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DOCUMENT_REFERENCE.ITEMS')) = 1;

wr2:
SIZEOF(
QUERY (cri <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REPRESENTATION.ITEMS')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COORDINATED_REPRESENTATION_ITEM' IN TYPEOF(cri)) AND (cri\representation.name = 'model parameter with valid range value'))) <= 1;

wr3:
SIZEOF(
QUERY (aga <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_GROUP_ASSIGNMENT.ITEMS')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PARAMETER_TYPE' IN TYPEOF(aga.assigned_group)) AND (aga.assigned_group.name IN [ 'string property type', 'logical property type', 'physical property type', 'boolean property type' ]))) = 1;
END_ENTITY;




ENTITY modified_geometric_tolerance
SUBTYPE OF (geometric_tolerance);

modifier : limit_condition;
END_ENTITY;




ENTITY mounting_restriction_area
SUBTYPE OF (shape_aspect);
WHERE

wr1:
(('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_UNIT' IN TYPEOF(SELF.of_shape.definition)) AND (SELF.of_shape.definition\product_definition.frame_of_reference.name = 'physical design')) AND (SIZEOF(
QUERY (prpc <* USEDIN(SELF.of_shape.definition.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'interconnect module'))) >= 1);

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(pdr.used_representation.items) <= 3) AND (SIZEOF(
QUERY (ms <* 
QUERY (it <* pdr.used_representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'mounting surface'))| (ms.description IN [ 'interconnect module edge segment surface', 'interconnect module primary surface', 'interconnect module secondary surface' ]))) = 1))) = 1))) = 0;

wr3:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_REPRESENTATION' IN TYPEOF(pdr.used_representation)))) = 1))) = 0;

wr4:
SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_SHAPE_ASPECT' IN TYPEOF(sar.related_shape_aspect)) AND (sar.name = 'mounting surface')) AND (sar.related_shape_aspect.description = 'interconnect module component surface feature'))) = 1;
END_ENTITY;




ENTITY named_unit
SUPERTYPE OF (ONEOF(si_unit, conversion_based_unit, context_dependent_unit) ANDOR ONEOF(length_unit, mass_unit, time_unit, electric_current_unit, thermodynamic_temperature_unit, amount_of_substance_unit, luminous_intensity_unit, plane_angle_unit, solid_angle_unit, area_unit, volume_unit, ratio_unit));

dimensions : dimensional_exponents;
END_ENTITY;




ENTITY network_node_definition
SUBTYPE OF (product_definition);
UNIQUE

ur1 : id;
WHERE

wr1:
SELF.frame_of_reference.name = 'functional network design';

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (funtdna <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATING_PROPERTY_DEFINITION')| (pdr.name = 'functional unit network terminal definition node assignment'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_SHAPE' IN TYPEOF(funtdna.related_property_definition)) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FUNCTIONAL_UNIT_TERMINAL_DEFINITION' IN TYPEOF(funtdna.related_property_definition.definition)))) <= 1))) <= 1;

wr3:
SIZEOF(
QUERY (funn <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FUNCTIONAL_UNIT' IN TYPEOF(funn.relating_product_definition)) AND (funn.relating_product_definition.frame_of_reference.name = 'functional network design'))) = 1;
END_ENTITY;




ENTITY next_assembly_usage_occurrence
SUBTYPE OF (assembly_component_usage);
END_ENTITY;




ENTITY offset_curve_2d
SUBTYPE OF (curve);

basis_curve : curve;

distance : length_measure;

self_intersect : LOGICAL;
WHERE

wr1:
basis_curve.dim = 2;
END_ENTITY;




ENTITY offset_curve_3d
SUBTYPE OF (curve);

basis_curve : curve;

distance : length_measure;

self_intersect : LOGICAL;

ref_direction : direction;
WHERE

wr1:
(basis_curve.dim = 3) AND (ref_direction.dim = 3);
END_ENTITY;




ENTITY offset_surface
SUBTYPE OF (surface);

basis_surface : surface;

distance : length_measure;

self_intersect : LOGICAL;
END_ENTITY;




ENTITY one_direction_repeat_factor
SUBTYPE OF (geometric_representation_item);

repeat_factor : vector;
END_ENTITY;




ENTITY open_shell
SUBTYPE OF (connected_face_set);
END_ENTITY;




ENTITY opposing_boundary_dimensional_size
SUBTYPE OF (dimensional_size);
WHERE

wr1:
SELF\dimensional_size.name IN [ 'angular', 'linear' ];
END_ENTITY;




ENTITY organization;

id : OPTIONAL identifier;

name : label;

description : text;
END_ENTITY;




ENTITY organization_assignment
ABSTRACT SUPERTYPE;

assigned_organization : organization;

role : organization_role;
END_ENTITY;




ENTITY organization_relationship;

name : label;

description : text;

relating_organization : organization;

related_organization : organization;
END_ENTITY;




ENTITY organization_role;

name : label;
END_ENTITY;




ENTITY organizational_address
SUBTYPE OF (address);

organizations : SET [1:?] OF organization;

description : text;
END_ENTITY;




ENTITY organizational_project;

name : label;

description : text;

responsible_organizations : SET [1:?] OF organization;
END_ENTITY;




ENTITY oriented_closed_shell
SUBTYPE OF (closed_shell);

closed_shell_element : closed_shell;

orientation : BOOLEAN;
DERIVE

cfs_faces : SET [1:?] OF face := conditional_reverse(SELF.orientation, SELF.closed_shell_element.cfs_faces);
WHERE

wr1:
NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ORIENTED_CLOSED_SHELL' IN TYPEOF(SELF.closed_shell_element));
END_ENTITY;




ENTITY oriented_edge
SUBTYPE OF (edge);

edge_element : edge;

orientation : BOOLEAN;
DERIVE

edge_start : vertex := boolean_choose(SELF.orientation, SELF.edge_element.edge_start, SELF.edge_element.edge_end);

edge_end : vertex := boolean_choose(SELF.orientation, SELF.edge_element.edge_end, SELF.edge_element.edge_start);
WHERE

wr1:
NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ORIENTED_EDGE' IN TYPEOF(SELF.edge_element));
END_ENTITY;




ENTITY oriented_face
SUBTYPE OF (face);

face_element : face;

orientation : BOOLEAN;
DERIVE

bounds : SET [1:?] OF face_bound := conditional_reverse(SELF.orientation, SELF.face_element.bounds);
WHERE

wr1:
NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ORIENTED_FACE' IN TYPEOF(SELF.face_element));
END_ENTITY;




ENTITY oriented_open_shell
SUBTYPE OF (open_shell);

open_shell_element : open_shell;

orientation : BOOLEAN;
DERIVE

cfs_faces : SET [1:?] OF face := conditional_reverse(SELF.orientation, SELF.open_shell_element.cfs_faces);
WHERE

wr1:
NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ORIENTED_OPEN_SHELL' IN TYPEOF(SELF.open_shell_element));
END_ENTITY;




ENTITY oriented_path
SUBTYPE OF (path);

path_element : path;

orientation : BOOLEAN;
DERIVE

edge_list : LIST [1:?] OF UNIQUE oriented_edge := conditional_reverse(SELF.orientation, SELF.path_element.edge_list);
WHERE

wr1:
NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ORIENTED_PATH' IN TYPEOF(SELF.path_element));
END_ENTITY;




ENTITY outer_boundary_curve
SUBTYPE OF (boundary_curve);
END_ENTITY;




ENTITY package
SUBTYPE OF (physical_unit);
WHERE

wr1:
SELF.frame_of_reference.name = 'physical design usage';

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'registered case style'))) >= 1))) = 1;

wr3:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE_BODY' IN TYPEOF(sa)))) <= 1))) = 0;

wr4:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_SHAPE' IN TYPEOF(pd)) AND (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE_TERMINAL' IN TYPEOF(sa)))) >= 1)))) = 0;

wr5:
NOT (SELF.description = 'altered package') OR (SIZEOF(
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'package alteration') AND (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_PACKAGE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_PACKAGE') ] * TYPEOF(pdr.relating_product_definition)) = 1))) = 1);

wr6:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'package mounting data'))) = 1))) = 0;
END_ENTITY;




ENTITY package_body
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SIZEOF(TYPEOF(SELF.of_shape.definition) * [ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_PACKAGE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_PACKAGE') ]) = 1;

wr2:
SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MATERIAL_DESIGNATION.DEFINITIONS')) = 1;
END_ENTITY;




ENTITY package_terminal
SUPERTYPE OF (primary_reference_terminal)
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SELF\shape_aspect.description IN [ 'altered package terminal', 'guided wave terminal', 'wire terminal', '' ];

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_REPRESENTATION' IN TYPEOF(pdr.used_representation)))) >= 1))) = 0;

wr3:
SIZEOF(TYPEOF(SELF.of_shape.definition) * [ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_PACKAGE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_PACKAGE') ]) = 1;

wr4:
SIZEOF(
QUERY (md <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MATERIAL_DESIGNATION.DEFINITIONS')| (SIZEOF(
QUERY (pd <* 
QUERY (defs <* md.definitions| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION' IN TYPEOF(defs)))| (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| ((pdr.name = 'material assembly relationship') AND (pdr.description = 'terminal core material')) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_COMPONENT_USAGE' IN TYPEOF(pdr)))) = 1))) = 1))) = 1;

wr5:
SIZEOF(
QUERY (md <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MATERIAL_DESIGNATION.DEFINITIONS')| (SIZEOF(
QUERY (pd <* 
QUERY (defs <* md.definitions| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION' IN TYPEOF(defs)))| (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| ((pdr.name = 'material assembly relationship') AND (pdr.description = 'terminal surface material')) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_COMPONENT_USAGE' IN TYPEOF(pdr)))) = 1))) = 1))) = 1;

wr6:
SIZEOF(
QUERY (mct <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'member connected terminal'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_CONNECTED_TERMINALS_DEFINITION' IN TYPEOF(mct.relating_shape_aspect)))) <= 1;

wr7:
NOT (SELF\shape_aspect.description = 'altered package terminal') OR (SIZEOF(
QUERY (mct <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name IN [ 'length trimmed preparation', 'shape formed preparation', 'surface preparation' ]))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE_TERMINAL' IN TYPEOF(mct.relating_shape_aspect)))) = 1);

wr8:
NOT (SELF\shape_aspect.description = 'altered package terminal') OR (SELF.of_shape.definition\product_definition.description = 'altered package');

wr9:
NOT (SELF\shape_aspect.description = 'length trimmed terminal') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2))) = 2))) = 1))) = 0);

wr10:
NOT (SELF\shape_aspect.description = 'length trimmed terminal') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'maximum trimmed length'))) = 1))) = 1))) = 0);

wr11:
NOT (SELF\shape_aspect.description = 'length trimmed terminal') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'minimum trimmed length'))) = 1))) = 1))) = 0);

wr12:
NOT (SELF\shape_aspect.description = 'shape formed terminal') OR (SIZEOF(
QUERY (ada <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DOCUMENT_REFERENCE.ITEMS')| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EE_SPECIFICATION' IN TYPEOF(ada.assigned_document)) AND (ada.assigned_document.kind.product_data_type = 'lead form specification')) AND (SIZEOF(
QUERY (dr <* USEDIN(ada.assigned_document, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DOCUMENT_RELATIONSHIP.RELATED_DOCUMENT')| (dr.relating_document.kind.product_data_type = 'material specification'))) = 1))) = 1);

wr13:
NOT (SELF\shape_aspect.description = 'surface prepped terminal') OR (SIZEOF(
QUERY (ada <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DOCUMENT_REFERENCE.ITEMS')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EE_SPECIFICATION' IN TYPEOF(ada.assigned_document)) AND (ada.assigned_document.kind.product_data_type = 'surface finish specification'))) = 1);

wr14:
NOT (SELF\shape_aspect.description = 'wire terminal') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_UNIT' IN TYPEOF(it.unit_component)))) = 2))) = 1))) = 0);

wr15:
NOT (SELF\shape_aspect.description = 'wire terminal') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'maximum wire terminal length')) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_UNIT' IN TYPEOF(it.unit_component)))) = 1))) = 1))) = 0);

wr16:
NOT (SELF\shape_aspect.description = 'wire terminal') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'minimum wire terminal length')) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_UNIT' IN TYPEOF(it.unit_component)))) = 1))) = 1))) = 0);

wr17:
NOT (SELF\shape_aspect.description = 'wire terminal') OR (SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'internal connection zone') AND (sar.related_shape_aspect.description = 'connection zone'))) = 1);

wr18:
SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'external connection zone') AND (sar.related_shape_aspect.description = 'connection zone'))) = 1;
END_ENTITY;




ENTITY packaged_component
SUBTYPE OF (component_definition);
WHERE

wr1:
SIZEOF(
QUERY (ip <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'instantiated part'))| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_PACKAGED_PART') ] * TYPEOF(ip.relating_product_definition)) = 1) AND (ip.relating_product_definition.frame_of_reference.name = 'physical design usage'))) = 1;

wr2:
SIZEOF(
QUERY (pa <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'package alternate'))| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_PACKAGE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_PACKAGE') ] * TYPEOF(pa.relating_product_definition)) = 1) AND (pa.relating_product_definition.description = 'as installed package'))) <= 1;

wr3:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL' IN TYPEOF(sa)) AND (sa.description = 'packaged component join terminal'))) >= 1))) = 0;

wr4:
NOT (SELF.description = 'packaged connector component') OR (SIZEOF(
QUERY (ip <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'instantiated part'))| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_PACKAGED_PART') ] * TYPEOF(ip.relating_product_definition)) = 1) AND (ip.relating_product_definition.frame_of_reference.name = 'packaged connector'))) = 1);

wr5:
NOT (SELF.description = 'packaged connector component') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL' IN TYPEOF(sa)) AND (sa.description = 'packaged component join terminal'))) >= 1))) = 0);

wr6:
NOT (SELF.description = 'routed packaged component') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| (SIZEOF(
QUERY (pd <* USEDIN(sa, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')) = 1))) = 1))) = 1))) = 0);
END_ENTITY;




ENTITY packaged_connector
SUBTYPE OF (packaged_part);
END_ENTITY;




ENTITY packaged_connector_terminal_relationship
SUBTYPE OF (shape_aspect, shape_aspect_relationship);
WHERE

wr1:
SELF\shape_aspect_relationship.name IN [ 'connector interface terminal', 'connector join terminal' ];

wr2:
(SIZEOF(TYPEOF(SELF.of_shape.definition) * [ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_PACKAGED_PART') ]) = 1) AND (SELF.of_shape.definition\product_definition.description = 'packaged connector');

wr3:
NOT (SELF\shape_aspect_relationship.name = 'connector interface terminal') OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART_TERMINAL' IN TYPEOF(SELF.related_shape_aspect)) AND (SELF.related_shape_aspect.description = 'interface terminal');

wr4:
NOT (SELF\shape_aspect_relationship.name = 'connector join terminal') OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART_TERMINAL' IN TYPEOF(SELF.related_shape_aspect)) AND (SELF.related_shape_aspect.description = 'join terminal');
END_ENTITY;




ENTITY packaged_part
SUPERTYPE OF (packaged_connector)
SUBTYPE OF (physical_unit);
WHERE

wr1:
NOT (SELF.frame_of_reference.name = 'physical design usage') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART_TERMINAL' IN TYPEOF(sa)))) >= 2))) = 0);

wr2:
NOT (SELF.frame_of_reference.name = 'physical design usage') OR (SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MATERIAL_DESIGNATION.DEFINITIONS')) <= 1);

wr3:
NOT (SELF.frame_of_reference.name = 'physical design usage') OR (SIZEOF(
QUERY (ifu <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'implemented function'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FUNCTIONAL_UNIT' IN TYPEOF(ifu.relating_product_definition)) AND (ifu.relating_product_definition.frame_of_reference.name = 'functional design usage'))) = 1);

wr4:
NOT (SELF.frame_of_reference.name = 'physical design usage') OR (SIZEOF(
QUERY (upkg <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION')| (pdr.name = 'used package'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE' IN TYPEOF(upkg.related_product_definition)))) = 1);

wr5:
NOT (SELF.description = 'as installed packaged part') OR (SIZEOF(
QUERY (bpp <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'base packaged part'))| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_PACKAGED_PART') ] * TYPEOF(bpp.relating_product_definition)) = 1) AND (bpp.relating_product_definition.frame_of_reference.name = 'physical design usage'))) >= 1);

wr6:
NOT (SELF.description = 'as installed packaged part') OR (SIZEOF(
QUERY (upkg <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'used package'))| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_PACKAGED_PART') ] * TYPEOF(upkg.relating_product_definition)) = 1))) >= 1);
END_ENTITY;




ENTITY packaged_part_terminal
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SELF\shape_aspect.description IN [ 'interface terminal', 'join terminal' ];

wr2:
(SIZEOF(TYPEOF(SELF.of_shape.definition) * [ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_PACKAGED_PART'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_PACKAGED_PART') ]) = 1) AND (SELF.of_shape.definition\product_definition.frame_of_reference.name = 'physical design usage');

wr3:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_REPRESENTATION' IN TYPEOF(pdr.used_representation)))) >= 1))) = 0;

wr4:
SIZEOF(
QUERY (top <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'terminal of package'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE_TERMINAL' IN TYPEOF(top.related_shape_aspect)))) = 1;

wr5:
SIZEOF(
QUERY (mct <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'member connected terminal'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_CONNECTED_TERMINALS_DEFINITION' IN TYPEOF(mct.relating_shape_aspect)))) <= 1;
END_ENTITY;




ENTITY parabola
SUBTYPE OF (conic);

focal_dist : length_measure;
WHERE

wr1:
focal_dist <> 0;
END_ENTITY;




ENTITY parallelism_tolerance
SUBTYPE OF (geometric_tolerance_with_specified_datum_system);
WHERE

wr1:
SELF\geometric_tolerance.name = 'parallelism';
END_ENTITY;




ENTITY parameter_assignment_representation
SUBTYPE OF (representation);
WHERE

wr1:
SIZEOF(SELF.items) = 2;

wr2:
SIZEOF(
QUERY (it <* SELF.items| (it.name = 'assigned parameter') AND (SIZEOF(TYPEOF(it) * [ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MODEL_PARAMETER'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM') ]) = 1))) = 1;
END_ENTITY;




ENTITY parameter_type
SUBTYPE OF (group);
WHERE

wr1:
SELF\group.name IN [ 'string property type', 'logical property type', 'physical property type', 'boolean property type' ];
END_ENTITY;




ENTITY parametric_representation_context
SUBTYPE OF (representation_context);
END_ENTITY;




ENTITY part_connected_terminals_definition
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SIZEOF(
QUERY (mct <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'member connected terminal'))| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_MODULE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'BARE_DIE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTERCONNECT_MODULE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART_TERMINAL') ] * TYPEOF(mct.related_shape_aspect)) = 1))) >= 2;
END_ENTITY;




ENTITY part_mounting_feature
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'mounting area') AND (sar.related_shape_aspect.description = 'connection zone'))) = 1;
END_ENTITY;




ENTITY part_template_definition
SUBTYPE OF (shape_aspect, externally_defined_item);
WHERE

wr1:
('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CHARACTERIZED_OBJECT' IN TYPEOF(SELF.of_shape.definition)) OR (SELF\shape_aspect.of_shape\property_definition.definition.frame_of_reference\application_context_element.name = 'template definition');

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ANALYTICAL_MODEL' IN TYPEOF(pdr.used_representation)) AND (pdr.used_representation.name = 'part template analytical model'))) <= 1))) = 0;

wr3:
NOT (SELF.description = 'component termination passage template') OR (SIZEOF(
QUERY (ctpt <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'component passage terminal technology'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PASSAGE_TECHNOLOGY' IN TYPEOF(ctpt.relating_shape_aspect)) AND (ctpt.relating_shape_aspect.description = 'default component termination passage definition'))) = 1);

wr4:
NOT (SELF.description = 'component termination passage template') OR (SIZEOF(
QUERY (am <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'access mechanism'))| (am.related_shape_aspect.description IN [ 'component termination passage template interface terminal', 'component termination passage template join terminal' ]))) >= 2);

wr5:
NOT (SELF.description = 'default trace template') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (tu <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')| (pdr.name = 'technology usage'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_TECHNOLOGY' IN TYPEOF(tu.relating_property_definition.definition)))) = 1))) = 1);

wr6:
NOT (SELF.description = 'inter stratum feature template') OR (SIZEOF(
QUERY (isfpt <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'inter stratum feature passage technology'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PASSAGE_TECHNOLOGY' IN TYPEOF(isfpt.relating_shape_aspect)))) = 1);

wr7:
NOT (SELF.description = 'printed connector template') OR (SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name IN [ 'connector interface terminal', 'connector join terminal' ]))) >= 1);

wr8:
NOT (SELF.description = 'printed part cross section template') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ANALYTICAL_MODEL' IN TYPEOF(pdr.used_representation)) AND (pdr.used_representation.name = 'transmission line model'))) = 1))) = 0);

wr9:
NOT (SELF.description = 'printed part cross section template') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2))) = 2))) = 1))) = 0);

wr10:
NOT (SELF.description = 'printed part cross section template') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'maximum width'))) = 1))) = 1))) = 0);

wr11:
NOT (SELF.description = 'printed part cross section template') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'minimum width'))) = 1))) = 1))) = 0);

wr12:
NOT (SELF.description = 'printed part cross section template') OR (SIZEOF(
QUERY (am <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'access mechanism'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRINTED_PART_CROSS_SECTION_TEMPLATE_TERMINAL' IN TYPEOF(am.related_shape_aspect)))) >= 2);

wr13:
NOT (SELF.description = 'printed part template') OR (SIZEOF(
QUERY (impl_func <* 
QUERY (pdr <* USEDIN(SELF.of_shape.definition, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.' + 'RELATED_PRODUCT_DEFINITION')| (pdr.name = 'implemented function'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FUNCTIONAL_UNIT' IN TYPEOF(impl_func.relating_product_definition)) AND (impl_func.relating_product_definition.frame_of_reference.name = 'functional design usage'))) = 1);

wr14:
NOT (SELF.description = 'printed part template') OR (SIZEOF(
QUERY (cs <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'cross section'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_TEMPLATE_DEFINITION' IN TYPEOF(cs.relating_shape_aspect)) AND (cs.relating_shape_aspect.description = 'printed part cross section template'))) <= 1);

wr15:
NOT (SELF.description = 'printed part template') OR (SIZEOF(
QUERY (ad <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'associated definition'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRINTED_PART_TEMPLATE_TERMINAL' IN TYPEOF(ad.related_shape_aspect)) AND (ad.relating_shape_aspect.description IN [ 'interface terminal', 'join terminal' ]))) >= 2);

wr16:
NOT (SELF.description = 'trace template') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (si <* 
QUERY (it <* pdr.used_representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STYLED_ITEM' IN TYPEOF(it)))| (si.name = 'trace style') AND (SIZEOF(
QUERY (psa <* si.styles| NOT (SIZEOF(
QUERY (sty <* psa.styles| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CURVE_STYLE' IN TYPEOF(sty)))) = 1))) = 0))) = 1))) = 1))) = 0);

wr17:
NOT (SELF.description = 'unsupported passage template') OR (SIZEOF(
QUERY (upt <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'unsupported passage technology'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PASSAGE_TECHNOLOGY' IN TYPEOF(upt.relating_shape_aspect)) AND (upt.relating_shape_aspect.description = 'default unsupported passage definition'))) = 1);

wr18:
NOT (SELF.description = 'via template') OR (SIZEOF(
QUERY (vpt <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'via passage technology'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PASSAGE_TECHNOLOGY' IN TYPEOF(vpt.relating_shape_aspect)) AND (vpt.relating_shape_aspect.description = 'default via definition'))) = 1);

wr19:
NOT (SELF.description = 'via template') OR (SIZEOF(
QUERY (am <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'access mechanism'))| (am.related_shape_aspect.description = 'via template terminal'))) >= 2);

wr20:
SIZEOF(
QUERY (esr <* USEDIN(SELF.source, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNAL_SOURCE_RELATIONSHIP.RELATING_SOURCE')| (esr.name = 'revision'))) = 1;
END_ENTITY;




ENTITY part_text_template_definition
SUBTYPE OF (part_template_definition);
WHERE

wr1:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'TEXT_LITERAL' IN TYPEOF(it)))) = 1))) = 1))) = 0;

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'maximum font vertical extent'))) = 1))) = 1))) = 0;

wr3:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'maximum font horizontal extent'))) = 1))) = 1))) = 0;
END_ENTITY;




ENTITY part_tooling_feature
SUPERTYPE OF (fiducial_part_feature)
SUBTYPE OF (shape_aspect);
END_ENTITY;




ENTITY passage_technology
SUBTYPE OF (shape_aspect);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CHARACTERIZED_OBJECT' IN TYPEOF(SELF.of_shape.definition);

wr2:
SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MATERIAL_DESIGNATION.DEFINITIONS')) <= 1;

wr3:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))) = 1))) = 0;

wr4:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT ((2 <= SIZEOF(pcr.used_representation.items)) AND (SIZEOF(pcr.used_representation.items) <= 8)))) = 0))) = 0;

wr5:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| NOT (it.name IN [ 'maximum aspect ratio', 'plated passage', 'maximum allowed component terminal extent', 'minimum allowed component terminal extent', 'maximum as finished deposition thickness', 'minimum as finished deposition thickness', 'maximum as finished passage extent', 'minimum as finished passage extent' ]))) = 0))) = 0))) = 0;

wr6:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| ((SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'RATIO_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'maximum aspect ratio')) AND (it\measure_with_unit.value_component > 1))) <= 1))) = 0))) = 0;

wr7:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'plated passage')) AND (it.description IN [ 'true', 'false' ]))) = 1))) = 0))) = 0;

wr8:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'minimum as finished passage extent'))) <= 1))) = 0))) = 0;

wr9:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'maximum as finished deposition thickness'))) <= 1))) = 0))) = 0;

wr10:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'minimum as finished deposition thickness'))) = 1))) = 0))) = 0;

wr11:
NOT (SELF\shape_aspect.description IN [ 'default component termination passage definition', 'default via definition' ]) OR (SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MATERIAL_DESIGNATION.DEFINITIONS')) = 1);

wr12:
NOT (SELF\shape_aspect.description IN [ 'default component termination passage definition', 'default unsupported passage definition', 'default via definition' ]) OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'minimum as finished passage extent'))) = 1))) = 0))) = 0);

wr13:
NOT (SELF\shape_aspect.description = 'default component termination passage definition') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'minimum as finished deposition thickness'))) = 1))) = 0))) = 0);

wr14:
NOT (SELF\shape_aspect.description = 'default component termination passage definition') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'minimum allowed component terminal extent'))) = 1))) = 0))) = 0);

wr15:
NOT (SELF\shape_aspect.description = 'default component termination passage definition') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'maximum allowed component terminal extent'))) = 1))) = 0))) = 0);

wr16:
NOT (SELF\shape_aspect.description = 'default via definition') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'minimum as finished deposition thickness'))) = 1))) = 0))) = 0);

wr17:
SIZEOF(
QUERY (rpt <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'as finished inter stratum extent'))| ((rpt.related_shape_aspect.of_shape\property_definition.description = 'finished stratum extent') AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP' IN TYPEOF(rpt.related_shape_aspect.of_shape\property_definition.definition))) AND (rpt.related_shape_aspect.of_shape\property_definition.definition.name = 'inter stratum extent'))) = 1;
END_ENTITY;




ENTITY path
SUPERTYPE OF (ONEOF(edge_loop, oriented_path))
SUBTYPE OF (topological_representation_item);

edge_list : LIST [1:?] OF UNIQUE oriented_edge;
WHERE

wr1:
path_head_to_tail(SELF);
END_ENTITY;




ENTITY pcurve
SUBTYPE OF (curve);

basis_surface : surface;

reference_to_curve : definitional_representation;
WHERE

wr1:
SIZEOF(reference_to_curve\representation.items) = 1;

wr2:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CURVE' IN TYPEOF(reference_to_curve\representation.items[1]);

wr3:
reference_to_curve\representation.items[1]\geometric_representation_item.dim = 2;
END_ENTITY;




ENTITY perpendicularity_tolerance
SUBTYPE OF (geometric_tolerance_with_specified_datum_system);
WHERE

wr1:
SELF\geometric_tolerance.name = 'perpendicularity';
END_ENTITY;




ENTITY person;

id : identifier;

last_name : OPTIONAL label;

first_name : OPTIONAL label;

middle_names : OPTIONAL LIST [1:?] OF label;

prefix_titles : OPTIONAL LIST [1:?] OF label;

suffix_titles : OPTIONAL LIST [1:?] OF label;
UNIQUE

ur1 : id;
WHERE

wr1:
EXISTS(last_name) OR EXISTS(first_name);
END_ENTITY;




ENTITY person_and_organization;

the_person : person;

the_organization : organization;
END_ENTITY;




ENTITY person_and_organization_assignment
ABSTRACT SUPERTYPE;

assigned_person_and_organization : person_and_organization;

role : person_and_organization_role;
END_ENTITY;




ENTITY person_and_organization_role;

name : label;
END_ENTITY;




ENTITY person_assignment
ABSTRACT SUPERTYPE;

assigned_person : person;

role : person_role;
END_ENTITY;




ENTITY person_role;

name : label;
END_ENTITY;




ENTITY personal_address
SUBTYPE OF (address);

people : SET [1:?] OF person;

description : text;
END_ENTITY;




ENTITY physical_connectivity_definition
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SIZEOF(
QUERY (at <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'associated terminals'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL' IN TYPEOF(at.related_shape_aspect)))) > 1;

wr2:
SIZEOF(
QUERY (pdr <* USEDIN(SELF.of_shape.definition, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| (pdr.name = 'connectivity allocation'))) <= 1;
END_ENTITY;




ENTITY physical_connectivity_element
SUBTYPE OF (shape_aspect_relationship, shape_aspect);
WHERE

wr1:
(SELF.relating_shape_aspect.description = 'topological junction') XOR (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CONNECTIVITY_SUB_STRUCTURE') ] * TYPEOF(SELF.relating_shape_aspect)) = 1);

wr2:
(SELF.related_shape_aspect.description = 'topological junction') XOR (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CONNECTIVITY_SUB_STRUCTURE') ] * TYPEOF(SELF.related_shape_aspect)) = 1);

wr3:
SIZEOF(
QUERY (se <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'structure element'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_CONNECTIVITY_DEFINITION' IN TYPEOF(se.relating_shape_aspect)))) = 1;

wr4:
('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_UNIT' IN TYPEOF(SELF.of_shape.definition)) AND (SELF.of_shape.definition\product_definition.frame_of_reference.name = 'physical design');
END_ENTITY;




ENTITY physical_network
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SIZEOF(
QUERY (cr <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'connectivity requirement'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL' IN TYPEOF(cr.related_shape_aspect)))) >= 2;

wr2:
SIZEOF(
QUERY (nt <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'network topology'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'JOIN_SHAPE_ASPECT' IN TYPEOF(nt.related_shape_aspect)))) >= 1;
END_ENTITY;




ENTITY physical_unit
SUPERTYPE OF (ONEOF(bare_die, package, packaged_part, assembly_definition, interconnect_definition))
SUBTYPE OF (product_definition);
WHERE

wr1:
NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_WITH_ASSOCIATED_DOCUMENTS' IN TYPEOF(SELF)) OR (SIZEOF(
QUERY (docs <* SELF\product_definition_with_associated_documents.documentation_ids| (docs.kind.product_data_type = 'CAD filename'))) <= 1);

wr2:
SIZEOF(
QUERY (adta <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DATE_AND_TIME_ASSIGNMENT.ITEMS')| (adta.role.name = 'creation date'))) + SIZEOF(
QUERY (ada <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DATE_ASSIGNMENT.ITEMS')| (ada.role.name = 'creation date'))) = 1;

wr3:
SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_APPROVAL_ASSIGNMENT.ITEMS')) = 1;

wr4:
SIZEOF(
QUERY (apoa <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_PERSON_AND_ORGANIZATION_ASSIGNMENT.ITEMS')| (apoa.role.name = 'creator'))) + SIZEOF(
QUERY (apoa <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_ORGANIZATION_ASSIGNMENT.ITEMS')| (apoa.role.name = 'creator'))) >= 1;

wr5:
SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_SECURITY_CLASSIFICATION_ASSIGNMENT.ITEMS')) = 1;

wr6:
SELF.frame_of_reference.name IN [ 'physical design', 'physical design usage' ];

wr7:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (pd.name = 'unit technology'))) <= 1;

wr8:
NOT ((SELF.frame_of_reference.name = 'physical design') AND (SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.' + 'PRODUCTS')| (prpc\product_category.name = 'assembly module'))) >= 1)) OR (SIZEOF(
QUERY (du <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.' + 'RELATING_PRODUCT_DEFINITION')| (pdr.name = 'design usage'))| (du.related_product_definition.frame_of_reference.name = 'physical design usage') AND (SIZEOF(
QUERY (prpc <* USEDIN(du.related_product_definition.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.' + 'PRODUCTS')| (prpc\product_category.name = 'assembly module'))) >= 1))) = 1);

wr9:
NOT ((SELF.frame_of_reference.name = 'physical design usage') AND (SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.' + 'PRODUCTS')| (prpc\product_category.name = 'assembly module'))) >= 1)) OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_MODULE_TERMINAL' IN TYPEOF(sa)))) >= 2))) = 0);

wr10:
NOT ((SELF.frame_of_reference.name = 'physical design usage') AND (SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.' + 'PRODUCTS')| (prpc\product_category.name = 'assembly module'))) >= 1)) OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'maximum negative component height'))) <= 1))) = 0);

wr11:
NOT ((SELF.frame_of_reference.name = 'physical design usage') AND (SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.' + 'PRODUCTS')| (prpc\product_category.name = 'assembly module'))) >= 1)) OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'maximum positive component height'))) <= 1))) = 0);

wr12:
NOT ((SELF.frame_of_reference.name = 'physical design usage') AND (SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.' + 'PRODUCTS')| (prpc\product_category.name = 'assembly module'))) >= 1)) OR (SIZEOF(
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.' + 'RELATED_PRODUCT_DEFINITION')| (pdr.name = 'implemented function') AND (pdr.relating_product_definition.frame_of_reference.name = 'functional design usage'))) = 1);

wr13:
NOT ((SELF.frame_of_reference.name = 'physical design') AND (SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.' + 'PRODUCTS')| (prpc\product_category.name = 'assembly module'))) >= 1)) OR (SIZEOF(
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.' + 'RELATED_PRODUCT_DEFINITION')| (pdr.relating_product_definition.description = 'laminate component'))) = 0);

wr14:
NOT ((SELF.frame_of_reference.name = 'physical design') AND (SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.' + 'PRODUCTS')| (prpc\product_category.name = 'interconnect module'))) >= 1)) OR (SIZEOF(
QUERY (du <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.' + 'RELATING_PRODUCT_DEFINITION')| (pdr.name = 'design usage'))| (du.related_product_definition.frame_of_reference.name = 'physical design usage') AND (SIZEOF(
QUERY (prpc <* USEDIN(du.related_product_definition.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.' + 'PRODUCTS')| (prpc\product_category.name = 'interconnect module'))) >= 1))) = 1);

wr15:
NOT ((SELF.frame_of_reference.name = 'physical design usage') AND (SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.' + 'PRODUCTS')| (prpc\product_category.name = 'interconnect module'))) >= 1)) OR (SIZEOF(
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.' + 'RELATED_PRODUCT_DEFINITION')| (pdr.name = 'implemented function') AND (pdr.relating_product_definition.frame_of_reference.name = 'functional design usage'))) = 1);

wr16:
NOT ((SELF.frame_of_reference.name = 'physical design usage') AND (SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.' + 'PRODUCTS')| (prpc\product_category.name = 'interconnect module'))) >= 1)) OR (SIZEOF(
QUERY (rp <* 
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REQUIREMENTS_PROPERTY' IN TYPEOF(pd)))| (rp.name = 'located interconnect module thickness'))) = 1);

wr17:
NOT (SELF.frame_of_reference.name = 'physical design') OR (SIZEOF(
QUERY (du <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.' + 'RELATING_PRODUCT_DEFINITION')| (pdr.name = 'design usage'))| (du.related_product_definition.frame_of_reference.name = 'physical design usage'))) = 1);
END_ENTITY;




ENTITY physical_unit_datum
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SELF\shape_aspect.description IN [ 'axis', 'plane', 'point' ];
END_ENTITY;




ENTITY physical_unit_datum_feature
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.' + 'DEFINITION')| (pd.description = 'datum feature identification'))) = 1;
END_ENTITY;




ENTITY physical_unit_datum_target
SUBTYPE OF (shape_aspect);
END_ENTITY;




ENTITY physical_unit_datum_target_set
SUBTYPE OF (physical_unit_datum_feature);
END_ENTITY;




ENTITY physical_unit_geometric_tolerance
SUBTYPE OF (geometric_tolerance, property_definition);
WHERE

wr1:
SELF\geometric_tolerance.name = SELF\property_definition.name;
END_ENTITY;




ENTITY placement
SUPERTYPE OF (ONEOF(axis1_placement, axis2_placement_2d, axis2_placement_3d))
SUBTYPE OF (geometric_representation_item);

location : cartesian_point;
END_ENTITY;




ENTITY planar_extent
SUBTYPE OF (geometric_representation_item);

size_in_x : length_measure;

size_in_y : length_measure;
END_ENTITY;




ENTITY plane
SUBTYPE OF (elementary_surface);
END_ENTITY;




ENTITY plane_angle_measure_with_unit
SUBTYPE OF (measure_with_unit);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PLANE_ANGLE_UNIT' IN TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY;




ENTITY plane_angle_unit
SUBTYPE OF (named_unit);
WHERE

wr1:
((((((SELF\named_unit.dimensions.length_exponent = 0) AND (SELF\named_unit.dimensions.mass_exponent = 0)) AND (SELF\named_unit.dimensions.time_exponent = 0)) AND (SELF\named_unit.dimensions.electric_current_exponent = 0)) AND (SELF\named_unit.dimensions.thermodynamic_temperature_exponent = 0)) AND (SELF\named_unit.dimensions.amount_of_substance_exponent = 0)) AND (SELF\named_unit.dimensions.luminous_intensity_exponent = 0);
END_ENTITY;




ENTITY plated_inter_stratum_feature
SUPERTYPE OF (plated_passage)
SUBTYPE OF (inter_stratum_feature);
WHERE

wr1:
SELF.description IN [ 'bonded conductive base blind via', 'buried via', 'component termination passage', 'interfacial connection', 'non conductive base blind via', 'plated conductive base blind via', 'plated cutout', 'plated cutout edge segment', 'plated interconnect module edge segment', 'plated interconnect module edge' ];

wr2:
SIZEOF(
QUERY (ji <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'join implementation'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'JOIN_SHAPE_ASPECT' IN TYPEOF(ji.relating_shape_aspect)) AND (ji.relating_shape_aspect.name = 'inter stratum join'))) <= 1;

wr3:
NOT (SELF.description = 'plated cutout edge segment') OR (SIZEOF(
QUERY (cc <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'composed cutout'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PLATED_INTER_STRATUM_FEATURE' IN TYPEOF(cc.relating_shape_aspect)) AND (cc.relating_shape_aspect.description = 'plated cutout'))) = 1);

wr4:
NOT (SELF.description = 'plated interconnect module edge segment') OR (SIZEOF(
QUERY (ce <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'composed edge'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PLATED_INTER_STRATUM_FEATURE' IN TYPEOF(ce.relating_shape_aspect)) AND (ce.relating_shape_aspect.description = 'plated interconnect module edge'))) = 1);
END_ENTITY;




ENTITY plated_passage
SUBTYPE OF (plated_inter_stratum_feature);
WHERE

wr1:
SELF.description IN [ 'bonded conductive base blind via', 'buried via', 'component termination passage', 'interfacial connection', 'non conductive base blind via', 'plated conductive base blind via' ];

wr2:
NOT (SELF.description = 'bonded conductive base blind via') OR (SIZEOF(
QUERY (fj <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'features join'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_CONCEPT_RELATIONSHIP' IN TYPEOF(fj.relating_shape_aspect)) AND (fj.relating_shape_aspect.name = 'stratum feature conductive join'))) = 1);

wr3:
NOT (SELF.description = 'component termination passage') OR (SIZEOF(
QUERY (it <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated template'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_TEMPLATE_DEFINITION' IN TYPEOF(it.relating_shape_aspect)) AND (it.relating_shape_aspect.description = 'component termination passage template'))) = 1);

wr4:
NOT (SELF.description = 'component termination passage') OR (SIZEOF(
QUERY (ac <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'associated component'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_SHAPE_ASPECT' IN TYPEOF(ac.related_shape_aspect)) AND (ac.related_shape_aspect.description = 'component termination passage interface terminal'))) = 1);

wr5:
NOT (SELF.description = 'component termination passage') OR (SIZEOF(
QUERY (ac <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'associated component'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL' IN TYPEOF(ac.related_shape_aspect)) AND (ac.related_shape_aspect.description = 'component termination passage join terminal'))) >= 1);

wr6:
NOT (SELF.description IN [ 'bonded conductive base blind via', 'buried via', 'interfacial connection', 'non conductive base blind via', 'plated conductive base blind via' ]) OR (SIZEOF(
QUERY (it <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated template'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_TEMPLATE_DEFINITION' IN TYPEOF(it.relating_shape_aspect)) AND (it.relating_shape_aspect.description = 'via template'))) = 1);
END_ENTITY;




ENTITY plus_minus_tolerance;

range : tolerance_method_definition;

toleranced_dimension : dimensional_characteristic;
UNIQUE

ur1 : toleranced_dimension;
END_ENTITY;




ENTITY point
SUPERTYPE OF (ONEOF(cartesian_point, point_on_curve, point_on_surface, point_replica, degenerate_pcurve))
SUBTYPE OF (geometric_representation_item);
END_ENTITY;




ENTITY point_on_curve
SUBTYPE OF (point);

basis_curve : curve;

point_parameter : parameter_value;
END_ENTITY;




ENTITY point_on_surface
SUBTYPE OF (point);

basis_surface : surface;

point_parameter_u : parameter_value;

point_parameter_v : parameter_value;
END_ENTITY;




ENTITY point_replica
SUBTYPE OF (point);

parent_pt : point;

transformation : cartesian_transformation_operator;
WHERE

wr1:
transformation.dim = parent_pt.dim;

wr2:
acyclic_point_replica(SELF, parent_pt);
END_ENTITY;




ENTITY poly_loop
SUBTYPE OF (loop, geometric_representation_item);

polygon : LIST [3:?] OF UNIQUE cartesian_point;
END_ENTITY;




ENTITY polyline
SUBTYPE OF (bounded_curve);

points : LIST [2:?] OF cartesian_point;
END_ENTITY;




ENTITY position_tolerance
SUBTYPE OF (physical_unit_geometric_tolerance);
END_ENTITY;




ENTITY positional_boundary
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SELF\shape_aspect.description IN [ 'dimension related positional boundary', 'profile related positional boundary' ];
END_ENTITY;




ENTITY positional_boundary_member
SUBTYPE OF (shape_aspect);
END_ENTITY;




ENTITY pre_defined_curve_font
SUBTYPE OF (pre_defined_item);
END_ENTITY;




ENTITY pre_defined_item;

name : label;
END_ENTITY;




ENTITY precision_qualifier;

precision_value : INTEGER;
END_ENTITY;




ENTITY presentation_representation
SUBTYPE OF (representation);
WHERE

wr1:
SELF\representation.context_of_items\geometric_representation_context.coordinate_space_dimension = 2;

wr2:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.GEOMETRIC_REPRESENTATION_CONTEXT' IN TYPEOF(SELF\representation.context_of_items);
END_ENTITY;




ENTITY presentation_style_assignment;

styles : SET [1:?] OF presentation_style_select;
WHERE

wr1:
SIZEOF(
QUERY (style1 <* SELF.styles| NOT (SIZEOF(
QUERY (style2 <* SELF.styles - style1| NOT ((TYPEOF(style1) <> TYPEOF(style2)) OR (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SURFACE_STYLE_USAGE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_STYLE') ] * TYPEOF(style1)) = 1)))) = 0))) = 0;

wr2:
SIZEOF(
QUERY (style1 <* SELF.styles| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SURFACE_STYLE_USAGE' IN TYPEOF(style1)))) <= 2;
END_ENTITY;




ENTITY presentation_style_by_context
SUBTYPE OF (presentation_style_assignment);

style_context : style_context_select;
END_ENTITY;




ENTITY primary_orientation_feature
SUBTYPE OF (shape_aspect);
END_ENTITY;




ENTITY primary_reference_terminal
SUBTYPE OF (package_terminal);
END_ENTITY;




ENTITY printed_component
SUBTYPE OF (component_definition);
WHERE

wr1:
SELF.frame_of_reference.name = 'physical occurrence';

wr2:
SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'interconnect module'))) >= 1;

wr3:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pt_occ <* 
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| (sa.description = 'part template occurrence'))| (SIZEOF(
QUERY (it <* 
QUERY (sar <* USEDIN(pt_occ, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated template'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_TEMPLATE_DEFINITION' IN TYPEOF(it.relating_shape_aspect)) AND (it.relating_shape_aspect.description IN [ 'printed part template', 'printed part cross section template', 'printed connector template' ]))) = 1))) = 1))) = 0;

wr4:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL' IN TYPEOF(sa)) AND (sa.description = 'printed component join terminal'))) >= 1))) = 0;

wr5:
NOT (SELF.description = 'join 2 physical connectivity definition supporting') OR (SIZEOF(
QUERY (propd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (ri <* 
QUERY (propdr <* USEDIN(propd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')| (propdr.name = 'requirement implementation'))| ((('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP' IN TYPEOF(ri.relating_property_definition.definition)) AND (ri.relating_property_definition.definition.name = 'ordered physical connectivity definition')) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_CONNECTIVITY_DEFINITION' IN TYPEOF(ri.relating_property_definition.definition.related_shape_aspect))) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_CONNECTIVITY_DEFINITION' IN TYPEOF(ri.relating_property_definition.definition.relating_shape_aspect)))) = 1))) = 1);

wr6:
NOT (SELF.description = 'printed connector component') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_SHAPE_ASPECT' IN TYPEOF(sa)) AND (sa.description = 'printed connector component interface terminal'))) >= 1))) = 0);

wr7:
NOT (SELF.description = 'printed connector component') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pt_occ <* 
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| (sa.description = 'part template occurrence'))| (SIZEOF(
QUERY (it <* 
QUERY (sar <* USEDIN(pt_occ, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'instantiated template'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_TEMPLATE_DEFINITION' IN TYPEOF(it.relating_shape_aspect)) AND (it.relating_shape_aspect.description = 'printed connector template'))) = 1))) = 1))) = 0);
END_ENTITY;




ENTITY printed_part_cross_section_template_terminal
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SIZEOF(
QUERY (am <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'access mechanism'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_TEMPLATE_DEFINITION' IN TYPEOF(am.relating_shape_aspect)) AND (am.relating_shape_aspect.description = 'printed part cross section template'))) = 1;
END_ENTITY;




ENTITY printed_part_template_connected_terminals_definition
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SIZEOF(
QUERY (mct <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'member connected terminal'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRINTED_PART_TEMPLATE_TERMINAL' IN TYPEOF(mct.related_shape_aspect)) AND (mct.related_shape_aspect.description IN [ 'interface terminal', 'join terminal' ]))) >= 2;
END_ENTITY;




ENTITY printed_part_template_terminal
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SELF.description IN [ 'interface terminal', 'join terminal' ];

wr2:
SIZEOF(
QUERY (ga <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_GROUP_ASSIGNMENT.ITEMS')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRINTED_PART_TEMPLATE_TERMINAL_CONNECTION_ZONE_CATEGORY' IN TYPEOF(ga.assigned_group)))) = 1;

wr3:
SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.related_shape_aspect.description = 'connection zone'))) >= 1;

wr4:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_REPRESENTATION' IN TYPEOF(pdr.used_representation)))) >= 1))) = 0;

wr5:
SIZEOF(
QUERY (ad <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'associated definition'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_TEMPLATE_DEFINITION' IN TYPEOF(ad.relating_shape_aspect)) AND (ad.relating_shape_aspect.description = 'printed part template'))) = 1;

wr6:
SIZEOF(
QUERY (mct <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'member connected terminal'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRINTED_PART_TEMPLATE_CONNECTED_TERMINALS_DEFINITION' IN TYPEOF(mct.relating_shape_aspect)))) <= 1;

wr7:
NOT (SELF.description = 'interface terminal') OR (SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'connector interface terminal'))) >= 1);

wr8:
NOT (SELF.description = 'join terminal') OR (SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'connector join terminal'))) >= 1);
END_ENTITY;




ENTITY printed_part_template_terminal_connection_zone_category
SUBTYPE OF (group);
WHERE

wr1:
SELF\group.name IN [ 'area edge segment', 'curve edge segment', 'surface area', 'surface point' ];
END_ENTITY;




ENTITY probe_access_area
SUBTYPE OF (component_shape_aspect);
WHERE

wr1:
('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_DEFINITION' IN TYPEOF(SELF.of_shape.definition)) AND (SIZEOF(
QUERY (prpc <* USEDIN(SELF.of_shape.definition.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.PRODUCTS')| (prpc\product_category.name = 'interconnect module'))) >= 1);

wr2:
SIZEOF(
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.related_shape_aspect.description = 'connection zone'))) = 1;

wr3:
SIZEOF(
QUERY (pli <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'probed layout item'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_FEATURE' IN TYPEOF(pli.related_shape_aspect)))) = 1;

wr4:
NOT (SELF\shape_aspect.description = 'internal probe access area') OR (SIZEOF(
QUERY (i <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'implementation'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_FEATURE' IN TYPEOF(i.relating_shape_aspect)))) = 1);
END_ENTITY;




ENTITY product;

id : identifier;

name : label;

description : text;

frame_of_reference : SET [1:?] OF product_context;
UNIQUE

ur1 : id;
END_ENTITY;




ENTITY product_category;

name : label;

description : OPTIONAL text;
END_ENTITY;




ENTITY product_category_relationship;

name : label;

description : text;

category : product_category;

sub_category : product_category;
WHERE

wr1:
acyclic_product_category_relationship(SELF, [ SELF.sub_category ]);
END_ENTITY;




ENTITY product_concept;

id : identifier;

name : label;

description : text;

market_context : product_concept_context;
UNIQUE

ur1 : id;
END_ENTITY;




ENTITY product_concept_context
SUBTYPE OF (application_context_element);

market_segment_type : label;
END_ENTITY;




ENTITY product_context
SUBTYPE OF (application_context_element);

discipline_type : label;
END_ENTITY;




ENTITY product_definition;

id : identifier;

description : text;

formation : product_definition_formation;

frame_of_reference : product_definition_context;
END_ENTITY;




ENTITY product_definition_context
SUBTYPE OF (application_context_element);

life_cycle_stage : label;
END_ENTITY;




ENTITY product_definition_effectivity
SUBTYPE OF (effectivity);

usage : product_definition_relationship;
UNIQUE

ur1 : usage, id;
END_ENTITY;




ENTITY product_definition_formation;

id : identifier;

description : text;

of_product : product;
UNIQUE

ur1 : id, of_product;
END_ENTITY;




ENTITY product_definition_formation_relationship;

id : identifier;

name : label;

description : text;

relating_product_definition_formation : product_definition_formation;

related_product_definition_formation : product_definition_formation;
END_ENTITY;




ENTITY product_definition_formation_with_specified_source
SUBTYPE OF (product_definition_formation);

make_or_buy : source;
END_ENTITY;




ENTITY product_definition_relationship;

id : identifier;

name : label;

description : text;

relating_product_definition : product_definition;

related_product_definition : product_definition;
END_ENTITY;




ENTITY product_definition_shape
SUBTYPE OF (property_definition);
UNIQUE

ur1 : definition;
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CHARACTERIZED_PRODUCT_DEFINITION' IN TYPEOF(SELF\property_definition.definition);
END_ENTITY;




ENTITY product_definition_usage
SUPERTYPE OF (ONEOF(make_from_usage_option, assembly_component_usage))
SUBTYPE OF (product_definition_relationship);
UNIQUE

ur1 : id, relating_product_definition, related_product_definition;
WHERE

wr1:
acyclic_product_definition_relationship(SELF, [ SELF\product_definition_relationship.related_product_definition ], 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PRODUCT_DEFINITION_RELATIONSHIP.' + 'RELATED_PRODUCT_DEFINITION');
END_ENTITY;




ENTITY product_definition_with_associated_documents
SUBTYPE OF (product_definition);

documentation_ids : SET [1:?] OF document;
END_ENTITY;




ENTITY product_material_composition_relationship
SUBTYPE OF (product_definition_relationship);

class : label;

constituent_amount : SET [1:?] OF measure_with_unit;

composition_basis : label;

determination_method : text;
END_ENTITY;




ENTITY product_related_characterized_product_category
SUBTYPE OF (characterized_product_category, product_related_product_category);
WHERE

wr1:
SIZEOF(SELF\product_related_product_category.products) = 1;

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (pd.description = 'product category parameter') AND (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MODEL_PARAMETER'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTION_REPRESENTATION_ITEM') ] * TYPEOF(pdr.used_representation)) = 1))) = 1))) = 1;

wr3:
SIZEOF(
QUERY (pcr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_CATEGORY_RELATIONSHIP.SUB_CATEGORY')| (pcr.description = 'product value assignment') AND (SIZEOF(('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY' IN TYPEOF(pcr.category))) = 1))) = 1;
END_ENTITY;




ENTITY product_related_product_category
SUBTYPE OF (product_category);

products : SET [1:?] OF product;
END_ENTITY;




ENTITY projected_zone_definition
SUBTYPE OF (tolerance_zone_definition);

projection_end : shape_aspect;

projected_length : measure_with_unit;
WHERE

wr1:
projected_length.value_component > 0;
END_ENTITY;




ENTITY promissory_usage_occurrence
SUBTYPE OF (assembly_component_usage);
END_ENTITY;




ENTITY property_definition;

name : label;

description : text;

definition : characterized_definition;
END_ENTITY;




ENTITY property_definition_relationship;

name : label;

description : text;

relating_property_definition : property_definition;

related_property_definition : property_definition;
END_ENTITY;




ENTITY property_definition_representation;

definition : property_definition;

used_representation : representation;
END_ENTITY;




ENTITY qualitative_uncertainty
SUBTYPE OF (uncertainty_qualifier);

uncertainty_value : text;
END_ENTITY;




ENTITY quantified_assembly_component_usage
SUBTYPE OF (assembly_component_usage);

quantity : measure_with_unit;
END_ENTITY;




ENTITY quasi_uniform_curve
SUBTYPE OF (b_spline_curve);
END_ENTITY;




ENTITY quasi_uniform_surface
SUBTYPE OF (b_spline_surface);
END_ENTITY;




ENTITY ratio_measure_with_unit
SUBTYPE OF (measure_with_unit);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.RATIO_UNIT' IN TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY;




ENTITY ratio_unit
SUBTYPE OF (named_unit);
WHERE

wr1:
((((((SELF\named_unit.dimensions.length_exponent = 0) AND (SELF\named_unit.dimensions.mass_exponent = 0)) AND (SELF\named_unit.dimensions.time_exponent = 0)) AND (SELF\named_unit.dimensions.electric_current_exponent = 0)) AND (SELF\named_unit.dimensions.thermodynamic_temperature_exponent = 0)) AND (SELF\named_unit.dimensions.amount_of_substance_exponent = 0)) AND (SELF\named_unit.dimensions.luminous_intensity_exponent = 0);
END_ENTITY;




ENTITY rational_b_spline_curve
SUBTYPE OF (b_spline_curve);

weights_data : LIST [2:?] OF REAL;
DERIVE

weights : ARRAY [0:upper_index_on_control_points] OF REAL := list_to_array(weights_data, 0, upper_index_on_control_points);
WHERE

wr1:
SIZEOF(weights_data) = SIZEOF(SELF\b_spline_curve.control_points_list);

wr2:
curve_weights_positive(SELF);
END_ENTITY;




ENTITY rational_b_spline_surface
SUBTYPE OF (b_spline_surface);

weights_data : LIST [2:?] OF LIST [2:?] OF REAL;
DERIVE

weights : ARRAY [0:u_upper] OF ARRAY [0:v_upper] OF REAL := make_array_of_array(weights_data, 0, u_upper, 0, v_upper);
WHERE

wr1:
(SIZEOF(weights_data) = SIZEOF(SELF\b_spline_surface.control_points_list)) AND (SIZEOF(weights_data[1]) = SIZEOF(SELF\b_spline_surface.control_points_list[1]));

wr2:
surface_weights_positive(SELF);
END_ENTITY;




ENTITY rectangular_composite_surface
SUBTYPE OF (bounded_surface);

segments : LIST [1:?] OF LIST [1:?] OF surface_patch;
DERIVE

n_u : INTEGER := SIZEOF(segments);

n_v : INTEGER := SIZEOF(segments[1]);
WHERE

wr1:
[] = 
QUERY (s <* segments| (n_v <> SIZEOF(s)));

wr2:
constraints_rectangular_composite_surface(SELF);
END_ENTITY;




ENTITY rectangular_trimmed_surface
SUBTYPE OF (bounded_surface);

basis_surface : surface;

u1 : parameter_value;

u2 : parameter_value;

v1 : parameter_value;

v2 : parameter_value;

usense : BOOLEAN;

vsense : BOOLEAN;
WHERE

wr1:
u1 <> u2;

wr2:
v1 <> v2;

wr3:
(('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ELEMENTARY_SURFACE' IN TYPEOF(basis_surface)) AND NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PLANE' IN TYPEOF(basis_surface)) OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SURFACE_OF_REVOLUTION' IN TYPEOF(basis_surface))) OR (usense = (u2 > u1));

wr4:
(('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SPHERICAL_SURFACE' IN TYPEOF(basis_surface)) OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.TOROIDAL_SURFACE' IN TYPEOF(basis_surface))) OR (vsense = (v2 > v1));
END_ENTITY;




ENTITY reparametrised_composite_curve_segment
SUBTYPE OF (composite_curve_segment);

param_length : parameter_value;
WHERE

wr1:
param_length > 0;
END_ENTITY;




ENTITY representation;

name : label;

items : SET [1:?] OF representation_item;

context_of_items : representation_context;
END_ENTITY;




ENTITY representation_context;

context_identifier : identifier;

context_type : text;
INVERSE

representations_in_context : SET [1:?] OF representation FOR context_of_items;
END_ENTITY;




ENTITY representation_item;

name : label;
WHERE

wr1:
SIZEOF(using_representations(SELF)) > 0;
END_ENTITY;




ENTITY representation_map;

mapping_origin : representation_item;

mapped_representation : representation;
INVERSE

map_usage : SET [1:?] OF mapped_item FOR mapping_source;
WHERE

wr1:
item_in_context(SELF.mapping_origin, SELF.mapped_representation.context_of_items);
END_ENTITY;




ENTITY representation_relationship;

name : label;

description : text;

rep_1 : representation;

rep_2 : representation;
END_ENTITY;




ENTITY representation_relationship_with_transformation
SUBTYPE OF (representation_relationship);

transformation_operator : transformation;
WHERE

wr1:
SELF\representation_relationship.rep_1.context_of_items :<>: SELF\representation_relationship.rep_2.context_of_items;
END_ENTITY;




ENTITY requirement_allocation_group
SUBTYPE OF (group, property_definition_relationship);
WHERE

wr1:
SIZEOF(
QUERY (aga <* 
QUERY (ga <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GROUP_ASSIGNMENT.ASSIGNED_GROUP')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_GROUP_ASSIGNMENT' IN TYPEOF(ga)))| SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_FORMATION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CONFIGURATION_ITEM') ] * TYPEOF(aga.items)))) = 1;

wr2:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REQUIREMENTS_PROPERTY' IN TYPEOF(SELF\property_definition_relationship.relating_property_definition);

wr3:
NOT (SELF\property_definition_relationship.name = 'derived from operation') OR (SELF\property_definition_relationship.relating_property_definition :=: SELF\property_definition_relationship.related_property_definition);
END_ENTITY;




ENTITY requirements_property
SUBTYPE OF (property_definition);
WHERE

wr1:
SIZEOF(
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')| (pdr.name = 'requirements property composition'))) <= 1;

wr2:
SIZEOF(
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'requirements description'))) = 1))) <= 1;

wr3:
SIZEOF(
QUERY (dr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DOCUMENT_REFERENCE.ITEMS')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EE_SPECIFICATION' IN TYPEOF(dr.assigned_document)))) >= 1;

wr4:
NOT (SELF.description IN [ 'constraint', 'part based constraint' ]) OR (SIZEOF(
QUERY (dc <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')| (pdr.name = 'design constraint'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'RULE_DEFINITION' IN TYPEOF(dc.relating_property_definition.definition)))) = 1);

wr5:
NOT (SELF.description = 'part based constraint') OR (SIZEOF(
QUERY (cp <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')| (pdr.name = 'constraining part'))| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP' IN TYPEOF(cp.relating_property_definition.definition)) AND (cp.relating_property_definition.definition.name = 'constraining part')) AND (cp.relating_property_definition.definition.related_product_definition.frame_of_reference.name = 'design requirement'))) = 1);

wr6:
NOT (SELF.description = 'interface requirement') OR (SIZEOF(
QUERY (itnha <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')| (pdr.name = 'interface to next higher assembly'))| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION' IN TYPEOF(itnha.relating_property_definition.definition)) AND (itnha.relating_property_definition.definition.frame_of_reference.name = 'design requirement')) AND (SIZEOF(
QUERY (hai <* 
QUERY (pdr <* USEDIN(itnha.relating_property_definition.definition, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATING_PRODUCT_DEFINITION')| (pdr.name = 'higher assembly interface'))| (SIZEOF(
QUERY (pdr <* USEDIN(hai, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SPECIFIED_HIGHER_USAGE_OCCURRENCE' IN TYPEOF(pdr)))) = 1))) = 1))) = 1);
END_ENTITY;




ENTITY requirements_property_group
SUBTYPE OF (requirements_property, group);
WHERE

wr1:
SIZEOF(
QUERY (rpc <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATING_PROPERTY_DEFINITION')| (pdr.name = 'requirements property composition'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REQUIREMENTS_PROPERTY' IN TYPEOF(rpc.related_property_definition)))) >= 1;
END_ENTITY;




ENTITY revolved_area_solid
SUBTYPE OF (swept_area_solid);

axis : axis1_placement;

angle : plane_angle_measure;
DERIVE

axis_line : line := dummy_gri || curve() || line(SELF\surface_of_revolution.axis_position.location, dummy_gri || vector(SELF\surface_of_revolution.axis_position.z, 1));
END_ENTITY;




ENTITY right_angular_wedge
SUBTYPE OF (geometric_representation_item);

position : axis2_placement_3d;

x : positive_length_measure;

y : positive_length_measure;

z : positive_length_measure;

ltx : length_measure;
WHERE

wr1:
(0 <= ltx) AND (ltx < x);
END_ENTITY;




ENTITY right_circular_cone
SUBTYPE OF (geometric_representation_item);

position : axis1_placement;

height : positive_length_measure;

radius : length_measure;

semi_angle : plane_angle_measure;
WHERE

wr1:
radius >= 0;
END_ENTITY;




ENTITY right_circular_cylinder
SUBTYPE OF (geometric_representation_item);

position : axis1_placement;

height : positive_length_measure;

radius : positive_length_measure;
END_ENTITY;




ENTITY routed_printed_component
SUBTYPE OF (printed_component);
END_ENTITY;




ENTITY rule_action
SUBTYPE OF (action);
WHERE

wr1:
SIZEOF(
QUERY (aaa <* 
QUERY (aa <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ACTION_ASSIGNMENT.ASSIGNED_ACTION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_ACTION_ASSIGNMENT' IN TYPEOF(aa)))| (SIZEOF(
QUERY (it <* aaa.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'RULE_DEFINITION' IN TYPEOF(it)))) = 1))) = 1;

wr2:
SIZEOF(
QUERY (adta <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DATE_AND_TIME_ASSIGNMENT.ITEMS')| (adta.role.name = 'participant date and time'))) + SIZEOF(
QUERY (ada <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DATE_ASSIGNMENT.ITEMS')| (ada.role.name = 'participant date'))) = 1;

wr3:
NOT (SELF.name = 'rule justification') OR (SIZEOF(
QUERY (ja <* 
QUERY (ar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ACTION_RELATIONSHIP.RELATED_ACTION')| (ar.name = 'justified action'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'RULE_ACTION' IN TYPEOF(ja.relating_action)))) = 1);

wr4:
NOT (SELF.name = 'rule modification') OR (SIZEOF(
QUERY (mr <* 
QUERY (ar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ACTION_RELATIONSHIP.RELATED_ACTION')| (ar.name = 'modification rationale'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'RULE_ACTION' IN TYPEOF(mr.relating_action)) AND (mr.relating_action.name = 'rule change request'))) = 1);

wr5:
NOT (SELF.name = 'rule replacement from') OR (SIZEOF(
QUERY (rrfa <* 
QUERY (aa <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ACTION_ASSIGNMENT.ASSIGNED_ACTION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'RULE_REPLACEMENT_FROM_ASSIGNMENT' IN TYPEOF(aa)))| (SIZEOF(
QUERY (it <* rrfa.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'RULE_DEFINITION' IN TYPEOF(it)))) = 1))) = 1);

wr6:
NOT (SELF.name = 'rule replacement to') OR (SIZEOF(
QUERY (rrta <* 
QUERY (aa <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ACTION_ASSIGNMENT.ASSIGNED_ACTION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'RULE_REPLACEMENT_TO_ASSIGNMENT' IN TYPEOF(aa)))| (SIZEOF(
QUERY (it <* rrta.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'RULE_DEFINITION' IN TYPEOF(it)))) = 1))) = 1);
END_ENTITY;




ENTITY rule_definition
SUBTYPE OF (characterized_object, externally_defined_item);
WHERE

wr1:
SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DOCUMENT_REFERENCE.ITEMS')) + SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_ORGANIZATION_ASSIGNMENT.ITEMS')) <= 1;

wr2:
SIZEOF(
QUERY (aaa <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_ACTION_ASSIGNMENT.ITEMS')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'RULE_ACTION' IN TYPEOF(aaa.assigned_action)))) >= 1;

wr3:
SIZEOF(
QUERY (esr <* USEDIN(SELF.source, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNAL_SOURCE_RELATIONSHIP.RELATING_SOURCE')| (esr.name = 'revision'))) = 1;
END_ENTITY;




ENTITY rule_function_definition
SUBTYPE OF (representation);
WHERE

wr1:
SIZEOF(
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM' IN TYPEOF(it)))) >= 1;

wr2:
SIZEOF(
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MODEL_PARAMETER' IN TYPEOF(it)))) = 1;

wr3:
SIZEOF(
QUERY (adf <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DOCUMENT_REFERENCE.ITEMS')| (adf\document_reference.assigned_document.kind.product_data_type = 'reference document') AND (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EE_SPECIFICATION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DOCUMENT') ] * TYPEOF(adf\document_reference.assigned_document)) >= 1))) = 1;

wr4:
SIZEOF(
QUERY (adf <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DOCUMENT_REFERENCE.ITEMS')| (adf\document_reference.assigned_document.kind.product_data_type = 'source code') AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EE_SPECIFICATION' IN TYPEOF(adf\document_reference.assigned_document)))) = 1;
END_ENTITY;




ENTITY rule_replacement_from_assignment
SUBTYPE OF (action_assignment);

items : SET [1:?] OF replacement_from_item;
WHERE

wr1:
SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ACTION_RELATIONSHIP.' + 'RELATING_ACTION')) = 1;
END_ENTITY;




ENTITY rule_replacement_from_request_assignment
SUBTYPE OF (action_request_assignment);

items : SET [1:?] OF replacement_from_item;
END_ENTITY;




ENTITY rule_replacement_to_assignment
SUBTYPE OF (action_assignment);

items : SET [1:?] OF replacement_to_item;
END_ENTITY;




ENTITY rule_replacement_to_request_assignment
SUBTYPE OF (action_request_assignment);

items : SET [1:?] OF replacement_to_item;
END_ENTITY;




ENTITY rule_set
SUBTYPE OF (group);
WHERE

wr1:
(SIZEOF(
QUERY (aga <* 
QUERY (ga <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GROUP_ASSIGNMENT.ASSIGNED_GROUP')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_GROUP_ASSIGNMENT' IN TYPEOF(ga)))| (SIZEOF(
QUERY (rd <* 
QUERY (it <* aga.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'RULE_DEFINITION' IN TYPEOF(it)))| (SIZEOF(
QUERY (pd <* USEDIN(rd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'rule priority'))) >= 1))) >= 1))) >= 1))) >= 1) OR (SIZEOF(
QUERY (rsge <* 
QUERY (gr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GROUP_RELATIONSHIP.RELATING_GROUP')| (gr.name = 'rule set group element'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'RULE_SET' IN TYPEOF(rsge.related_group)))) >= 2);
END_ENTITY;




ENTITY runout_zone_definition
SUBTYPE OF (tolerance_zone_definition);

orientation : runout_zone_orientation;
END_ENTITY;




ENTITY runout_zone_orientation;

angle : measure_with_unit;
END_ENTITY;




ENTITY runout_zone_orientation_reference_direction
SUBTYPE OF (runout_zone_orientation);

orientation_defining_relationship : shape_aspect_relationship;
END_ENTITY;




ENTITY seam_curve
SUBTYPE OF (surface_curve);
WHERE

wr1:
SIZEOF(SELF\surface_curve.associated_geometry) = 2;

wr2:
associated_surface(SELF\surface_curve.associated_geometry[1]) = associated_surface(SELF\surface_curve.associated_geometry[2]);

wr3:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PCURVE' IN TYPEOF(SELF\surface_curve.associated_geometry[1]);

wr4:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PCURVE' IN TYPEOF(SELF\surface_curve.associated_geometry[2]);
END_ENTITY;




ENTITY security_classification;

name : label;

purpose : text;

security_level : security_classification_level;
END_ENTITY;




ENTITY security_classification_assignment
ABSTRACT SUPERTYPE;

assigned_security_classification : security_classification;
END_ENTITY;




ENTITY security_classification_level;

name : label;
END_ENTITY;




ENTITY sequential_laminate_passage_based_fabrication_joint
SUBTYPE OF (shape_aspect);
END_ENTITY;




ENTITY serial_numbered_effectivity
SUBTYPE OF (effectivity);

effectivity_start_id : identifier;

effectivity_end_id : OPTIONAL identifier;
END_ENTITY;




ENTITY shape_aspect;

name : label;

description : text;

of_shape : product_definition_shape;

product_definitional : LOGICAL;
END_ENTITY;




ENTITY shape_aspect_deriving_relationship
SUBTYPE OF (shape_aspect_relationship);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.DERIVED_SHAPE_ASPECT' IN TYPEOF(SELF\shape_aspect_relationship.relating_shape_aspect);
END_ENTITY;




ENTITY shape_aspect_relationship;

name : label;

description : text;

relating_shape_aspect : shape_aspect;

related_shape_aspect : shape_aspect;
END_ENTITY;




ENTITY shape_definition_representation
SUBTYPE OF (property_definition_representation);
WHERE

wr1:
('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHAPE_DEFINITION' IN TYPEOF(SELF.definition.definition)) OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PRODUCT_DEFINITION_SHAPE' IN TYPEOF(SELF.definition));

wr2:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHAPE_REPRESENTATION' IN TYPEOF(SELF.used_representation);
END_ENTITY;




ENTITY shape_dimension_representation
SUBTYPE OF (shape_representation);
WHERE

wr1:
SIZEOF(
QUERY (temp <* SELF.items| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MEASURE_REPRESENTATION_ITEM' IN TYPEOF(temp)))) = 0;

wr2:
SIZEOF(SELF.items) <= 2;

wr3:
SIZEOF(
QUERY (pos_mri <* 
QUERY (real_mri <* SELF.items| ('REAL' IN TYPEOF(real_mri\measure_with_unit.value_component)))| NOT (pos_mri\measure_with_unit.value_component > 0))) = 0;
END_ENTITY;




ENTITY shape_modification
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SIZEOF(
QUERY (dim <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'design intent modification'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_FEATURE' IN TYPEOF(dim.relating_shape_aspect)))) = 1;

wr2:
(SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REQUIREMENTS_PROPERTY' IN TYPEOF(pd)) AND (pd.description = 'modification causal'))) = 1) OR (SIZEOF(
QUERY (mcf <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'modification causal feature'))| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_SHAPE_ASPECT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_INTERFACE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_FEATURE') ] * TYPEOF(mcf.relating_shape_aspect)) = 1) OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM' IN TYPEOF(mcf.relating_shape_aspect.of_shape.definition)))) = 1);

wr3:
NOT (SELF.description IN [ 'electrical isolation removal', 'thermal isolation removal' ]) OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REQUIREMENTS_PROPERTY' IN TYPEOF(pd)) AND (pd.description = 'spacing requirement'))) = 1);

wr4:
NOT (SELF.description IN [ 'electrical isolation removal', 'thermal isolation removal' ]) OR (SIZEOF(
QUERY (di <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'design intent'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_FEATURE' IN TYPEOF(di.relating_shape_aspect)) AND (di.relating_shape_aspect.description IN [ 'conductive filled area', 'connected filled area' ]))) = 1);

wr5:
NOT (SELF.description = 'thermal isolation removal') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REQUIREMENTS_PROPERTY' IN TYPEOF(pd)) AND (pd.description = 'angular orientation requirement'))) = 1);

wr6:
NOT (SELF.description = 'thermal isolation removal') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REQUIREMENTS_PROPERTY' IN TYPEOF(pd)) AND (pd.description = 'effective current capacity requirement'))) = 1);
END_ENTITY;




ENTITY shape_representation
SUBTYPE OF (representation);
END_ENTITY;




ENTITY shape_representation_relationship
SUBTYPE OF (representation_relationship);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHAPE_REPRESENTATION' IN TYPEOF(SELF\representation_relationship.rep_1) + TYPEOF(SELF\representation_relationship.rep_2);
END_ENTITY;




ENTITY shell_based_2d_wireframe_shape_representation
SUBTYPE OF (shape_representation);
WHERE

wr1:
SIZEOF(
QUERY (it <* SELF\representation.items| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHELL_BASED_WIREFRAME_MODEL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MAPPED_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'AXIS2_PLACEMENT_2D') ] * TYPEOF(it)) = 1))) = 0;

wr2:
SIZEOF(
QUERY (it <* SELF\representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHELL_BASED_WIREFRAME_MODEL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MAPPED_ITEM') ] * TYPEOF(it)) = 1))) >= 1;

wr3:
SIZEOF(
QUERY (sbwm <* 
QUERY (it <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHELL_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (ws <* 
QUERY (sb <* sbwm\shell_based_wireframe_model.sbwm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'WIRE_SHELL' IN TYPEOF(sb)))| NOT (SIZEOF(
QUERY (eloop <* 
QUERY (wsb <* ws\wire_shell.wire_shell_extent| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EDGE_LOOP' IN TYPEOF(wsb)))| NOT (SIZEOF(
QUERY (el <* eloop\path.edge_list| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EDGE_CURVE' IN TYPEOF(el.edge_element)))) = 0))) = 0))) = 0))) = 0;

wr4:
SIZEOF(
QUERY (sbwm <* 
QUERY (it <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHELL_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (ws <* 
QUERY (sb <* sbwm\shell_based_wireframe_model.sbwm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'WIRE_SHELL' IN TYPEOF(sb)))| NOT (SIZEOF(
QUERY (eloop <* 
QUERY (wsb <* ws\wire_shell.wire_shell_extent| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EDGE_LOOP' IN TYPEOF(wsb)))| NOT (SIZEOF(
QUERY (pline_el <* 
QUERY (el <* eloop\path.edge_list| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'POLYLINE' IN TYPEOF(el.edge_element\edge_curve.edge_geometry)))| NOT (SIZEOF(pline_el.edge_element\edge_curve.edge_geometry\polyline.points) > 2))) = 0))) = 0))) = 0))) = 0;

wr5:
SIZEOF(
QUERY (sbwm <* 
QUERY (it <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHELL_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (ws <* 
QUERY (sb <* sbwm\shell_based_wireframe_model.sbwm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'WIRE_SHELL' IN TYPEOF(sb)))| NOT (SIZEOF(
QUERY (eloop <* 
QUERY (wsb <* ws\wire_shell.wire_shell_extent| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EDGE_LOOP' IN TYPEOF(wsb)))| NOT (SIZEOF(
QUERY (el <* eloop\path.edge_list| NOT valid_2d_wireframe_edge_curve(el.edge_element\edge_curve.edge_geometry, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN'))) = 0))) = 0))) = 0))) = 0;

wr6:
SIZEOF(
QUERY (sbwm <* 
QUERY (it <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHELL_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (ws <* 
QUERY (sb <* sbwm\shell_based_wireframe_model.sbwm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'WIRE_SHELL' IN TYPEOF(sb)))| NOT (SIZEOF(
QUERY (eloop <* 
QUERY (wsb <* ws\wire_shell.wire_shell_extent| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EDGE_LOOP' IN TYPEOF(wsb)))| NOT (SIZEOF(
QUERY (el <* eloop\path.edge_list| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'VERTEX_POINT' IN TYPEOF(el.edge_element.edge_start)) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'VERTEX_POINT' IN TYPEOF(el.edge_element.edge_end))))) = 0))) = 0))) = 0))) = 0;

wr7:
SIZEOF(
QUERY (sbwm <* 
QUERY (it <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHELL_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (ws <* 
QUERY (sb <* sbwm\shell_based_wireframe_model.sbwm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'WIRE_SHELL' IN TYPEOF(sb)))| NOT (SIZEOF(
QUERY (eloop <* 
QUERY (wsb <* ws\wire_shell.wire_shell_extent| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EDGE_LOOP' IN TYPEOF(wsb)))| NOT (SIZEOF(
QUERY (el <* eloop\path.edge_list| NOT (valid_wireframe_vertex_point(el.edge_element.edge_start\vertex_point.vertex_geometry, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN') AND valid_wireframe_vertex_point(el.edge_element.edge_end\vertex_point.vertex_geometry, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN')))) = 0))) = 0))) = 0))) = 0;

wr8:
SIZEOF(
QUERY (sbwm <* 
QUERY (it <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHELL_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (ws <* 
QUERY (sb <* sbwm\shell_based_wireframe_model.sbwm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'WIRE_SHELL' IN TYPEOF(sb)))| NOT (SIZEOF(
QUERY (eloop <* 
QUERY (wsb <* ws\wire_shell.wire_shell_extent| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EDGE_LOOP' IN TYPEOF(wsb)))| NOT (SIZEOF(
QUERY (con_edges <* 
QUERY (el <* eloop\path.edge_list| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CONIC' IN TYPEOF(el.edge_element\edge_curve.edge_geometry)))| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'AXIS2_PLACEMENT_2D' IN TYPEOF(con_edges.edge_element\edge_curve.edge_geometry\conic.position)))) = 0))) = 0))) = 0))) = 0;

wr9:
SIZEOF(
QUERY (sbwm <* 
QUERY (it <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHELL_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (ws <* 
QUERY (sb <* sbwm\shell_based_wireframe_model.sbwm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'WIRE_SHELL' IN TYPEOF(sb)))| NOT (SIZEOF(
QUERY (vloop <* 
QUERY (wsb <* ws\wire_shell.wire_shell_extent| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'VERTEX_LOOP' IN TYPEOF(wsb)))| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'VERTEX_POINT' IN TYPEOF(vloop\vertex_loop.loop_vertex)))) = 0))) = 0))) = 0;

wr10:
SIZEOF(
QUERY (sbwm <* 
QUERY (it <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHELL_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (ws <* 
QUERY (sb <* sbwm\shell_based_wireframe_model.sbwm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'WIRE_SHELL' IN TYPEOF(sb)))| NOT (SIZEOF(
QUERY (vloop <* 
QUERY (wsb <* ws\wire_shell.wire_shell_extent| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'VERTEX_LOOP' IN TYPEOF(wsb)))| NOT valid_wireframe_vertex_point(vloop\vertex_loop.loop_vertex\vertex_point.vertex_geometry, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN'))) = 0))) = 0))) = 0;

wr11:
SIZEOF(
QUERY (sbwm <* 
QUERY (it <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHELL_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (vs <* 
QUERY (sb <* sbwm\shell_based_wireframe_model.sbwm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'VERTEX_SHELL' IN TYPEOF(sb)))| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'VERTEX_POINT' IN TYPEOF(vs\vertex_shell.vertex_shell_extent.loop_vertex)))) = 0))) = 0;

wr12:
SIZEOF(
QUERY (sbwm <* 
QUERY (it <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHELL_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (vs <* 
QUERY (sb <* sbwm\shell_based_wireframe_model.sbwm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'VERTEX_SHELL' IN TYPEOF(sb)))| NOT valid_wireframe_vertex_point(vs\vertex_shell.vertex_shell_extent.loop_vertex\vertex_point.vertex_geometry, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN'))) = 0))) = 0;

wr13:
SIZEOF(
QUERY (mi <* 
QUERY (it <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MAPPED_ITEM' IN TYPEOF(it)))| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHELL_BASED_2D_WIREFRAME_SHAPE_REPRESENTATION' IN TYPEOF(mi\mapped_item.mapping_source.mapped_representation)))) = 0;

wr14:
SELF.context_of_items\geometric_representation_context.coordinate_space_dimension = 2;
END_ENTITY;




ENTITY shell_based_surface_model
SUBTYPE OF (geometric_representation_item);

sbsm_boundary : SET [1:?] OF shell;
WHERE

wr1:
constraints_geometry_shell_based_surface_model(SELF);
END_ENTITY;




ENTITY shell_based_wireframe_model
SUBTYPE OF (geometric_representation_item);

sbwm_boundary : SET [1:?] OF shell;
WHERE

wr1:
constraints_geometry_shell_based_wireframe_model(SELF);
END_ENTITY;




ENTITY shell_based_wireframe_shape_representation
SUBTYPE OF (shape_representation);
WHERE

wr1:
SIZEOF(
QUERY (it <* SELF.items| NOT (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_WIREFRAME_MODEL', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AXIS2_PLACEMENT_3D' ] * TYPEOF(it)) = 1))) = 0;

wr2:
SIZEOF(
QUERY (it <* SELF.items| (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_WIREFRAME_MODEL', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' ] * TYPEOF(it)) = 1))) >= 1;

wr3:
SIZEOF(
QUERY (sbwm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (ws <* 
QUERY (sb <* sbwm\shell_based_wireframe_model.sbwm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.WIRE_SHELL' IN TYPEOF(sb)))| NOT (SIZEOF(
QUERY (eloop <* 
QUERY (wsb <* ws\wire_shell.wire_shell_extent| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_LOOP' IN TYPEOF(wsb)))| NOT (SIZEOF(
QUERY (el <* eloop\path.edge_list| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_CURVE' IN TYPEOF(el.edge_element)))) = 0))) = 0))) = 0))) = 0;

wr4:
SIZEOF(
QUERY (sbwm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (ws <* 
QUERY (sb <* sbwm\shell_based_wireframe_model.sbwm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.WIRE_SHELL' IN TYPEOF(sb)))| NOT (SIZEOF(
QUERY (eloop <* 
QUERY (wsb <* ws\wire_shell.wire_shell_extent| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_LOOP' IN TYPEOF(wsb)))| NOT (SIZEOF(
QUERY (pline_el <* 
QUERY (el <* eloop\path.edge_list| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POLYLINE' IN TYPEOF(el.edge_element\edge_curve.edge_geometry)))| NOT (SIZEOF(pline_el.edge_element\edge_curve.edge_geometry\polyline.points) > 2))) = 0))) = 0))) = 0))) = 0;

wr5:
SIZEOF(
QUERY (sbwm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (ws <* 
QUERY (sb <* sbwm\shell_based_wireframe_model.sbwm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.WIRE_SHELL' IN TYPEOF(sb)))| NOT (SIZEOF(
QUERY (eloop <* 
QUERY (wsb <* ws\wire_shell.wire_shell_extent| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_LOOP' IN TYPEOF(wsb)))| NOT (SIZEOF(
QUERY (el <* eloop\path.edge_list| NOT valid_wireframe_edge_curve(el.edge_element\edge_curve.edge_geometry))) = 0))) = 0))) = 0))) = 0;

wr6:
SIZEOF(
QUERY (sbwm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (ws <* 
QUERY (sb <* sbwm\shell_based_wireframe_model.sbwm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.WIRE_SHELL' IN TYPEOF(sb)))| NOT (SIZEOF(
QUERY (eloop <* 
QUERY (wsb <* ws\wire_shell.wire_shell_extent| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_LOOP' IN TYPEOF(wsb)))| NOT (SIZEOF(
QUERY (el <* eloop\path.edge_list| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_POINT' IN TYPEOF(el.edge_element.edge_start)) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_POINT' IN TYPEOF(el.edge_element.edge_end))))) = 0))) = 0))) = 0))) = 0;

wr7:
SIZEOF(
QUERY (sbwm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (ws <* 
QUERY (sb <* sbwm\shell_based_wireframe_model.sbwm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.WIRE_SHELL' IN TYPEOF(sb)))| NOT (SIZEOF(
QUERY (eloop <* 
QUERY (wsb <* ws\wire_shell.wire_shell_extent| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_LOOP' IN TYPEOF(wsb)))| NOT (SIZEOF(
QUERY (el <* eloop\path.edge_list| NOT (valid_wireframe_vertex_point(el.edge_element.edge_start\vertex_point.vertex_geometry, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN') AND valid_wireframe_vertex_point(el.edge_element.edge_end\vertex_point.vertex_geometry, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN')))) = 0))) = 0))) = 0))) = 0;

wr8:
SIZEOF(
QUERY (sbwm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (ws <* 
QUERY (sb <* sbwm\shell_based_wireframe_model.sbwm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.WIRE_SHELL' IN TYPEOF(sb)))| NOT (SIZEOF(
QUERY (eloop <* 
QUERY (wsb <* ws\wire_shell.wire_shell_extent| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE_LOOP' IN TYPEOF(wsb)))| NOT (SIZEOF(
QUERY (con_edges <* 
QUERY (el <* eloop\path.edge_list| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CONIC' IN TYPEOF(el.edge_element\edge_curve.edge_geometry)))| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AXIS2_PLACEMENT_3D' IN TYPEOF(con_edges.edge_element\edge_curve.edge_geometry\conic.position)))) = 0))) = 0))) = 0))) = 0;

wr9:
SIZEOF(
QUERY (sbwm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (ws <* 
QUERY (sb <* sbwm\shell_based_wireframe_model.sbwm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.WIRE_SHELL' IN TYPEOF(sb)))| NOT (SIZEOF(
QUERY (vloop <* 
QUERY (wsb <* ws\wire_shell.wire_shell_extent| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_LOOP' IN TYPEOF(wsb)))| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_POINT' IN TYPEOF(vloop\vertex_loop.loop_vertex)))) = 0))) = 0))) = 0;

wr10:
SIZEOF(
QUERY (sbwm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (ws <* 
QUERY (sb <* sbwm\shell_based_wireframe_model.sbwm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.WIRE_SHELL' IN TYPEOF(sb)))| NOT (SIZEOF(
QUERY (vloop <* 
QUERY (wsb <* ws\wire_shell.wire_shell_extent| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_LOOP' IN TYPEOF(wsb)))| NOT valid_wireframe_vertex_point(vloop\vertex_loop.loop_vertex\vertex_point.vertex_geometry, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN'))) = 0))) = 0))) = 0;

wr11:
SIZEOF(
QUERY (sbwm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (vs <* 
QUERY (sb <* sbwm\shell_based_wireframe_model.sbwm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_SHELL' IN TYPEOF(sb)))| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_POINT' IN TYPEOF(vs\vertex_shell.vertex_shell_extent.loop_vertex)))) = 0))) = 0;

wr12:
SIZEOF(
QUERY (sbwm <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL_BASED_WIREFRAME_MODEL' IN TYPEOF(it)))| NOT (SIZEOF(
QUERY (vs <* 
QUERY (sb <* sbwm\shell_based_wireframe_model.sbwm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_SHELL' IN TYPEOF(sb)))| NOT valid_wireframe_vertex_point(vs\vertex_shell.vertex_shell_extent.loop_vertex\vertex_point.vertex_geometry, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN'))) = 0))) = 0;

wr13:
SIZEOF(
QUERY (mi <* 
QUERY (it <* SELF.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' IN TYPEOF(it)))| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHELL_BASED_WIREFRAME_SHAPE_REPRESENTATION' IN TYPEOF(mi\mapped_item.mapping_source.mapped_representation)))) = 0;

wr14:
SELF.context_of_items\geometric_representation_context.coordinate_space_dimension = 3;
END_ENTITY;




ENTITY si_unit
SUBTYPE OF (named_unit);

prefix : OPTIONAL si_prefix;

name : si_unit_name;
DERIVE

dimensions : dimensional_exponents := dimensions_for_si_unit(SELF.name);
END_ENTITY;




ENTITY signal
SUBTYPE OF (characterized_object, property_definition);
WHERE

wr1:
SIZEOF(
QUERY (aca <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_CLASSIFICATION_ASSIGNMENT.ITEMS')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SIGNAL_CATEGORY' IN TYPEOF(aca.assigned_group)))) >= 1;

wr2:
('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNAL_DEFINITION' IN TYPEOF(SELF)) XOR (SIZEOF(
QUERY (ada <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DOCUMENT_REFERENCE.ITEMS')| (SIZEOF(
QUERY (duc <* USEDIN(ada.assigned_document, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DOCUMENT_USAGE_CONSTRAINT.SOURCE')| (duc.subject_element = 'signal category'))) = 1))) = 1);

wr3:
SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DOCUMENT_REFERENCE.ITEMS')) = 1;
END_ENTITY;




ENTITY signal_category
SUBTYPE OF (group, externally_defined_item);
WHERE

wr1:
SELF\group.description IN [ 'signal characteristic category', 'signal property category' ];
END_ENTITY;




ENTITY solid_angle_measure_with_unit
SUBTYPE OF (measure_with_unit);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SOLID_ANGLE_UNIT' IN TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY;




ENTITY solid_angle_unit
SUBTYPE OF (named_unit);
WHERE

wr1:
((((((SELF\named_unit.dimensions.length_exponent = 0) AND (SELF\named_unit.dimensions.mass_exponent = 0)) AND (SELF\named_unit.dimensions.time_exponent = 0)) AND (SELF\named_unit.dimensions.electric_current_exponent = 0)) AND (SELF\named_unit.dimensions.thermodynamic_temperature_exponent = 0)) AND (SELF\named_unit.dimensions.amount_of_substance_exponent = 0)) AND (SELF\named_unit.dimensions.luminous_intensity_exponent = 0);
END_ENTITY;




ENTITY solid_curve_font
SUBTYPE OF (pre_defined_curve_font);
END_ENTITY;




ENTITY solid_model
SUPERTYPE OF (ONEOF(csg_solid, manifold_solid_brep, swept_area_solid, solid_replica))
SUBTYPE OF (geometric_representation_item);
END_ENTITY;




ENTITY solid_replica
SUBTYPE OF (solid_model);

parent_solid : solid_model;

transformation : cartesian_transformation_operator_3d;
WHERE

wr1:
acyclic_solid_replica(SELF, parent_solid);
END_ENTITY;




ENTITY specified_higher_usage_occurrence
SUBTYPE OF (assembly_component_usage);

upper_usage : assembly_component_usage;

next_usage : next_assembly_usage_occurrence;
UNIQUE

ur1 : upper_usage, next_usage;
WHERE

wr1:
SELF :<>: upper_usage;

wr2:
SELF\product_definition_relationship.relating_product_definition :=: upper_usage.relating_product_definition;

wr3:
SELF\product_definition_relationship.related_product_definition :=: next_usage.related_product_definition;

wr4:
upper_usage.related_product_definition :=: next_usage.relating_product_definition;

wr5:
NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PROMISSORY_USAGE_OCCURRENCE' IN TYPEOF(upper_usage));
END_ENTITY;




ENTITY sphere
SUBTYPE OF (geometric_representation_item);

radius : positive_length_measure;

centre : point;
END_ENTITY;




ENTITY spherical_surface
SUBTYPE OF (elementary_surface);

radius : positive_length_measure;
END_ENTITY;




ENTITY standard_uncertainty
SUPERTYPE OF (expanded_uncertainty)
SUBTYPE OF (uncertainty_qualifier);

uncertainty_value : REAL;
END_ENTITY;




ENTITY start_request
SUBTYPE OF (action_request_assignment);

items : SET [1:?] OF start_request_item;
END_ENTITY;




ENTITY start_work
SUBTYPE OF (action_assignment);

items : SET [1:?] OF work_item;
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DIRECTED_ACTION' IN TYPEOF(SELF.assigned_action);
END_ENTITY;




ENTITY statistical_dimensional_location
SUBTYPE OF (dimensional_location);
END_ENTITY;




ENTITY statistical_dimensional_size
SUBTYPE OF (dimensional_size_property);
END_ENTITY;




ENTITY statistical_geometric_tolerance
SUBTYPE OF (physical_unit_geometric_tolerance);
END_ENTITY;




ENTITY stratum
SUBTYPE OF (product_definition);
UNIQUE

ur1 : id;
WHERE

wr1:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (tu <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')| (pdr.name = 'technology usage'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_TECHNOLOGY' IN TYPEOF(tu.relating_property_definition.definition)))) = 1))) = 1;

wr2:
(SIZEOF(
QUERY (ada <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'APPLIED_DOCUMENT_REFERENCE.ITEMS')| (SIZEOF(
QUERY (duc <* USEDIN(ada.assigned_document, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DOCUMENT_USAGE_CONSTRAINT.SOURCE')| (duc.subject_element = 'attachment region size'))) = 1))) <= 1) OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (tu <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')| (pdr.name = 'stratum usage'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNAL_DEFINITION' IN TYPEOF(tu.relating_property_definition)))) = 1))) <= 1);

wr3:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sr_pdr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_REPRESENTATION' IN TYPEOF(pdr.used_representation)))| (sr_pdr.used_representation.name = '3d bound volume shape'))) <= 1))) = 0;

wr4:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sr_pdr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_REPRESENTATION' IN TYPEOF(pdr.used_representation)))| (sr_pdr.used_representation.name = 'planar projected shape'))) <= 1))) = 0;

wr5:
SIZEOF(
QUERY (acu <* 
QUERY (pdr <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_RELATIONSHIP.RELATED_PRODUCT_DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_COMPONENT_USAGE' IN TYPEOF(pdr)))| (acu.name = 'interconnect module stratum assembly relationship'))) >= 1;

wr6:
NOT (SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.' + 'PRODUCTS')| (prpc\product_category.name = 'design layer'))) >= 1) OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (tu <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')| (pdr.name = 'technology usage'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_TECHNOLOGY' IN TYPEOF(tu.relating_property_definition.definition)) AND (tu.relating_property_definition.definition.description = 'design layer'))) = 1))) = 1);

wr7:
NOT (SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.' + 'PRODUCTS')| (prpc\product_category.name = 'design layer'))) >= 1) OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (sa <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT.OF_SHAPE')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAYER_CONNECTION_POINT' IN TYPEOF(sa)))) >= 1))) >= 1);

wr8:
NOT (SIZEOF(
QUERY (prpc <* USEDIN(SELF.formation.of_product, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_RELATED_PRODUCT_CATEGORY.' + 'PRODUCTS')| (prpc\product_category.name = 'documentation layer'))) >= 1) OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (tu <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_RELATIONSHIP.RELATED_PROPERTY_DEFINITION')| (pdr.name = 'technology usage'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_TECHNOLOGY' IN TYPEOF(tu.relating_property_definition.definition)) AND (tu.relating_property_definition.definition.description = 'documentation layer'))) = 1))) = 1);
END_ENTITY;




ENTITY stratum_concept_relationship
SUBTYPE OF (shape_aspect, shape_aspect_relationship);
WHERE

wr1:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REQUIREMENTS_PROPERTY' IN TYPEOF(pd)))) >= 1;

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')) = 1))) = 1;

wr3:
NOT (SELF\shape_aspect_relationship.name = 'dielectric crossover area') OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_FEATURE' IN TYPEOF(SELF.relating_shape_aspect)) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_FEATURE' IN TYPEOF(SELF.related_shape_aspect));

wr4:
NOT (SELF\shape_aspect_relationship.name = 'dielectric crossover area') OR (SIZEOF(
QUERY (rdc <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'resulting dielectric crossover'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_FEATURE' IN TYPEOF(rdc.relating_shape_aspect)))) = 1);

wr5:
(NOT (SELF\shape_aspect_relationship.name = 'stratum feature conductive join') OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND' IN TYPEOF(SELF.relating_shape_aspect))) OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_SHAPE_ASPECT' IN TYPEOF(SELF.relating_shape_aspect)) AND (SELF.relating_shape_aspect.description = 'stratum feature template component');

wr6:
(NOT (SELF\shape_aspect_relationship.name = 'stratum feature conductive join') OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND' IN TYPEOF(SELF.related_shape_aspect))) OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_SHAPE_ASPECT' IN TYPEOF(SELF.related_shape_aspect)) AND (SELF.related_shape_aspect.description = 'stratum feature template component');

wr7:
NOT (SELF\shape_aspect_relationship.name = 'stratum feature conductive join') OR (SIZEOF(
QUERY (fj <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATING_SHAPE_ASPECT')| (sar.name = 'features join'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PLATED_PASSAGE' IN TYPEOF(fj.related_shape_aspect)) AND (fj.related_shape_aspect.description = 'bonded conductive base blind via'))) <= 1);

wr8:
NOT ((SELF\shape_aspect.description = 'physical network supporting stratum feature conductive join') AND (SELF\shape_aspect_relationship.name = 'stratum feature conductive join')) OR (SIZEOF(
QUERY (ji <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'join implementation'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'JOIN_SHAPE_ASPECT' IN TYPEOF(ji.relating_shape_aspect)) AND (ji.relating_shape_aspect.name = 'inter stratum join'))) = 1);
END_ENTITY;




ENTITY stratum_feature
SUPERTYPE OF (fiducial_stratum_feature)
SUBTYPE OF (shape_aspect);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM' IN TYPEOF(SELF.of_shape.definition);

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (SIZEOF(
QUERY (it <* pdr.used_representation.items| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'feature of size')) AND (it.description IN [ 'true', 'false' ]))) = 1))) = 1))) = 0;

wr3:
NOT (SELF.description = 'conductor') OR (SIZEOF(
QUERY (ji <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'join implementation'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'JOIN_SHAPE_ASPECT' IN TYPEOF(ji.relating_shape_aspect)) AND (ji.relating_shape_aspect.name = 'intra stratum join'))) >= 1);

wr4:
NOT (SELF.description = 'connected filled area') OR (SIZEOF(
QUERY (ji <* 
QUERY (sar <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name = 'join implementation'))| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'JOIN_SHAPE_ASPECT' IN TYPEOF(ji.relating_shape_aspect)) AND (ji.relating_shape_aspect.name = 'intra stratum join'))) = 1);
END_ENTITY;




ENTITY stratum_surface
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SELF\shape_aspect.description IN [ 'primary surface', 'secondary surface', 'average surface' ];

wr2:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM' IN TYPEOF(SELF\shape_aspect.of_shape.definition);
END_ENTITY;




ENTITY stratum_technology
SUBTYPE OF (characterized_object);
WHERE

wr1:
SIZEOF(USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MATERIAL_DESIGNATION.DEFINITIONS')) = 1;

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'stiffness class representation'))) <= 1))) = 0;

wr3:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))) = 1))) = 0;

wr4:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (scr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'stratum class representation'))| NOT (SIZEOF(
QUERY (it <* scr.used_representation.items| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'laminate stiffness class')) AND (it.description IN [ 'fluid like', 'conformal coat', 'stiff laminate' ]))) = 1))) = 0))) = 0;

wr5:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT ((3 <= SIZEOF(pcr.used_representation.items)) AND (SIZEOF(pcr.used_representation.items) <= 8)))) = 0))) = 0;

wr6:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| NOT (it.name IN [ 'documentation layer purpose', 'design layer purpose', 'design layer position', 'maximum feature size requirement', 'minimum finished feature spacing', 'minimum finished feature size', 'maximum stratum thickness', 'minimum stratum thickness' ]))) = 0))) = 0))) = 0;

wr7:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'minimum finished feature size'))) = 1))) = 0))) = 0;

wr8:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'maximum stratum thickness'))) = 1))) = 0))) = 0;

wr9:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'minimum stratum thickness'))) = 1))) = 0))) = 0;

wr10:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'maximum feature size requirement'))) <= 1))) = 0))) = 0;

wr11:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'minimum finished feature spacing'))) <= 1))) = 0))) = 0;

wr12:
NOT (SELF.description = 'documentation layer') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'layer purpose'))) = 1))) = 0))) = 0);

wr13:
NOT (SELF.description = 'design layer') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT') ] * TYPEOF(it)) = 2) AND (it.name = 'minimum finished feature spacing'))) = 1))) = 0))) = 0);

wr14:
NOT (SELF.description = 'design layer') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'layer purpose')) AND (it.description IN [ 'power or ground', 'other signal', 'lands only' ]))) = 1))) = 0))) = 0);

wr15:
NOT (SELF.description = 'design layer') OR (SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (pcr <* 
QUERY (pdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (pdr.used_representation.name = 'physical characteristics representation'))| NOT (SIZEOF(
QUERY (it <* pcr.used_representation.items| (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(it)) AND (it.name = 'layer position')) AND (it.description IN [ 'primary', 'secondary', 'internal' ]))) = 1))) = 0))) = 0);
END_ENTITY;




ENTITY styled_item
SUBTYPE OF (representation_item);

styles : SET [1:?] OF presentation_style_assignment;

item : representation_item;
WHERE

wr1:
(SIZEOF(SELF.styles) = 1) XOR (SIZEOF(
QUERY (pres_style <* SELF.styles| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRESENTATION_STYLE_BY_CONTEXT' IN TYPEOF(pres_style)))) = 0);
END_ENTITY;




ENTITY supplied_part_relationship
SUBTYPE OF (product_definition_relationship);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_FORMATION_WITH_SPECIFIED_SOURCE' IN TYPEOF(SELF.related_product_definition.formation);

wr2:
NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION' IN ROLESOF(SELF));
END_ENTITY;




ENTITY surface
SUPERTYPE OF (ONEOF(elementary_surface, swept_surface, bounded_surface, offset_surface, surface_replica))
SUBTYPE OF (geometric_representation_item);
END_ENTITY;




ENTITY surface_curve
SUPERTYPE OF (ONEOF(intersection_curve, seam_curve) ANDOR bounded_surface_curve)
SUBTYPE OF (curve);

curve_3d : curve;

associated_geometry : LIST [1:2] OF pcurve_or_surface;

master_representation : preferred_surface_curve_representation;
DERIVE

basis_surface : SET [1:2] OF surface := get_basis_surface(SELF);
WHERE

wr1:
curve_3d.dim = 3;

wr2:
('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PCURVE' IN TYPEOF(associated_geometry[1])) OR (master_representation <> pcurve_s1);

wr3:
('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PCURVE' IN TYPEOF(associated_geometry[2])) OR (master_representation <> pcurve_s2);

wr4:
NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PCURVE' IN TYPEOF(curve_3d));
END_ENTITY;




ENTITY surface_of_linear_extrusion
SUBTYPE OF (swept_surface);

extrusion_axis : vector;
END_ENTITY;




ENTITY surface_of_revolution
SUBTYPE OF (swept_surface);

axis_position : axis1_placement;
DERIVE

axis_line : line := dummy_gri || curve() || line(axis_position.location, dummy_gri || vector(axis_position.z, 1));
END_ENTITY;




ENTITY surface_patch;

parent_surface : bounded_surface;

u_transition : transition_code;

v_transition : transition_code;

u_sense : BOOLEAN;

v_sense : BOOLEAN;
INVERSE

using_surfaces : BAG [1:?] OF rectangular_composite_surface FOR segments;
WHERE

wr1:
NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CURVE_BOUNDED_SURFACE' IN TYPEOF(parent_surface));

wr2:
SIZEOF(
QUERY (rcs <* SELF.using_surfaces| (SIZEOF(
QUERY (rep <* using_representations(rcs)| NOT item_in_context(SELF.parent_surface, rep.context_of_items))) > 0))) = 0;
END_ENTITY;




ENTITY surface_profile_tolerance
SUBTYPE OF (physical_unit_geometric_tolerance);
END_ENTITY;




ENTITY surface_replica
SUBTYPE OF (surface);

parent_surface : surface;

transformation : cartesian_transformation_operator_3d;
WHERE

wr1:
acyclic_surface_replica(SELF, parent_surface);
END_ENTITY;




ENTITY swept_area_solid
SUPERTYPE OF (ONEOF(revolved_area_solid, extruded_area_solid))
SUBTYPE OF (solid_model);

swept_area : curve_bounded_surface;
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PLANE' IN TYPEOF(swept_area.basis_surface);
END_ENTITY;




ENTITY swept_surface
SUPERTYPE OF (ONEOF(surface_of_linear_extrusion, surface_of_revolution))
SUBTYPE OF (surface);

swept_curve : curve;
END_ENTITY;




ENTITY symbol_representation
SUBTYPE OF (representation);
END_ENTITY;




ENTITY symbol_representation_map
SUBTYPE OF (representation_map);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SYMBOL_REPRESENTATION' IN TYPEOF(SELF\representation_map.mapped_representation);

wr2:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AXIS2_PLACEMENT' IN TYPEOF(SELF\representation_map.mapping_origin);
END_ENTITY;




ENTITY symbol_target
SUBTYPE OF (geometric_representation_item);

placement : axis2_placement;

x_scale : positive_ratio_measure;

y_scale : positive_ratio_measure;
END_ENTITY;




ENTITY symmetric_shape_aspect
SUBTYPE OF (shape_aspect);
INVERSE

basis_relationships : SET [1:?] OF shape_aspect_relationship FOR relating_shape_aspect;
WHERE

wr1:
SIZEOF(
QUERY (x <* SELF.basis_relationships| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CENTRE_OF_SYMMETRY' IN TYPEOF(x.related_shape_aspect)))) >= 1;
END_ENTITY;




ENTITY symmetry_tolerance
SUBTYPE OF (geometric_tolerance_with_specified_datum_system);
WHERE

wr1:
SELF\geometric_tolerance.name = 'symmetry';
END_ENTITY;




ENTITY tangent
SUBTYPE OF (derived_shape_aspect);
WHERE

wr1:
SIZEOF(SELF\derived_shape_aspect.deriving_relationships) = 1;
END_ENTITY;




ENTITY text_font;

id : identifier;

name : label;

description : text;
INVERSE

glyphs : SET [1:?] OF character_glyph_font_usage FOR font;
END_ENTITY;




ENTITY text_font_family;

id : identifier;

name : label;

description : text;
INVERSE

fonts : SET [1:?] OF text_font_in_family FOR family;
END_ENTITY;




ENTITY text_font_in_family;

font : text_font;

family : text_font_family;
END_ENTITY;




ENTITY text_literal
SUBTYPE OF (geometric_representation_item);

literal : presentable_text;

placement : axis2_placement;

alignment : text_alignment;

path : text_path;

font : font_select;
END_ENTITY;




ENTITY text_literal_with_associated_curves
SUBTYPE OF (text_literal);

associated_curves : SET [1:?] OF curve;
END_ENTITY;




ENTITY text_literal_with_extent
SUBTYPE OF (text_literal);

extent : planar_extent;
END_ENTITY;




ENTITY text_string_representation
SUBTYPE OF (representation);
WHERE

wr1:
SIZEOF(
QUERY (item <* SELF\representation.items| (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.TEXT_LITERAL', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ANNOTATION_TEXT', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ANNOTATION_TEXT_CHARACTER', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.DEFINED_CHARACTER_GLYPH', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.COMPOSITE_TEXT', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AXIS2_PLACEMENT' ] * TYPEOF(item)) = 0))) = 0;

wr2:
SIZEOF(
QUERY (item <* SELF\representation.items| NOT (SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.TEXT_LITERAL', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ANNOTATION_TEXT', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ANNOTATION_TEXT_CHARACTER', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.DEFINED_CHARACTER_GLYPH', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.COMPOSITE_TEXT' ] * TYPEOF(item)) = 0))) >= 1;

wr3:
SIZEOF(
QUERY (a2p <* 
QUERY (item <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AXIS2_PLACEMENT' IN TYPEOF(item)))| NOT ((SIZEOF(
QUERY (at <* 
QUERY (item <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ANNOTATION_TEXT' IN TYPEOF(item)))| (at\mapped_item.mapping_target :=: a2p))) >= 1) OR (SIZEOF(
QUERY (atc <* 
QUERY (item <* SELF\representation.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ANNOTATION_TEXT_CHARACTER' IN TYPEOF(item)))| (atc\mapped_item.mapping_target :=: a2p))) >= 1)))) = 0;
END_ENTITY;




ENTITY text_style;

name : label;

character_appearance : character_style_select;
END_ENTITY;




ENTITY text_style_for_defined_font;

text_colour : colour;
END_ENTITY;




ENTITY thermal_component
SUBTYPE OF (component_definition);
END_ENTITY;




ENTITY thermal_component_shape_aspect
SUBTYPE OF (component_shape_aspect);
END_ENTITY;




ENTITY thermal_feature
SUBTYPE OF (shape_aspect);
END_ENTITY;




ENTITY thermal_network
SUBTYPE OF (functional_unit);
END_ENTITY;




ENTITY thermodynamic_temperature_measure_with_unit
SUBTYPE OF (measure_with_unit);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.THERMODYNAMIC_TEMPERATURE_UNIT' IN TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY;




ENTITY thermodynamic_temperature_unit
SUBTYPE OF (named_unit);
WHERE

wr1:
((((((SELF\named_unit.dimensions.length_exponent = 0) AND (SELF\named_unit.dimensions.mass_exponent = 0)) AND (SELF\named_unit.dimensions.time_exponent = 0)) AND (SELF\named_unit.dimensions.electric_current_exponent = 0)) AND (SELF\named_unit.dimensions.thermodynamic_temperature_exponent = 1)) AND (SELF\named_unit.dimensions.amount_of_substance_exponent = 0)) AND (SELF\named_unit.dimensions.luminous_intensity_exponent = 0);
END_ENTITY;




ENTITY time_measure_with_unit
SUBTYPE OF (measure_with_unit);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.TIME_UNIT' IN TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY;




ENTITY time_unit
SUBTYPE OF (named_unit);
WHERE

wr1:
((((((SELF\named_unit.dimensions.length_exponent = 0) AND (SELF\named_unit.dimensions.mass_exponent = 0)) AND (SELF\named_unit.dimensions.time_exponent = 1)) AND (SELF\named_unit.dimensions.electric_current_exponent = 0)) AND (SELF\named_unit.dimensions.thermodynamic_temperature_exponent = 0)) AND (SELF\named_unit.dimensions.amount_of_substance_exponent = 0)) AND (SELF\named_unit.dimensions.luminous_intensity_exponent = 0);
END_ENTITY;




ENTITY tolerance_value;

lower_bound : measure_with_unit;

upper_bound : measure_with_unit;
WHERE

wr1:
upper_bound.value_component > lower_bound.value_component;

wr2:
upper_bound.unit_component = lower_bound.unit_component;
END_ENTITY;




ENTITY tolerance_zone
SUBTYPE OF (shape_aspect);

defining_tolerance : SET [1:?] OF geometric_tolerance;

form : tolerance_zone_form;
END_ENTITY;




ENTITY tolerance_zone_boundary
SUBTYPE OF (shape_aspect);
END_ENTITY;




ENTITY tolerance_zone_definition
SUPERTYPE OF (ONEOF(projected_zone_definition, runout_zone_definition));

zone : tolerance_zone;

boundaries : SET [1:?] OF shape_aspect;
END_ENTITY;




ENTITY tolerance_zone_explicit_opposing_boundary_set
SUBTYPE OF (tolerance_zone_boundary);
END_ENTITY;




ENTITY tolerance_zone_form;

name : label;
END_ENTITY;




ENTITY tolerance_zone_implicit_opposing_boundary_set
SUBTYPE OF (tolerance_zone_boundary);
END_ENTITY;




ENTITY topological_representation_item
SUPERTYPE OF (ONEOF(vertex, edge, face_bound, face, vertex_shell, wire_shell, connected_edge_set, connected_face_set, loop ANDOR path))
SUBTYPE OF (representation_item);
END_ENTITY;




ENTITY toroidal_surface
SUBTYPE OF (elementary_surface);

major_radius : positive_length_measure;

minor_radius : positive_length_measure;
END_ENTITY;




ENTITY torus
SUBTYPE OF (geometric_representation_item);

position : axis1_placement;

major_radius : positive_length_measure;

minor_radius : positive_length_measure;
WHERE

wr1:
major_radius > minor_radius;
END_ENTITY;




ENTITY total_runout_tolerance
SUBTYPE OF (geometric_tolerance_with_specified_datum_system);
WHERE

wr1:
SELF\geometric_tolerance.name = 'total runout';
END_ENTITY;




ENTITY trimmed_curve
SUBTYPE OF (bounded_curve);

basis_curve : curve;

trim_1 : SET [1:2] OF trimming_select;

trim_2 : SET [1:2] OF trimming_select;

sense_agreement : BOOLEAN;

master_representation : trimming_preference;
WHERE

wr1:
(HIINDEX(trim_1) = 1) OR (TYPEOF(trim_1[1]) <> TYPEOF(trim_1[2]));

wr2:
(HIINDEX(trim_2) = 1) OR (TYPEOF(trim_2[1]) <> TYPEOF(trim_2[2]));
END_ENTITY;




ENTITY two_direction_repeat_factor
SUBTYPE OF (one_direction_repeat_factor);

second_repeat_factor : vector;
END_ENTITY;




ENTITY type_qualifier;

name : label;
END_ENTITY;




ENTITY uncertainty_measure_with_unit
SUBTYPE OF (measure_with_unit);

name : label;

description : text;
WHERE

wr1:
NOT ('NUMBER' IN TYPEOF(SELF\measure_with_unit.value_component)) OR (SELF\measure_with_unit.value_component >= 0);
END_ENTITY;




ENTITY uncertainty_qualifier
SUPERTYPE OF (ONEOF(standard_uncertainty, qualitative_uncertainty));

measure_name : label;

description : text;
END_ENTITY;




ENTITY uniform_curve
SUBTYPE OF (b_spline_curve);
END_ENTITY;




ENTITY uniform_surface
SUBTYPE OF (b_spline_surface);
END_ENTITY;




ENTITY vector
SUBTYPE OF (geometric_representation_item);

orientation : direction;

magnitude : length_measure;
WHERE

wr1:
magnitude >= 0;
END_ENTITY;




ENTITY versioned_action_request;

id : identifier;

version : label;

purpose : text;

description : text;
END_ENTITY;




ENTITY vertex
SUBTYPE OF (topological_representation_item);
END_ENTITY;




ENTITY vertex_loop
SUBTYPE OF (loop);

loop_vertex : vertex;
END_ENTITY;




ENTITY vertex_point
SUBTYPE OF (vertex, geometric_representation_item);

vertex_geometry : point;
END_ENTITY;




ENTITY vertex_shell
SUBTYPE OF (topological_representation_item);

vertex_shell_extent : vertex_loop;
END_ENTITY;




ENTITY viewing_plane
SUBTYPE OF (shape_aspect);
WHERE

wr1:
SELF\shape_aspect.description = 'affected plane';

wr2:
SIZEOF(
QUERY (pd <* USEDIN(SELF, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.' + 'DEFINITION')| (pd.description = 'viewing plane property'))) = 1;
END_ENTITY;




ENTITY volume_measure_with_unit
SUBTYPE OF (measure_with_unit);
WHERE

wr1:
'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VOLUME_UNIT' IN TYPEOF(SELF\measure_with_unit.unit_component);
END_ENTITY;




ENTITY volume_unit
SUBTYPE OF (named_unit);
WHERE

wr1:
((((((SELF\named_unit.dimensions.length_exponent = 3) AND (SELF\named_unit.dimensions.mass_exponent = 0)) AND (SELF\named_unit.dimensions.time_exponent = 0)) AND (SELF\named_unit.dimensions.electric_current_exponent = 0)) AND (SELF\named_unit.dimensions.thermodynamic_temperature_exponent = 0)) AND (SELF\named_unit.dimensions.amount_of_substance_exponent = 0)) AND (SELF\named_unit.dimensions.luminous_intensity_exponent = 0);
END_ENTITY;




ENTITY wire_shell
SUBTYPE OF (topological_representation_item);

wire_shell_extent : SET [1:?] OF loop;
WHERE

wr1:
NOT mixed_loop_type_set(wire_shell_extent);
END_ENTITY;





***********************************



TYPE action_assigned_item = SELECT
(product_definition_formation,
 rule_definition);
END_TYPE;




TYPE ahead_or_behind = ENUMERATION OF
(
ahead,
 
behind);
END_TYPE;




TYPE amount_of_substance_measure = REAL;
END_TYPE;




TYPE angle_relator = ENUMERATION OF
(
equal,
 
large,
 
small);
END_TYPE;




TYPE approval_assigned_item = SELECT
(action,
 action_directive,
 alternate_product_relationship,
 applied_date_and_time_assignment,
 applied_document_reference,
 certification,
 change_request,
 characterized_object,
 colour,
 component_definition,
 component_shape_aspect,
 composite_curve_segment,
 configuration_effectivity,
 configuration_item,
 contract,
 curve_style,
 curve_style_font,
 curve_style_font_and_scaling,
 date,
 dimensional_characteristic_representation,
 dimensional_size,
 directed_action,
 document,
 document_usage_constraint,
 externally_defined_item,
 fill_area_style,
 fill_area_style_colour,
 geometric_tolerance,
 geometric_tolerance_relationship,
 group,
 inter_stratum_feature,
 material_designation,
 measure_with_unit,
 plus_minus_tolerance,
 pre_defined_item,
 product,
 product_concept,
 product_definition,
 product_definition_formation,
 product_definition_formation_relationship,
 product_definition_formation_with_specified_source,
 product_definition_relationship,
 property_definition,
 property_definition_relationship,
 property_definition_representation,
 representation,
 representation_context,
 representation_item,
 representation_relationship,
 runout_zone_orientation,
 security_classification,
 shape_aspect,
 shape_aspect_relationship,
 start_request,
 stratum_feature,
 tolerance_value,
 tolerance_zone_form,
 versioned_action_request);
END_TYPE;




TYPE area_measure = REAL;
END_TYPE;




TYPE axis2_placement = SELECT
(axis2_placement_2d,
 axis2_placement_3d);
END_TYPE;




TYPE b_spline_curve_form = ENUMERATION OF
(
polyline_form,
 
circular_arc,
 
elliptic_arc,
 
parabolic_arc,
 
hyperbolic_arc,
 
unspecified);
END_TYPE;




TYPE b_spline_surface_form = ENUMERATION OF
(
plane_surf,
 
cylindrical_surf,
 
conical_surf,
 
spherical_surf,
 
toroidal_surf,
 
surf_of_revolution,
 
ruled_surf,
 
generalised_cone,
 
quadric_surf,
 
surf_of_linear_extrusion,
 
unspecified);
END_TYPE;




TYPE boolean_operand = SELECT
(solid_model,
 half_space_solid,
 csg_primitive,
 boolean_result);
END_TYPE;




TYPE boolean_operator = ENUMERATION OF
(
union,
 
intersection,
 
difference);
END_TYPE;




TYPE box_characteristic_select = SELECT
(box_height,
 box_width,
 box_slant_angle,
 box_rotate_angle);
END_TYPE;




TYPE box_height = positive_ratio_measure;
END_TYPE;




TYPE box_rotate_angle = plane_angle_measure;
END_TYPE;




TYPE box_slant_angle = plane_angle_measure;
END_TYPE;




TYPE box_width = positive_ratio_measure;
END_TYPE;




TYPE certification_assigned_item = SELECT
(supplied_part_relationship,
 make_from_usage_option,
 product_definition_formation_with_specified_source);
END_TYPE;




TYPE change_request_item = SELECT
(product_definition_formation);
END_TYPE;




TYPE character_spacing_select = SELECT
(length_measure,
 ratio_measure,
 measure_with_unit,
 descriptive_measure);
END_TYPE;




TYPE character_style_select = SELECT
(character_glyph_style_stroke,
 character_glyph_style_outline,
 text_style_for_defined_font);
END_TYPE;




TYPE characterized_definition = SELECT
(characterized_object,
 characterized_product_definition,
 shape_definition);
END_TYPE;




TYPE characterized_material_property = SELECT
(material_property_representation,
 product_material_composition_relationship);
END_TYPE;




TYPE characterized_product_definition = SELECT
(product_definition,
 product_definition_relationship);
END_TYPE;




TYPE classification_assigned_item = SELECT
(requirements_property,
 signal,
 stratum);
END_TYPE;




TYPE context_dependent_measure = REAL;
END_TYPE;




TYPE contract_assigned_item = SELECT
(alternate_product_relationship,
 directed_action,
 product,
 product_definition_formation);
END_TYPE;




TYPE count_measure = NUMBER;
END_TYPE;




TYPE csg_primitive = SELECT
(sphere,
 block,
 right_angular_wedge,
 torus,
 right_circular_cone,
 right_circular_cylinder);
END_TYPE;




TYPE csg_select = SELECT
(boolean_result,
 csg_primitive);
END_TYPE;




TYPE curve_font_or_scaled_curve_font_select = SELECT
(curve_style_font_select,
 curve_style_font_and_scaling);
END_TYPE;




TYPE curve_on_surface = SELECT
(pcurve,
 surface_curve,
 composite_curve_on_surface);
END_TYPE;




TYPE curve_or_annotation_curve_occurrence = SELECT
(curve,
 annotation_curve_occurrence);
END_TYPE;




TYPE curve_or_render = SELECT
(curve_style);
END_TYPE;




TYPE curve_style_font_select = SELECT
(curve_style_font,
 pre_defined_curve_font,
 externally_defined_curve_font);
END_TYPE;




TYPE date_and_time_assigned_item = SELECT
(approval_person_organization,
 certification,
 change,
 contract,
 directed_action,
 document,
 product_definition,
 rule_action,
 security_classification,
 versioned_action_request);
END_TYPE;




TYPE date_assigned_item = SELECT
(product_definition,
 versioned_action_request,
 directed_action,
 approval_person_organization,
 contract,
 security_classification,
 certification);
END_TYPE;




TYPE date_time_select = SELECT
(date,
 local_time,
 date_and_time);
END_TYPE;




TYPE day_in_month_number = INTEGER;
END_TYPE;




TYPE defined_symbol_select = SELECT
(externally_defined_symbol);
END_TYPE;




TYPE descriptive_measure = STRING;
END_TYPE;




TYPE dimension_count = INTEGER;
WHERE

wr1:
SELF > 0;
END_TYPE;




TYPE dimensional_characteristic = SELECT
(dimensional_location,
 dimensional_size);
END_TYPE;




TYPE document_assigned_item = SELECT
(action_method,
 assembly_component_usage,
 bond_category,
 characterized_object,
 component_definition,
 component_interface_terminal,
 component_shape_aspect,
 component_terminal,
 configuration_item,
 descriptive_representation_item,
 externally_defined_item,
 functional_unit_terminal_definition,
 layer,
 measure_representation_item,
 package_terminal,
 part_template_definition,
 product,
 product_definition,
 product_definition_formation,
 product_definition_formation_relationship,
 property_definition,
 representation,
 representation_item,
 requirements_property,
 rule_definition,
 shape_aspect,
 signal,
 stratum);
END_TYPE;




TYPE electric_current_measure = REAL;
END_TYPE;




TYPE fill_area_style_tile_shape_select = SELECT
(fill_area_style_tile_curve_with_style,
 fill_area_style_tile_coloured_region,
 fill_area_style_tile_symbol_with_style,
 externally_defined_tile);
END_TYPE;




TYPE fill_style_select = SELECT
(fill_area_style_colour,
 externally_defined_tile_style,
 fill_area_style_tiles,
 externally_defined_hatch_style,
 fill_area_style_hatching);
END_TYPE;




TYPE font_select = SELECT
(externally_defined_text_font);
END_TYPE;




TYPE geometric_set_select = SELECT
(point,
 curve,
 surface);
END_TYPE;




TYPE group_assigned_item = SELECT
(component_definition,
 component_interface_terminal,
 component_shape_aspect,
 component_terminal,
 configuration_item,
 inter_stratum_feature,
 printed_part_template_terminal,
 product,
 product_definition_formation,
 representation,
 representation_item,
 requirements_property,
 rule_definition,
 shape_aspect,
 stratum,
 stratum_feature,
 stratum_surface);
END_TYPE;




TYPE hiding_or_blanking_select = SELECT
(annotation_fill_area,
 character_glyph_symbol_outline);
END_TYPE;




TYPE hour_in_day = INTEGER;
WHERE

wr1:
(0 <= SELF) AND (SELF < 24);
END_TYPE;




TYPE identifier = STRING;
END_TYPE;




TYPE invisibility_context = SELECT
(presentation_representation);
END_TYPE;




TYPE invisible_item = SELECT
(styled_item,
 presentation_representation);
END_TYPE;




TYPE knot_type = ENUMERATION OF
(
uniform_knots,
 
unspecified,
 
quasi_uniform_knots,
 
piecewise_bezier_knots);
END_TYPE;




TYPE label = STRING;
END_TYPE;




TYPE layered_item = SELECT
(presentation_representation,
 representation_item);
END_TYPE;




TYPE length_measure = REAL;
END_TYPE;




TYPE limit_condition = ENUMERATION OF
(
maximum_material_condition,
 
least_material_condition,
 
regardless_of_feature_size);
END_TYPE;




TYPE list_of_reversible_topology_item = LIST [0:?] OF reversible_topology_item;
END_TYPE;




TYPE luminous_intensity_measure = REAL;
END_TYPE;




TYPE managed_design_object = SELECT
(action,
 alternate_product_relationship,
 applied_approval_assignment,
 applied_date_and_time_assignment,
 applied_document_reference,
 approval,
 approval_status,
 certification,
 characterized_object,
 colour,
 composite_curve_segment,
 configuration_effectivity,
 configuration_item,
 contract,
 curve_style,
 curve_style_font,
 curve_style_font_and_scaling,
 date,
 dimensional_characteristic_representation,
 dimensional_size,
 document,
 document_usage_constraint,
 externally_defined_item,
 fill_area_style,
 fill_area_style_colour,
 geometric_tolerance,
 geometric_tolerance_relationship,
 group,
 material_designation,
 measure_with_unit,
 organization,
 person,
 person_and_organization,
 plus_minus_tolerance,
 pre_defined_item,
 product,
 product_concept,
 product_definition,
 product_definition_formation,
 product_definition_formation_relationship,
 product_definition_relationship,
 property_definition,
 property_definition_relationship,
 property_definition_representation,
 representation,
 representation_context,
 representation_item,
 representation_relationship,
 runout_zone_orientation,
 security_classification,
 shape_aspect,
 shape_aspect_relationship,
 tolerance_value,
 tolerance_zone_form,
 versioned_action_request);
END_TYPE;




TYPE mass_measure = REAL;
END_TYPE;




TYPE measure_value = SELECT
(length_measure,
 mass_measure,
 time_measure,
 electric_current_measure,
 thermodynamic_temperature_measure,
 amount_of_substance_measure,
 luminous_intensity_measure,
 plane_angle_measure,
 solid_angle_measure,
 area_measure,
 volume_measure,
 ratio_measure,
 parameter_value,
 numeric_measure,
 context_dependent_measure,
 descriptive_measure,
 positive_length_measure,
 positive_plane_angle_measure,
 positive_ratio_measure,
 count_measure);
END_TYPE;




TYPE minute_in_hour = INTEGER;
WHERE

wr1:
(0 <= SELF) AND (SELF <= 59);
END_TYPE;




TYPE month_in_year_number = INTEGER;
WHERE

wr1:
(1 <= SELF) AND (SELF <= 12);
END_TYPE;




TYPE numeric_measure = NUMBER;
END_TYPE;




TYPE organization_assigned_item = SELECT
(configuration_item,
 contract,
 directed_action,
 document,
 versioned_action_request,
 product,
 product_definition,
 product_definition_formation,
 product_definition_formation_with_specified_source,
 representation,
 security_classification);
END_TYPE;




TYPE parameter_value = REAL;
END_TYPE;




TYPE pcurve_or_surface = SELECT
(pcurve,
 surface);
END_TYPE;




TYPE person_and_organization_assigned_item = SELECT
(configuration_item,
 contract,
 document,
 product,
 product_definition_formation,
 product_definition,
 rule_action,
 security_classification,
 versioned_action_request);
END_TYPE;




TYPE person_assigned_item = SELECT
(change,
 document,
 security_classification);
END_TYPE;




TYPE person_organization_select = SELECT
(person,
 organization,
 person_and_organization);
END_TYPE;




TYPE plane_angle_measure = REAL;
END_TYPE;




TYPE positive_length_measure = length_measure;
WHERE

wr1:
SELF > 0;
END_TYPE;




TYPE positive_plane_angle_measure = plane_angle_measure;
WHERE

wr1:
SELF > 0;
END_TYPE;




TYPE positive_ratio_measure = ratio_measure;
WHERE

wr1:
SELF > 0;
END_TYPE;




TYPE preferred_surface_curve_representation = ENUMERATION OF
(
curve_3d,
 
pcurve_s1,
 
pcurve_s2);
END_TYPE;




TYPE presentable_text = STRING;
END_TYPE;




TYPE presentation_representation_select = SELECT
(presentation_representation);
END_TYPE;




TYPE presentation_style_select = SELECT
(curve_style,
 fill_area_style,
 text_style);
END_TYPE;




TYPE ratio_measure = REAL;
END_TYPE;




TYPE replacement_from_item = SELECT
(rule_definition);
END_TYPE;




TYPE replacement_to_item = SELECT
(rule_definition);
END_TYPE;




TYPE reversible_topology = SELECT
(reversible_topology_item,
 list_of_reversible_topology_item,
 set_of_reversible_topology_item);
END_TYPE;




TYPE reversible_topology_item = SELECT
(edge,
 path,
 face,
 face_bound,
 closed_shell,
 open_shell);
END_TYPE;




TYPE second_in_minute = REAL;
WHERE

wr1:
(0 <= SELF) AND (SELF < 60);
END_TYPE;




TYPE security_classification_assigned_item = SELECT
(assembly_component_usage,
 document,
 make_from_usage_option,
 product_definition_formation,
 product_definition);
END_TYPE;




TYPE set_of_reversible_topology_item = SET [0:?] OF reversible_topology_item;
END_TYPE;




TYPE shape_definition = SELECT
(product_definition_shape,
 shape_aspect,
 shape_aspect_relationship);
END_TYPE;




TYPE shell = SELECT
(vertex_shell,
 wire_shell,
 open_shell,
 closed_shell);
END_TYPE;




TYPE si_prefix = ENUMERATION OF
(
exa,
 
peta,
 
tera,
 
giga,
 
mega,
 
kilo,
 
hecto,
 
deca,
 
deci,
 
centi,
 
milli,
 
micro,
 
nano,
 
pico,
 
femto,
 
atto);
END_TYPE;




TYPE si_unit_name = ENUMERATION OF
(
metre,
 
gram,
 
second,
 
ampere,
 
kelvin,
 
mole,
 
candela,
 
radian,
 
steradian,
 
hertz,
 
newton,
 
pascal,
 
joule,
 
watt,
 
coulomb,
 
volt,
 
farad,
 
ohm,
 
siemens,
 
weber,
 
tesla,
 
henry,
 
degree_celsius,
 
lumen,
 
lux,
 
becquerel,
 
gray,
 
sievert);
END_TYPE;




TYPE size_select = SELECT
(positive_length_measure,
 measure_with_unit,
 descriptive_measure);
END_TYPE;




TYPE solid_angle_measure = REAL;
END_TYPE;




TYPE source = ENUMERATION OF
(
made,
 
bought,
 
not_known);
END_TYPE;




TYPE source_item = SELECT
(identifier);
END_TYPE;




TYPE squared_or_rounded = ENUMERATION OF
(
squared,
 
rounded);
END_TYPE;




TYPE start_request_item = SELECT
(product_definition_formation);
END_TYPE;




TYPE style_context_select = SELECT
(representation,
 representation_item);
END_TYPE;




TYPE supported_item = SELECT
(action_directive,
 action,
 action_method);
END_TYPE;




TYPE surface_model = SELECT
(shell_based_surface_model);
END_TYPE;




TYPE text = STRING;
END_TYPE;




TYPE text_alignment = label;
END_TYPE;




TYPE text_or_character = SELECT
(annotation_text,
 annotation_text_character,
 text_literal);
END_TYPE;




TYPE text_path = ENUMERATION OF
(
left,
 
right,
 
up,
 
down);
END_TYPE;




TYPE thermodynamic_temperature_measure = REAL;
END_TYPE;




TYPE time_measure = REAL;
END_TYPE;




TYPE tolerance_method_definition = SELECT
(tolerance_value);
END_TYPE;




TYPE tolerance_select = SELECT
(geometric_tolerance,
 plus_minus_tolerance);
END_TYPE;




TYPE transformation = SELECT
(item_defined_transformation,
 functionally_defined_transformation);
END_TYPE;




TYPE transition_code = ENUMERATION OF
(
discontinuous,
 
continuous,
 
cont_same_gradient,
 
cont_same_gradient_same_curvature);
END_TYPE;




TYPE trimming_preference = ENUMERATION OF
(
cartesian,
 
parameter,
 
unspecified);
END_TYPE;




TYPE trimming_select = SELECT
(cartesian_point,
 parameter_value);
END_TYPE;




TYPE unit = SELECT
(named_unit,
 derived_unit);
END_TYPE;




TYPE value_qualifier = SELECT
(precision_qualifier,
 type_qualifier,
 uncertainty_qualifier);
END_TYPE;




TYPE vector_or_direction = SELECT
(vector,
 direction);
END_TYPE;




TYPE volume_measure = REAL;
END_TYPE;




TYPE wireframe_model = SELECT
(shell_based_wireframe_model,
 edge_based_wireframe_model);
END_TYPE;




TYPE work_item = SELECT
(product_definition_formation);
END_TYPE;




TYPE year_number = INTEGER;
END_TYPE;





***********************************



FUNCTION acyclic_curve_replica
(
rep : curve_replica;
 
parent : curve ) : BOOLEAN;
IF NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CURVE_REPLICA' IN TYPEOF(parent)) THEN
RETURN (TRUE);
END_IF;
IF parent :=: rep THEN
RETURN (FALSE);
ELSE
RETURN (acyclic_curve_replica(rep, parent\curve_replica.parent_curve));
END_IF;
END_FUNCTION;




FUNCTION acyclic_mapped_representation
(
parent_set : SET OF representation;
 
children_set : SET OF representation_item ) : BOOLEAN;
LOCAL

i : INTEGER;

x : SET OF representation_item;

y : SET OF representation_item;
END_LOCAL;
x := 
QUERY (z <* children_set| 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MAPPED_ITEM' IN TYPEOF(z));
IF SIZEOF(x) > 0 THEN
REPEAT
 i := 1 TO HIINDEX(x) BY 1;
IF x[i]\mapped_item.mapping_source.mapped_representation IN parent_set THEN
RETURN (FALSE);
END_IF;
IF NOT acyclic_mapped_representation((parent_set + x[i]\mapped_item.mapping_source.mapped_representation), x[i]\mapped_item.mapping_source.mapped_representation.items) THEN
RETURN (FALSE);
END_IF;
END_REPEAT;
END_IF;
x := children_set - x;
IF SIZEOF(x) > 0 THEN
REPEAT
 i := 1 TO HIINDEX(x) BY 1;
y := 
QUERY (z <* bag_to_set(USEDIN(x[i], ''))| 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.REPRESENTATION_ITEM' IN TYPEOF(z));
IF NOT acyclic_mapped_representation(parent_set, y) THEN
RETURN (FALSE);
END_IF;
END_REPEAT;
END_IF;
RETURN (TRUE);
END_FUNCTION;




FUNCTION acyclic_point_replica
(
rep : point_replica;
 
parent : point ) : BOOLEAN;
IF NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POINT_REPLICA' IN TYPEOF(parent)) THEN
RETURN (TRUE);
END_IF;
IF parent :=: rep THEN
RETURN (FALSE);
ELSE
RETURN (acyclic_point_replica(rep, parent\point_replica.parent_pt));
END_IF;
END_FUNCTION;




FUNCTION acyclic_product_category_relationship
(
relation : product_category_relationship;
 
children : SET OF product_category ) : LOGICAL;
LOCAL

i : INTEGER;

x : SET OF product_category_relationship;

local_children : SET OF product_category;
END_LOCAL;
REPEAT
 i := 1 TO HIINDEX(children) BY 1;
IF relation.category :=: children[i] THEN
RETURN (FALSE);
END_IF;
END_REPEAT;
x := bag_to_set(USEDIN(relation.category, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_CATEGORY_RELATIONSHIP.SUB_CATEGORY'));
local_children := children + relation.category;
IF SIZEOF(x) > 0 THEN
REPEAT
 i := 1 TO HIINDEX(x) BY 1;
IF NOT acyclic_product_category_relationship(x[i], local_children) THEN
RETURN (FALSE);
END_IF;
END_REPEAT;
END_IF;
RETURN (TRUE);
END_FUNCTION;




FUNCTION acyclic_product_definition_relationship
(
relation : product_definition_relationship;
 
relatives : SET OF product_definition;
 
specific_relation : STRING ) : LOGICAL;
LOCAL

i : INTEGER;

x : SET OF product_definition_relationship;

local_relatives : SET OF product_definition;
END_LOCAL;
REPEAT
 i := 1 TO HIINDEX(relatives) BY 1;
IF relation.relating_product_definition :=: relatives[i] THEN
RETURN (FALSE);
END_IF;
END_REPEAT;
x := bag_to_set(USEDIN(relation.relating_product_definition, specific_relation));
local_relatives := relatives + relation.relating_product_definition;
IF SIZEOF(x) > 0 THEN
REPEAT
 i := 1 TO HIINDEX(x) BY 1;
IF NOT acyclic_product_definition_relationship(x[i], local_relatives, specific_relation) THEN
RETURN (FALSE);
END_IF;
END_REPEAT;
END_IF;
RETURN (TRUE);
END_FUNCTION;




FUNCTION acyclic_solid_replica
(
rep : solid_replica;
 
parent : solid_model ) : BOOLEAN;
IF NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SOLID_REPLICA' IN TYPEOF(parent)) THEN
RETURN (TRUE);
END_IF;
IF parent :=: rep THEN
RETURN (FALSE);
ELSE
RETURN (acyclic_solid_replica(rep, parent\solid_replica.parent_solid));
END_IF;
END_FUNCTION;




FUNCTION acyclic_surface_replica
(
rep : surface_replica;
 
parent : surface ) : BOOLEAN;
IF NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SURFACE_REPLICA' IN TYPEOF(parent)) THEN
RETURN (TRUE);
END_IF;
IF parent :=: rep THEN
RETURN (FALSE);
ELSE
RETURN (acyclic_surface_replica(rep, parent\surface_replica.parent_surface));
END_IF;
END_FUNCTION;




FUNCTION applied_date_correlation
(
e : applied_date_assignment;
 
schema_name : STRING ) : BOOLEAN;
LOCAL

d_role : STRING;
END_LOCAL;
d_role := e\date_assignment.role.name;
CASE d_role OF
'creation date' :
IF SIZEOF(e.items) <> SIZEOF(
QUERY (x <* e.items| (schema_name + '.PRODUCT_DEFINITION' IN TYPEOF(x)))) THEN
RETURN (FALSE);
END_IF;
'request date' :
IF SIZEOF(e.items) <> SIZEOF(
QUERY (x <* e.items| (schema_name + '.VERSIONED_ACTION_REQUEST' IN TYPEOF(x)))) THEN
RETURN (FALSE);
END_IF;
'release date' :
IF SIZEOF(e.items) <> SIZEOF(
QUERY (x <* e.items| (SIZEOF([ (schema_name + '.CHANGE' + schema_name + '.START_WORK') ] * TYPEOF(x)) = 1))) THEN
RETURN (FALSE);
END_IF;
'start date' :
IF SIZEOF(e.items) <> SIZEOF(
QUERY (x <* e.items| (SIZEOF([ (schema_name + '.CHANGE' + schema_name + '.START_WORK') ] * TYPEOF(x)) = 1))) THEN
RETURN (FALSE);
END_IF;
'sign off date' :
IF SIZEOF(e.items) <> SIZEOF(
QUERY (x <* e.items| (schema_name + '.APPROVAL_PERSON_ORGANIZATION' IN TYPEOF(x)))) THEN
RETURN (FALSE);
END_IF;
'contract date' :
IF SIZEOF(e.items) <> SIZEOF(
QUERY (x <* e.items| (schema_name + '.CONTRACT' IN TYPEOF(x)))) THEN
RETURN (FALSE);
END_IF;
'certification date' :
IF SIZEOF(e.items) <> SIZEOF(
QUERY (x <* e.items| (schema_name + '.CERTIFICATION' IN TYPEOF(x)))) THEN
RETURN (FALSE);
END_IF;
'classification date' :
IF SIZEOF(e.items) <> SIZEOF(
QUERY (x <* e.items| (schema_name + '.SECURITY_CLASSIFICATION' IN TYPEOF(x)))) THEN
RETURN (FALSE);
END_IF;
'declassification date' :
IF SIZEOF(e.items) <> SIZEOF(
QUERY (x <* e.items| (schema_name + '.SECURITY_CLASSIFICATION' IN TYPEOF(x)))) THEN
RETURN (FALSE);
END_IF;
OTHERWISE :
RETURN (TRUE);
END_CASE;
RETURN (TRUE);
END_FUNCTION;




FUNCTION applied_date_time_correlation
(
e : applied_date_and_time_assignment;
 
schema_name : STRING ) : BOOLEAN;
LOCAL

dt_role : STRING;
END_LOCAL;
dt_role := e\date_and_time_assignment.role.name;
CASE dt_role OF
'creation date' :
IF SIZEOF(e.items) <> SIZEOF(
QUERY (x <* e.items| (schema_name + '.PRODUCT_DEFINITION' IN TYPEOF(x)))) THEN
RETURN (FALSE);
END_IF;
'request date' :
IF SIZEOF(e.items) <> SIZEOF(
QUERY (x <* e.items| (schema_name + '.VERSIONED_ACTION_REQUEST' IN TYPEOF(x)))) THEN
RETURN (FALSE);
END_IF;
'release date' :
IF SIZEOF(e.items) <> SIZEOF(
QUERY (x <* e.items| (SIZEOF([ (schema_name + '.CHANGE' + schema_name + '.START_WORK') ] * TYPEOF(x)) = 1))) THEN
RETURN (FALSE);
END_IF;
'start date' :
IF SIZEOF(e.items) <> SIZEOF(
QUERY (x <* e.items| (SIZEOF([ (schema_name + '.CHANGE' + schema_name + '.START_WORK') ] * TYPEOF(x)) = 1))) THEN
RETURN (FALSE);
END_IF;
'sign off date' :
IF SIZEOF(e.items) <> SIZEOF(
QUERY (x <* e.items| (schema_name + '.APPROVAL_PERSON_ORGANIZATION' IN TYPEOF(x)))) THEN
RETURN (FALSE);
END_IF;
'contract date' :
IF SIZEOF(e.items) <> SIZEOF(
QUERY (x <* e.items| (schema_name + '.CONTRACT' IN TYPEOF(x)))) THEN
RETURN (FALSE);
END_IF;
'certification date' :
IF SIZEOF(e.items) <> SIZEOF(
QUERY (x <* e.items| (schema_name + '.CERTIFICATION' IN TYPEOF(x)))) THEN
RETURN (FALSE);
END_IF;
'classification date' :
IF SIZEOF(e.items) <> SIZEOF(
QUERY (x <* e.items| (schema_name + '.SECURITY_CLASSIFICATION' IN TYPEOF(x)))) THEN
RETURN (FALSE);
END_IF;
'declassification date' :
IF SIZEOF(e.items) <> SIZEOF(
QUERY (x <* e.items| (schema_name + '.SECURITY_CLASSIFICATION' IN TYPEOF(x)))) THEN
RETURN (FALSE);
END_IF;
'participant date and time' :
IF SIZEOF(e.items) <> SIZEOF(
QUERY (x <* e.items| (schema_name + '.RULE_ACTION' IN TYPEOF(x)))) THEN
RETURN (FALSE);
END_IF;
OTHERWISE :
RETURN (TRUE);
END_CASE;
RETURN (TRUE);
END_FUNCTION;




FUNCTION assembly_shape_is_defined
(
assy : next_assembly_usage_occurrence;
 
schma : STRING ) : BOOLEAN;
LOCAL

srr_set : SET OF shape_representation_relationship := [];

i : INTEGER;

j : INTEGER;

sdr_set : SET OF shape_definition_representation := [];

pr1_set : SET OF property_definition := [];

pdrel_set : SET OF product_definition_relationship := [];

pr2_set : SET OF property_definition := [];
END_LOCAL;
pr1_set := bag_to_set(USEDIN(assy.related_product_definition, schma + '.PROPERTY_DEFINITION.DEFINITION'));
REPEAT
 i := 1 TO HIINDEX(pr1_set) BY 1;
sdr_set := sdr_set + 
QUERY (pdr <* USEDIN(pr1_set[i], schma + '.PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (schma + '.SHAPE_DEFINITION_REPRESENTATION' IN TYPEOF(pdr)));
END_REPEAT;
pdrel_set := bag_to_set(USEDIN(assy.related_product_definition, schma + '.PRODUCT_DEFINITION_RELATIONSHIP.' + 'RELATED_PRODUCT_DEFINITION'));
REPEAT
 j := 1 TO HIINDEX(pdrel_set) BY 1;
pr2_set := pr2_set + USEDIN(pdrel_set[j], schma + '.PROPERTY_DEFINITION.DEFINITION');
END_REPEAT;
REPEAT
 i := 1 TO HIINDEX(pr2_set) BY 1;
sdr_set := sdr_set + 
QUERY (pdr <* USEDIN(pr2_set[i], schma + '.PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| (schma + '.SHAPE_DEFINITION_REPRESENTATION' IN TYPEOF(pdr)));
END_REPEAT;
IF SIZEOF(sdr_set) > 0 THEN
REPEAT
 i := 1 TO HIINDEX(sdr_set) BY 1;
srr_set := 
QUERY (rr <* bag_to_set(USEDIN(sdr_set[i]\property_definition_representation.used_representation, schma + '.REPRESENTATION_RELATIONSHIP.REP_2'))| schma + '.SHAPE_REPRESENTATION_RELATIONSHIP' IN TYPEOF(rr));
IF SIZEOF(srr_set) > 0 THEN
REPEAT
 j := 1 TO HIINDEX(srr_set) BY 1;
IF SIZEOF(
QUERY (pdr <* bag_to_set(USEDIN(srr_set[j]\representation_relationship.rep_1, (schma + '.PROPERTY_DEFINITION_REPRESENTATION.USED_REPRESENTATION')))| (schma + '.SHAPE_DEFINITION_REPRESENTATION' IN TYPEOF(pdr))) * 
QUERY (pdr <* bag_to_set(USEDIN(assy.relating_product_definition, (schma + '.PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')))| (schma + '.SHAPE_DEFINITION_REPRESENTATION' IN TYPEOF(pdr)))) >= 1 THEN
IF SIZEOF(
QUERY (cdsr <* USEDIN(srr_set[j], schma + '.CONTEXT_DEPENDENT_SHAPE_REPRESENTATION.' + 'REPRESENTATION_RELATION')| NOT (cdsr\context_dependent_shape_representation.represented_product_relation\property_definition.definition :=: assy))) > 0 THEN
RETURN (FALSE);
END_IF;
END_IF;
END_REPEAT;
END_IF;
END_REPEAT;
END_IF;
RETURN (TRUE);
END_FUNCTION;




FUNCTION associated_surface
(
arg : pcurve_or_surface ) : surface;
LOCAL

surf : surface;
END_LOCAL;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PCURVE' IN TYPEOF(arg) THEN
surf := arg.basis_surface;
ELSE
surf := arg;
END_IF;
RETURN (surf);
END_FUNCTION;




FUNCTION bag_to_set
(
the_bag : BAG OF GENERIC : intype ) : SET OF GENERIC : intype;
LOCAL

i : INTEGER;

the_set : SET OF GENERIC : intype := [];
END_LOCAL;
IF SIZEOF(the_bag) > 0 THEN
REPEAT
 i := 1 TO HIINDEX(the_bag) BY 1;
the_set := the_set + the_bag[i];
END_REPEAT;
END_IF;
RETURN (the_set);
END_FUNCTION;




FUNCTION base_axis
(
dim : INTEGER;
 
axis1 : direction;
 
axis2 : direction;
 
axis3 : direction ) : LIST [2:3] OF direction;
LOCAL

u : LIST [2:3] OF direction;

vec : direction;

factor : REAL;
END_LOCAL;
IF dim = 3 THEN
u[3] := NVL(normalise(axis3), dummy_gri || direction([ 0, 0, 1 ]));
u[1] := first_proj_axis(u[3], axis1);
u[2] := second_proj_axis(u[3], u[1], axis2);
ELSE
u[3] := ?;
IF EXISTS(axis1) THEN
u[1] := normalise(axis1);
u[2] := orthogonal_complement(u[1]);
IF EXISTS(axis2) THEN
factor := dot_product(axis2, u[2]);
IF factor < 0 THEN
u[2].direction_ratios[1] := -u[2].direction_ratios[1];
u[2].direction_ratios[2] := -u[2].direction_ratios[2];
END_IF;
END_IF;
ELSE
IF EXISTS(axis2) THEN
u[2] := normalise(axis2);
u[1] := orthogonal_complement(u[2]);
u[1].direction_ratios[1] := -u[1].direction_ratios[1];
u[1].direction_ratios[2] := -u[1].direction_ratios[2];
ELSE
u[1].name := '';
u[2].name := '';
u[1].direction_ratios[1] := 1;
u[1].direction_ratios[2] := 0;
u[2].direction_ratios[1] := 0;
u[2].direction_ratios[2] := 1;
END_IF;
END_IF;
END_IF;
RETURN (u);
END_FUNCTION;




FUNCTION boolean_choose
(
b : BOOLEAN;
 
choice1 : GENERIC : item;
 
choice2 : GENERIC : item ) : GENERIC : item;
IF b THEN
RETURN (choice1);
ELSE
RETURN (choice2);
END_IF;
END_FUNCTION;




FUNCTION build_2axes
(
ref_direction : direction ) : LIST [2:2] OF direction;
LOCAL

u : LIST [2:2] OF direction;
END_LOCAL;
u[1] := NVL(normalise(ref_direction), dummy_gri || direction([ 1, 0 ]));
u[2] := orthogonal_complement(u[1]);
RETURN (u);
END_FUNCTION;




FUNCTION build_axes
(
axis : direction;
 
ref_direction : direction ) : LIST [3:3] OF direction;
LOCAL

d : direction;

u : LIST [3:3] OF direction;
END_LOCAL;
d := NVL(normalise(axis), dummy_gri || direction([ 0, 0, 1 ]));
u[1] := first_proj_axis(d, ref_direction);
u[2] := normalise(cross_product(d, u[1])).orientation;
u[3] := d;
RETURN (u);
END_FUNCTION;




FUNCTION conditional_reverse
(
p : BOOLEAN;
 
an_item : reversible_topology ) : reversible_topology;
IF p THEN
RETURN (an_item);
ELSE
RETURN (topology_reversed(an_item));
END_IF;
END_FUNCTION;




FUNCTION constraints_composite_curve_on_surface
(
c : composite_curve_on_surface ) : BOOLEAN;
LOCAL

n_segments : INTEGER := SIZEOF(c.segments);
END_LOCAL;
REPEAT
 k := 1 TO n_segments BY 1;
IF (NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PCURVE' IN TYPEOF(c\composite_curve.segments[k].parent_curve)) AND NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SURFACE_CURVE' IN TYPEOF(c\composite_curve.segments[k].parent_curve))) AND NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.COMPOSITE_CURVE_ON_SURFACE' IN TYPEOF(c\composite_curve.segments[k].parent_curve)) THEN
RETURN (FALSE);
END_IF;
END_REPEAT;
RETURN (TRUE);
END_FUNCTION;




FUNCTION constraints_geometry_shell_based_surface_model
(
m : shell_based_surface_model ) : BOOLEAN;
LOCAL

result : BOOLEAN := TRUE;
END_LOCAL;
REPEAT
 j := 1 TO SIZEOF(m.sbsm_boundary) BY 1;
IF NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.OPEN_SHELL' IN TYPEOF(m.sbsm_boundary[j])) AND NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CLOSED_SHELL' IN TYPEOF(m.sbsm_boundary[j])) THEN
result := FALSE;
RETURN (result);
END_IF;
END_REPEAT;
RETURN (result);
END_FUNCTION;




FUNCTION constraints_geometry_shell_based_wireframe_model
(
m : shell_based_wireframe_model ) : BOOLEAN;
LOCAL

result : BOOLEAN := TRUE;
END_LOCAL;
REPEAT
 j := 1 TO SIZEOF(m.sbwm_boundary) BY 1;
IF NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.WIRE_SHELL' IN TYPEOF(m.sbwm_boundary[j])) AND NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VERTEX_SHELL' IN TYPEOF(m.sbwm_boundary[j])) THEN
result := FALSE;
RETURN (result);
END_IF;
END_REPEAT;
RETURN (result);
END_FUNCTION;




FUNCTION constraints_param_b_spline
(
degree : INTEGER;
 
up_knots : INTEGER;
 
up_cp : INTEGER;
 
knot_mult : LIST OF INTEGER;
 
knots : LIST OF parameter_value ) : BOOLEAN;
LOCAL

k : INTEGER;

l : INTEGER;

sum : INTEGER;

result : BOOLEAN := TRUE;
END_LOCAL;
sum := knot_mult[1];
REPEAT
 i := 2 TO up_knots BY 1;
sum := sum + knot_mult[i];
END_REPEAT;
IF (((degree < 1) OR (up_knots < 2)) OR (up_cp < degree)) OR (sum <> degree + up_cp + 2) THEN
result := FALSE;
RETURN (result);
END_IF;
k := knot_mult[1];
IF (k < 1) OR (k > degree + 1) THEN
result := FALSE;
RETURN (result);
END_IF;
REPEAT
 i := 2 TO up_knots BY 1;
IF (knot_mult[i] < 1) OR (knots[i] <= knots[(i - 1)]) THEN
result := FALSE;
RETURN (result);
END_IF;
k := knot_mult[i];
IF (i < up_knots) AND (k > degree) THEN
result := FALSE;
RETURN (result);
END_IF;
IF (i = up_knots) AND (k > degree + 1) THEN
result := FALSE;
RETURN (result);
END_IF;
END_REPEAT;
RETURN (result);
END_FUNCTION;




FUNCTION constraints_rectangular_composite_surface
(
s : rectangular_composite_surface ) : BOOLEAN;
REPEAT
 i := 1 TO s.n_u BY 1;
REPEAT
 j := 1 TO s.n_v BY 1;
IF NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.B_SPLINE_SURFACE' IN TYPEOF(s.segments[i][j].parent_surface)) OR ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.RECTANGULAR_TRIMMED_SURFACE' IN TYPEOF(s.segments[i][j].parent_surface))) THEN
RETURN (FALSE);
END_IF;
END_REPEAT;
END_REPEAT;
REPEAT
 i := 1 TO s.n_u - 1 BY 1;
REPEAT
 j := 1 TO s.n_v BY 1;
IF s.segments[i][j].u_transition = discontinuous THEN
RETURN (FALSE);
END_IF;
END_REPEAT;
END_REPEAT;
REPEAT
 i := 1 TO s.n_u BY 1;
REPEAT
 j := 1 TO s.n_v - 1 BY 1;
IF s.segments[i][j].v_transition = discontinuous THEN
RETURN (FALSE);
END_IF;
END_REPEAT;
END_REPEAT;
RETURN (TRUE);
END_FUNCTION;




FUNCTION cross_product
(
arg1 : direction;
 
arg2 : direction ) : vector;
LOCAL

v2 : LIST [3:3] OF REAL;

v1 : LIST [3:3] OF REAL;

mag : REAL;

res : direction;

result : vector;
END_LOCAL;
IF ((NOT EXISTS(arg1) OR (arg1.dim = 2)) OR NOT EXISTS(arg2)) OR (arg2.dim = 2) THEN
RETURN (?);
ELSE
BEGIN
v1 := normalise(arg1).direction_ratios;
v2 := normalise(arg2).direction_ratios;
res.name := '';
res.direction_ratios[1] := v1[2] * v2[3] - v1[3] * v2[2];
res.direction_ratios[2] := v1[3] * v2[1] - v1[1] * v2[3];
res.direction_ratios[3] := v1[1] * v2[2] - v1[2] * v2[1];
mag := 0;
REPEAT
 i := 1 TO 3 BY 1;
mag := mag + res.direction_ratios[i] * res.direction_ratios[i];
END_REPEAT;
IF mag > 0 THEN
result.orientation := res;
result.magnitude := SQRT(mag);
ELSE
result.orientation := arg1;
result.magnitude := 0;
END_IF;
result.name := '';
RETURN (result);
END;
END_IF;
END_FUNCTION;




FUNCTION curve_weights_positive
(
b : rational_b_spline_curve ) : BOOLEAN;
LOCAL

result : BOOLEAN := TRUE;
END_LOCAL;
REPEAT
 i := 0 TO b.upper_index_on_control_points BY 1;
IF b.weights[i] <= 0 THEN
result := FALSE;
RETURN (result);
END_IF;
END_REPEAT;
RETURN (result);
END_FUNCTION;




FUNCTION derive_dimensional_exponents
(
x : unit ) : dimensional_exponents;
LOCAL

i : INTEGER;

result : dimensional_exponents := dimensional_exponents(0, 0, 0, 0, 0, 0, 0);
END_LOCAL;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.DERIVED_UNIT' IN TYPEOF(x) THEN
REPEAT
 i := LOINDEX(x.elements) TO HIINDEX(x.elements) BY 1;
result.length_exponent := result.length_exponent + x.elements[i].exponent * x.elements[i].unit.dimensions.length_exponent;
result.mass_exponent := result.mass_exponent + x.elements[i].exponent * x.elements[i].unit.dimensions.mass_exponent;
result.time_exponent := result.time_exponent + x.elements[i].exponent * x.elements[i].unit.dimensions.time_exponent;
result.electric_current_exponent := result.electric_current_exponent + x.elements[i].exponent * x.elements[i].unit.dimensions.electric_current_exponent;
result.thermodynamic_temperature_exponent := result.thermodynamic_temperature_exponent + x.elements[i].exponent * x.elements[i].unit.dimensions.thermodynamic_temperature_exponent;
result.amount_of_substance_exponent := result.amount_of_substance_exponent + x.elements[i].exponent * x.elements[i].unit.dimensions.amount_of_substance_exponent;
result.luminous_intensity_exponent := result.luminous_intensity_exponent + x.elements[i].exponent * x.elements[i].unit.dimensions.luminous_intensity_exponent;
END_REPEAT;
ELSE
result := x.dimensions;
END_IF;
RETURN (result);
END_FUNCTION;




FUNCTION dimension_of
(
item : geometric_representation_item ) : dimension_count;
LOCAL

x : SET OF representation;

y : representation_context;
END_LOCAL;
x := using_representations(item);
y := x[1].context_of_items;
RETURN (y\geometric_representation_context.coordinate_space_dimension);
END_FUNCTION;




FUNCTION dimensions_for_si_unit
(
n : si_unit_name ) : dimensional_exponents;
CASE n OF
metre :
RETURN (dimensional_exponents(1, 0, 0, 0, 0, 0, 0));
gram :
RETURN (dimensional_exponents(0, 1, 0, 0, 0, 0, 0));
second :
RETURN (dimensional_exponents(0, 0, 1, 0, 0, 0, 0));
ampere :
RETURN (dimensional_exponents(0, 0, 0, 1, 0, 0, 0));
kelvin :
RETURN (dimensional_exponents(0, 0, 0, 0, 1, 0, 0));
mole :
RETURN (dimensional_exponents(0, 0, 0, 0, 0, 1, 0));
candela :
RETURN (dimensional_exponents(0, 0, 0, 0, 0, 0, 1));
radian :
RETURN (dimensional_exponents(0, 0, 0, 0, 0, 0, 0));
steradian :
RETURN (dimensional_exponents(0, 0, 0, 0, 0, 0, 0));
hertz :
RETURN (dimensional_exponents(0, 0, -1, 0, 0, 0, 0));
newton :
RETURN (dimensional_exponents(1, 1, -2, 0, 0, 0, 0));
pascal :
RETURN (dimensional_exponents(-1, 1, -2, 0, 0, 0, 0));
joule :
RETURN (dimensional_exponents(2, 1, -2, 0, 0, 0, 0));
watt :
RETURN (dimensional_exponents(2, 1, -3, 0, 0, 0, 0));
coulomb :
RETURN (dimensional_exponents(0, 0, 1, 1, 0, 0, 0));
volt :
RETURN (dimensional_exponents(2, 1, -3, -1, 0, 0, 0));
farad :
RETURN (dimensional_exponents(-2, -1, 4, 1, 0, 0, 0));
ohm :
RETURN (dimensional_exponents(2, 1, -3, -2, 0, 0, 0));
siemens :
RETURN (dimensional_exponents(-2, -1, 3, 2, 0, 0, 0));
weber :
RETURN (dimensional_exponents(2, 1, -2, -1, 0, 0, 0));
tesla :
RETURN (dimensional_exponents(0, 1, -2, -1, 0, 0, 0));
henry :
RETURN (dimensional_exponents(2, 1, -2, -2, 0, 0, 0));
degree_celsius :
RETURN (dimensional_exponents(0, 0, 0, 0, 1, 0, 0));
lumen :
RETURN (dimensional_exponents(0, 0, 0, 0, 0, 0, 1));
lux :
RETURN (dimensional_exponents(-2, 0, 0, 0, 0, 0, 1));
becquerel :
RETURN (dimensional_exponents(0, 0, -1, 0, 0, 0, 0));
gray :
RETURN (dimensional_exponents(2, 0, -2, 0, 0, 0, 0));
sievert :
RETURN (dimensional_exponents(2, 0, -2, 0, 0, 0, 0));
END_CASE;
END_FUNCTION;




FUNCTION dot_product
(
arg1 : direction;
 
arg2 : direction ) : REAL;
LOCAL

ndim : INTEGER;

scalar : REAL;

vec1 : direction;

vec2 : direction;
END_LOCAL;
IF NOT EXISTS(arg1) OR NOT EXISTS(arg2) THEN
scalar := ?;
ELSE
IF arg1.dim <> arg2.dim THEN
scalar := ?;
ELSE
BEGIN
vec1 := normalise(arg1);
vec2 := normalise(arg2);
ndim := arg1.dim;
scalar := 0;
REPEAT
 i := 1 TO ndim BY 1;
scalar := scalar + vec1.direction_ratios[i] * vec2.direction_ratios[i];
END_REPEAT;
END;
END_IF;
END_IF;
RETURN (scalar);
END_FUNCTION;




FUNCTION edge_reversed
(
an_edge : edge ) : oriented_edge;
LOCAL

the_reverse : oriented_edge;
END_LOCAL;
the_reverse.name := '';
the_reverse.edge_start := an_edge.edge_end;
the_reverse.edge_end := an_edge.edge_start;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ORIENTED_EDGE' IN TYPEOF(an_edge) THEN
the_reverse.edge_element := an_edge\oriented_edge.edge_element;
the_reverse.orientation := NOT an_edge\oriented_edge.orientation;
ELSE
the_reverse.edge_element := an_edge;
the_reverse.orientation := FALSE;
END_IF;
RETURN (the_reverse);
END_FUNCTION;




FUNCTION face_bound_reversed
(
a_face_bound : face_bound ) : face_bound;
LOCAL

the_reverse : face_bound;
END_LOCAL;
the_reverse.name := '';
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.FACE_OUTER_BOUND' IN TYPEOF(a_face_bound) THEN
the_reverse.bound := a_face_bound\face_bound.bound;
the_reverse.orientation := NOT a_face_bound\face_bound.orientation;
ELSE
the_reverse.bound := a_face_bound.bound;
the_reverse.orientation := NOT a_face_bound.orientation;
END_IF;
RETURN (the_reverse);
END_FUNCTION;




FUNCTION face_reversed
(
a_face : face ) : oriented_face;
LOCAL

the_reverse : oriented_face;
END_LOCAL;
the_reverse.name := '';
the_reverse.bounds := set_of_topology_reversed(a_face.bounds);
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ORIENTED_FACE' IN TYPEOF(a_face) THEN
the_reverse.face_element := a_face\oriented_face.face_element;
the_reverse.orientation := NOT a_face\oriented_face.orientation;
ELSE
the_reverse.face_element := a_face;
the_reverse.orientation := FALSE;
END_IF;
RETURN (the_reverse);
END_FUNCTION;




FUNCTION first_proj_axis
(
z_axis : direction;
 
arg : direction ) : direction;
LOCAL

x_vec : vector;

v : direction;

z : direction;

x_axis : direction;
END_LOCAL;
IF NOT EXISTS(z_axis) THEN
RETURN (?);
ELSE
z := normalise(z_axis);
IF NOT EXISTS(arg) THEN
IF z.direction_ratios <> [ 1, 0, 0 ] THEN
v := dummy_gri || direction([ 1, 0, 0 ]);
ELSE
v := dummy_gri || direction([ 0, 1, 0 ]);
END_IF;
ELSE
IF arg.dim <> 3 THEN
RETURN (?);
END_IF;
IF cross_product(arg, z).magnitude = 0 THEN
RETURN (?);
ELSE
v := normalise(arg);
END_IF;
END_IF;
x_vec := scalar_times_vector(dot_product(v, z), z);
x_axis := vector_difference(v, x_vec).orientation;
x_axis := normalise(x_axis);
END_IF;
RETURN (x_axis);
END_FUNCTION;




FUNCTION gbsf_check_curve
(
cv : curve ) : BOOLEAN;
IF SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.BOUNDED_CURVE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CONIC', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CURVE_REPLICA', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.LINE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.OFFSET_CURVE_3D' ] * TYPEOF(cv)) > 1 THEN
RETURN (FALSE);
ELSE
IF SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CIRCLE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ELLIPSE' ] * TYPEOF(cv)) = 1 THEN
RETURN (TRUE);
ELSE
IF ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.B_SPLINE_CURVE' IN TYPEOF(cv)) AND (cv\b_spline_curve.self_intersect = FALSE) THEN
RETURN (TRUE);
ELSE
IF ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.COMPOSITE_CURVE' IN TYPEOF(cv)) AND (cv\composite_curve.self_intersect = FALSE) THEN
RETURN (SIZEOF(
QUERY (seg <* cv\composite_curve.segments| NOT gbsf_check_curve(seg.parent_curve))) = 0);
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CURVE_REPLICA' IN TYPEOF(cv) THEN
RETURN (gbsf_check_curve(cv\curve_replica.parent_curve));
ELSE
IF ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.OFFSET_CURVE_3D' IN TYPEOF(cv)) AND (cv\offset_curve_3d.self_intersect = FALSE) THEN
RETURN (gbsf_check_curve(cv\offset_curve_3d.basis_curve));
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PCURVE' IN TYPEOF(cv) THEN
RETURN (gbsf_check_curve(cv\pcurve.reference_to_curve\representation.items[1]) AND gbsf_check_surface(cv\pcurve.basis_surface));
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POLYLINE' IN TYPEOF(cv) THEN
IF (SIZEOF(cv\polyline.points) >= 3) AND (SIZEOF(bag_to_set(USEDIN(cv, '')) - bag_to_set(USEDIN(cv, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SURFACE_CURVE.CURVE_3D'))) = 0) THEN
RETURN (TRUE);
END_IF;
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SURFACE_CURVE' IN TYPEOF(cv) THEN
IF gbsf_check_curve(cv\surface_curve.curve_3d) THEN
REPEAT
 i := 1 TO SIZEOF(cv\surface_curve.associated_geometry) BY 1;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SURFACE' IN TYPEOF(cv\surface_curve.associated_geometry[i]) THEN
IF NOT gbsf_check_surface(cv\surface_curve.associated_geometry[i]) THEN
RETURN (FALSE);
END_IF;
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PCURVE' IN TYPEOF(cv\surface_curve.associated_geometry[i]) THEN
IF NOT gbsf_check_curve(cv\surface_curve.associated_geometry[i]) THEN
RETURN (FALSE);
END_IF;
END_IF;
END_IF;
END_REPEAT;
RETURN (TRUE);
END_IF;
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.TRIMMED_CURVE' IN TYPEOF(cv) THEN
IF SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.LINE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PARABOLA', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.HYPERBOLA' ] * TYPEOF(cv\trimmed_curve.basis_curve)) = 1 THEN
RETURN (TRUE);
ELSE
RETURN (gbsf_check_curve(cv\trimmed_curve.basis_curve));
END_IF;
END_IF;
END_IF;
END_IF;
END_IF;
END_IF;
END_IF;
END_IF;
END_IF;
END_IF;
END_IF;
RETURN (FALSE);
END_FUNCTION;




FUNCTION gbsf_check_point
(
pnt : point ) : BOOLEAN;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CARTESIAN_POINT' IN TYPEOF(pnt) THEN
RETURN (TRUE);
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POINT_ON_CURVE' IN TYPEOF(pnt) THEN
RETURN (gbsf_check_curve(pnt\point_on_curve.basis_curve));
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POINT_ON_SURFACE' IN TYPEOF(pnt) THEN
RETURN (gbsf_check_surface(pnt\point_on_surface.basis_surface));
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.DEGENERATE_PCURVE' IN TYPEOF(pnt) THEN
RETURN (gbsf_check_curve(pnt\degenerate_pcurve.reference_to_curve\representation.items[1]) AND gbsf_check_surface(pnt\degenerate_pcurve.basis_surface));
END_IF;
END_IF;
END_IF;
END_IF;
RETURN (FALSE);
END_FUNCTION;




FUNCTION gbsf_check_surface
(
sf : surface ) : BOOLEAN;
IF ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.B_SPLINE_SURFACE' IN TYPEOF(sf)) AND (sf\b_spline_surface.self_intersect = FALSE) THEN
RETURN (TRUE);
ELSE
IF SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SPHERICAL_SURFACE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.TOROIDAL_SURFACE' ] * TYPEOF(sf)) = 1 THEN
RETURN (TRUE);
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CURVE_BOUNDED_SURFACE' IN TYPEOF(sf) THEN
IF SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CONICAL_SURFACE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CYLINDRICAL_SURFACE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PLANE' ] * TYPEOF(sf\curve_bounded_surface.basis_surface)) = 1 THEN
RETURN (SIZEOF(
QUERY (bcurve <* sf\curve_bounded_surface.boundaries| NOT gbsf_check_curve(bcurve))) = 0);
ELSE
IF gbsf_check_surface(sf\curve_bounded_surface.basis_surface) THEN
RETURN (SIZEOF(
QUERY (bcurve <* sf\curve_bounded_surface.boundaries| NOT gbsf_check_curve(bcurve))) = 0);
END_IF;
END_IF;
ELSE
IF ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.OFFSET_SURFACE' IN TYPEOF(sf)) AND (sf\offset_surface.self_intersect = FALSE) THEN
RETURN (gbsf_check_surface(sf\offset_surface.basis_surface));
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.RECTANGULAR_COMPOSITE_SURFACE' IN TYPEOF(sf) THEN
REPEAT
 i := 1 TO SIZEOF(sf\rectangular_composite_surface.segments) BY 1;
REPEAT
 j := 1 TO SIZEOF(sf\rectangular_composite_surface.segments[i]) BY 1;
IF NOT gbsf_check_surface(sf\rectangular_composite_surface.segments[i][j].parent_surface) THEN
RETURN (FALSE);
END_IF;
END_REPEAT;
END_REPEAT;
RETURN (TRUE);
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.RECTANGULAR_TRIMMED_SURFACE' IN TYPEOF(sf) THEN
IF SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CONICAL_SURFACE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CYLINDRICAL_SURFACE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PLANE' ] * TYPEOF(sf\rectangular_trimmed_surface.basis_surface)) = 1 THEN
RETURN (TRUE);
ELSE
RETURN (gbsf_check_surface(sf\rectangular_trimmed_surface.basis_surface));
END_IF;
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SURFACE_REPLICA' IN TYPEOF(sf) THEN
RETURN (gbsf_check_surface(sf\surface_replica.parent_surface));
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SWEPT_SURFACE' IN TYPEOF(sf) THEN
RETURN (gbsf_check_curve(sf\swept_surface.swept_curve));
END_IF;
END_IF;
END_IF;
END_IF;
END_IF;
END_IF;
END_IF;
END_IF;
RETURN (FALSE);
END_FUNCTION;




FUNCTION get_basis_surface
(
c : curve_on_surface ) : SET [0:2] OF surface;
LOCAL

surfs : SET [0:2] OF surface;

n : INTEGER;
END_LOCAL;
surfs := [];
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PCURVE' IN TYPEOF(c) THEN
surfs := [ c\pcurve.basis_surface ];
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SURFACE_CURVE' IN TYPEOF(c) THEN
n := SIZEOF(c\surface_curve.associated_geometry);
REPEAT
 i := 1 TO n BY 1;
surfs := surfs + associated_surface(c\surface_curve.associated_geometry[i]);
END_REPEAT;
END_IF;
END_IF;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.COMPOSITE_CURVE_ON_SURFACE' IN TYPEOF(c) THEN
n := SIZEOF(c\composite_curve_on_surface.segments);
surfs := get_basis_surface(c\composite_curve_on_surface.segments[1].parent_curve);
IF n > 1 THEN
REPEAT
 i := 2 TO n BY 1;
surfs := surfs * get_basis_surface(c\composite_curve_on_surface.segments[i].parent_curve);
END_REPEAT;
END_IF;
END_IF;
RETURN (surfs);
END_FUNCTION;




FUNCTION item_in_context
(
item : representation_item;
 
cntxt : representation_context ) : BOOLEAN;
LOCAL

i : INTEGER;

y : BAG OF representation_item;
END_LOCAL;
IF SIZEOF(USEDIN(item, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.REPRESENTATION.ITEMS') * cntxt.representations_in_context) > 0 THEN
RETURN (TRUE);
ELSE
y := 
QUERY (z <* USEDIN(item, '')| 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.REPRESENTATION_ITEM' IN TYPEOF(z));
IF SIZEOF(y) > 0 THEN
REPEAT
 i := 1 TO HIINDEX(y) BY 1;
IF item_in_context(y[i], cntxt) THEN
RETURN (TRUE);
END_IF;
END_REPEAT;
END_IF;
END_IF;
RETURN (FALSE);
END_FUNCTION;




FUNCTION leap_year
(
year : year_number ) : BOOLEAN;
IF (year MOD 4 = 0) AND (year MOD 100 <> 0) OR (year MOD 400 = 0) THEN
RETURN (TRUE);
ELSE
RETURN (FALSE);
END_IF;
END_FUNCTION;




FUNCTION list_face_loops
(
f : face ) : LIST [0:?] OF loop;
LOCAL

loops : LIST [0:?] OF loop := [];
END_LOCAL;
REPEAT
 i := 1 TO SIZEOF(f.bounds) BY 1;
loops := loops + f.bounds[i].bound;
END_REPEAT;
RETURN (loops);
END_FUNCTION;




FUNCTION list_of_topology_reversed
(
a_list : list_of_reversible_topology_item ) : list_of_reversible_topology_item;
LOCAL

the_reverse : list_of_reversible_topology_item;
END_LOCAL;
the_reverse := [];
REPEAT
 i := 1 TO SIZEOF(a_list) BY 1;
the_reverse := topology_reversed(a_list[i]) + the_reverse;
END_REPEAT;
RETURN (the_reverse);
END_FUNCTION;




FUNCTION list_to_array
(
lis : LIST [0:?] OF GENERIC : t;
 
low : INTEGER;
 
u : INTEGER ) : ARRAY [low:u] OF GENERIC : t;
LOCAL

n : INTEGER;

res : ARRAY [low:u] OF GENERIC : t;
END_LOCAL;
n := SIZEOF(lis);
IF n <> u - low + 1 THEN
RETURN (?);
ELSE
REPEAT
 i := 1 TO n BY 1;
res[(low + i - 1)] := lis[i];
END_REPEAT;
RETURN (res);
END_IF;
END_FUNCTION;




FUNCTION list_to_set
(
l : LIST [0:?] OF GENERIC : t ) : SET OF GENERIC : t;
LOCAL

s : SET OF GENERIC : t := [];
END_LOCAL;
REPEAT
 i := 1 TO SIZEOF(l) BY 1;
s := s + l[i];
END_REPEAT;
RETURN (s);
END_FUNCTION;




FUNCTION make_array_of_array
(
lis : LIST [1:?] OF LIST [1:?] OF GENERIC : t;
 
low1 : INTEGER;
 
u1 : INTEGER;
 
low2 : INTEGER;
 
u2 : INTEGER ) : ARRAY [low1:u1] OF ARRAY [low2:u2] OF GENERIC : t;
LOCAL

n2 : INTEGER;

n1 : INTEGER;

res : ARRAY [low1:u1] OF ARRAY [low2:u2] OF GENERIC : t;

resl : LIST [1:?] OF ARRAY [low2:u2] OF GENERIC : t;
END_LOCAL;
n1 := SIZEOF(lis);
n2 := SIZEOF(lis[1]);
IF (n1 <> u1 - low1 + 1) AND (n2 <> u2 - low2 + 1) THEN
RETURN (?);
END_IF;
REPEAT
 i := 1 TO n1 BY 1;
IF SIZEOF(lis[i]) <> n2 THEN
RETURN (?);
END_IF;
END_REPEAT;
REPEAT
 i := 1 TO n1 BY 1;
resl[i] := list_to_array(lis[i], low2, u2);
END_REPEAT;
res := list_to_array(resl, low1, u1);
RETURN (res);
END_FUNCTION;




FUNCTION mixed_loop_type_set
(
l : SET [0:?] OF loop ) : LOGICAL;
LOCAL

i : INTEGER;

poly_loop_type : LOGICAL;
END_LOCAL;
IF SIZEOF(l) <= 1 THEN
RETURN (FALSE);
END_IF;
poly_loop_type := 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POLY_LOOP' IN TYPEOF(l[1]);
REPEAT
 i := 2 TO SIZEOF(l) BY 1;
IF ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POLY_LOOP' IN TYPEOF(l[i])) <> poly_loop_type THEN
RETURN (TRUE);
END_IF;
END_REPEAT;
RETURN (FALSE);
END_FUNCTION;




FUNCTION msb_shells
(
brep : manifold_solid_brep;
 
schema_name : STRING ) : SET [1:?] OF closed_shell;
IF schema_name + '.BREP_WITH_VOIDS' IN TYPEOF(brep) THEN
RETURN (brep\brep_with_voids.voids + brep.outer);
ELSE
RETURN ([ brep.outer ]);
END_IF;
END_FUNCTION;




FUNCTION msf_curve_check
(
cv : curve ) : BOOLEAN;
IF SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.BOUNDED_CURVE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CONIC', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CURVE_REPLICA', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.LINE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.OFFSET_CURVE_3D' ] * TYPEOF(cv)) > 1 THEN
RETURN (FALSE);
ELSE
IF ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.B_SPLINE_CURVE' IN TYPEOF(cv)) AND (cv\b_spline_curve.self_intersect = FALSE) THEN
RETURN (TRUE);
ELSE
IF SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CONIC', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.LINE' ] * TYPEOF(cv)) = 1 THEN
RETURN (TRUE);
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CURVE_REPLICA' IN TYPEOF(cv) THEN
RETURN (msf_curve_check(cv\curve_replica.parent_curve));
ELSE
IF ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.OFFSET_CURVE_3D' IN TYPEOF(cv)) AND (cv\offset_curve_3d.self_intersect = FALSE) THEN
RETURN (msf_curve_check(cv\offset_curve_3d.basis_curve));
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PCURVE' IN TYPEOF(cv) THEN
RETURN (msf_curve_check(cv\pcurve.reference_to_curve\representation.items[1]) AND msf_surface_check(cv\pcurve.basis_surface));
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SURFACE_CURVE' IN TYPEOF(cv) THEN
IF msf_curve_check(cv\surface_curve.curve_3d) THEN
REPEAT
 i := 1 TO SIZEOF(cv\surface_curve.associated_geometry) BY 1;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SURFACE' IN TYPEOF(cv\surface_curve.associated_geometry[i]) THEN
IF NOT msf_surface_check(cv\surface_curve.associated_geometry[i]) THEN
RETURN (FALSE);
END_IF;
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PCURVE' IN TYPEOF(cv\surface_curve.associated_geometry[i]) THEN
IF NOT msf_curve_check(cv\surface_curve.associated_geometry[i]) THEN
RETURN (FALSE);
END_IF;
END_IF;
END_IF;
END_REPEAT;
RETURN (TRUE);
END_IF;
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POLYLINE' IN TYPEOF(cv) THEN
IF SIZEOF(cv\polyline.points) >= 3 THEN
RETURN (TRUE);
END_IF;
END_IF;
END_IF;
END_IF;
END_IF;
END_IF;
END_IF;
END_IF;
END_IF;
RETURN (FALSE);
END_FUNCTION;




FUNCTION msf_surface_check
(
surf : surface ) : BOOLEAN;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ELEMENTARY_SURFACE' IN TYPEOF(surf) THEN
RETURN (TRUE);
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SWEPT_SURFACE' IN TYPEOF(surf) THEN
RETURN (msf_curve_check(surf\swept_surface.swept_curve));
ELSE
IF ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.OFFSET_SURFACE' IN TYPEOF(surf)) AND (surf\offset_surface.self_intersect = FALSE) THEN
RETURN (msf_surface_check(surf\offset_surface.basis_surface));
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SURFACE_REPLICA' IN TYPEOF(surf) THEN
RETURN (msf_surface_check(surf\surface_replica.parent_surface));
ELSE
IF ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.B_SPLINE_SURFACE' IN TYPEOF(surf)) AND (surf\b_spline_surface.self_intersect = FALSE) THEN
RETURN (TRUE);
END_IF;
END_IF;
END_IF;
END_IF;
END_IF;
RETURN (FALSE);
END_FUNCTION;




FUNCTION normalise
(
arg : vector_or_direction ) : vector_or_direction;
LOCAL

ndim : INTEGER;

v : direction;

vec : vector;

mag : REAL;

result : vector_or_direction;
END_LOCAL;
IF NOT EXISTS(arg) THEN
result := ?;
ELSE
ndim := arg.dim;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VECTOR' IN TYPEOF(arg) THEN
BEGIN
vec := arg;
v := arg.orientation;
IF arg.magnitude = 0 THEN
RETURN (?);
ELSE
vec.magnitude := 1;
END_IF;
END;
ELSE
v := arg;
END_IF;
mag := 0;
REPEAT
 i := 1 TO ndim BY 1;
mag := mag + v.direction_ratios[i] * v.direction_ratios[i];
END_REPEAT;
IF mag > 0 THEN
mag := SQRT(mag);
REPEAT
 i := 1 TO ndim BY 1;
v.direction_ratios[i] := v.direction_ratios[i] / mag;
END_REPEAT;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VECTOR' IN TYPEOF(arg) THEN
vec.orientation := v;
result := vec;
ELSE
result := v;
END_IF;
ELSE
RETURN (?);
END_IF;
END_IF;
RETURN (result);
END_FUNCTION;




FUNCTION orthogonal_complement
(
vec : direction ) : direction;
LOCAL

result : direction;
END_LOCAL;
IF (vec.dim <> 2) OR NOT EXISTS(vec) THEN
RETURN (?);
ELSE
result.name := '';
result.direction_ratios[1] := -vec.direction_ratios[2];
result.direction_ratios[2] := vec.direction_ratios[1];
RETURN (result);
END_IF;
END_FUNCTION;




FUNCTION path_head_to_tail
(
a_path : path ) : LOGICAL;
LOCAL

n : INTEGER;

p : BOOLEAN := TRUE;
END_LOCAL;
n := SIZEOF(a_path.edge_list);
REPEAT
 i := 2 TO n BY 1;
p := p AND (a_path.edge_list[(i - 1)].edge_end :=: a_path.edge_list[i].edge_start);
END_REPEAT;
RETURN (p);
END_FUNCTION;




FUNCTION path_reversed
(
a_path : path ) : oriented_path;
LOCAL

the_reverse : oriented_path;
END_LOCAL;
the_reverse.name := '';
the_reverse.edge_list := list_of_topology_reversed(path.edge_list);
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ORIENTED_PATH' IN TYPEOF(a_path) THEN
the_reverse.path_element := a_path\oriented_path.path_element;
the_reverse.orientation := NOT a_path\oriented_path.orientation;
ELSE
the_reverse.path_element := a_path;
the_reverse.orientation := FALSE;
END_IF;
RETURN (the_reverse);
END_FUNCTION;




FUNCTION scalar_times_vector
(
scalar : REAL;
 
vec : vector_or_direction ) : vector;
LOCAL

v : direction;

mag : REAL;

result : vector;
END_LOCAL;
IF NOT EXISTS(scalar) OR NOT EXISTS(vec) THEN
RETURN (?);
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VECTOR' IN TYPEOF(vec) THEN
v := vec.orientation;
mag := scalar * vec.magnitude;
ELSE
v := vec;
mag := scalar;
END_IF;
IF mag < 0 THEN
REPEAT
 i := 1 TO SIZEOF(v.direction_ratios) BY 1;
v.direction_ratios[i] := -v.direction_ratios[i];
END_REPEAT;
mag := -mag;
END_IF;
result.name := '';
result.orientation := normalise(v);
result.magnitude := mag;
END_IF;
RETURN (result);
END_FUNCTION;




FUNCTION second_proj_axis
(
z_axis : direction;
 
x_axis : direction;
 
arg : direction ) : direction;
LOCAL

temp : vector;

v : direction;

y_axis : vector;
END_LOCAL;
IF NOT EXISTS(arg) THEN
v := dummy_gri || direction([ 0, 1, 0 ]);
ELSE
v := arg;
END_IF;
temp := scalar_times_vector(dot_product(v, z_axis), z_axis);
y_axis := vector_difference(v, temp);
temp := scalar_times_vector(dot_product(v, x_axis), x_axis);
y_axis := vector_difference(y_axis, temp);
y_axis := normalise(y_axis);
RETURN (y_axis.orientation);
END_FUNCTION;




FUNCTION set_of_topology_reversed
(
a_set : set_of_reversible_topology_item ) : set_of_reversible_topology_item;
LOCAL

the_reverse : set_of_reversible_topology_item;
END_LOCAL;
the_reverse := [];
REPEAT
 i := 1 TO SIZEOF(a_set) BY 1;
the_reverse := the_reverse + topology_reversed(a_set[i]);
END_REPEAT;
RETURN (the_reverse);
END_FUNCTION;




FUNCTION shell_reversed
(
a_shell : shell ) : shell;
LOCAL

the_reverse : shell;
END_LOCAL;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ORIENTED_OPEN_SHELL' IN TYPEOF(a_shell) THEN
the_reverse := representation_item('') || topological_representation_item() || connected_face_set(set_of_topology_reversed(a_shell\connected_face_set.cfs_faces)) || open_shell() || oriented_open_shell(a_shell\oriented_open_shell.open_shell_element, NOT a_shell\oriented_open_shell.orientation);
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.OPEN_SHELL' IN TYPEOF(a_shell) THEN
the_reverse := representation_item('') || topological_representation_item() || connected_face_set(set_of_topology_reversed(a_shell\connected_face_set.cfs_faces)) || open_shell() || oriented_open_shell(a_shell, FALSE);
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ORIENTED_CLOSED_SHELL' IN TYPEOF(a_shell) THEN
the_reverse := representation_item('') || topological_representation_item() || connected_face_set(set_of_topology_reversed(a_shell\connected_face_set.cfs_faces)) || closed_shell() || oriented_closed_shell(a_shell\oriented_closed_shell.closed_shell_element, NOT a_shell\oriented_closed_shell.orientation);
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CLOSED_SHELL' IN TYPEOF(a_shell) THEN
the_reverse := representation_item('') || topological_representation_item() || connected_face_set(set_of_topology_reversed(a_shell\connected_face_set.cfs_faces)) || closed_shell() || oriented_closed_shell(a_shell, FALSE);
ELSE
RETURN (?);
END_IF;
END_IF;
END_IF;
END_IF;
RETURN (the_reverse);
END_FUNCTION;




FUNCTION surface_weights_positive
(
b : rational_b_spline_surface ) : BOOLEAN;
LOCAL

result : BOOLEAN := TRUE;
END_LOCAL;
REPEAT
 i := 0 TO b.u_upper BY 1;
REPEAT
 j := 0 TO b.v_upper BY 1;
IF b.weights[i][j] <= 0 THEN
result := FALSE;
RETURN (result);
END_IF;
END_REPEAT;
END_REPEAT;
RETURN (result);
END_FUNCTION;




FUNCTION topology_reversed
(
an_item : reversible_topology ) : reversible_topology;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.EDGE' IN TYPEOF(an_item) THEN
RETURN (edge_reversed(an_item));
END_IF;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PATH' IN TYPEOF(an_item) THEN
RETURN (path_reversed(an_item));
END_IF;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.FACE_BOUND' IN TYPEOF(an_item) THEN
RETURN (face_bound_reversed(an_item));
END_IF;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.FACE' IN TYPEOF(an_item) THEN
RETURN (face_reversed(an_item));
END_IF;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SHELL' IN TYPEOF(an_item) THEN
RETURN (shell_reversed(an_item));
END_IF;
IF 'SET' IN TYPEOF(an_item) THEN
RETURN (set_of_topology_reversed(an_item));
END_IF;
IF 'LIST' IN TYPEOF(an_item) THEN
RETURN (list_of_topology_reversed(an_item));
END_IF;
RETURN (?);
END_FUNCTION;




FUNCTION unique_version_change_order
(
c : action;
 
schema_name : STRING ) : BOOLEAN;
LOCAL

ords : action_directive := c\directed_action.directive;

assign : SET OF action_request_assignment := [];

versions : SET OF product_definition_formation := [];
END_LOCAL;
REPEAT
 i := 1 TO SIZEOF(ords.requests) BY 1;
assign := assign + 
QUERY (ara <* bag_to_set(USEDIN(ords.requests[i], schema_name + '.ACTION_REQUEST_ASSIGNMENT.' + 'ASSIGNED_ACTION_REQUEST'))| (schema_name + '.CHANGE_REQUEST' IN TYPEOF(ara)));
END_REPEAT;
REPEAT
 k := 1 TO SIZEOF(assign) BY 1;
versions := versions + assign[k]\change_request.items;
END_REPEAT;
RETURN (SIZEOF(
QUERY (vers <* versions| NOT (SIZEOF(
QUERY (other_vers <* versions - vers| (vers.of_product :=: other_vers.of_product))) = 0))) = 0);
END_FUNCTION;




FUNCTION using_representations
(
item : representation_item ) : SET OF representation;
LOCAL

results : SET OF representation;

i : INTEGER;

intermediate_items : SET OF representation_item;

result_bag : BAG OF representation;
END_LOCAL;
result_bag := USEDIN(item, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.REPRESENTATION.ITEMS');
IF SIZEOF(result_bag) > 0 THEN
REPEAT
 i := 1 TO HIINDEX(result_bag) BY 1;
results := results + result_bag[i];
END_REPEAT;
END_IF;
intermediate_items := 
QUERY (z <* bag_to_set(USEDIN(item, ''))| 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.REPRESENTATION_ITEM' IN TYPEOF(z));
IF SIZEOF(intermediate_items) > 0 THEN
REPEAT
 i := 1 TO HIINDEX(intermediate_items) BY 1;
results := results + using_representations(intermediate_items[i]);
END_REPEAT;
END_IF;
RETURN (results);
END_FUNCTION;




FUNCTION valid_2d_wireframe_edge_curve
(
crv : curve;
 
schma : STRING ) : BOOLEAN;
IF SIZEOF([ (schma + '.LINE'), (schma + '.B_SPLINE_CURVE'), (schma + '.CIRCLE'), (schma + '.HYPERBOLA'), (schma + '.ELLIPSE'), (schma + '.PARABOLA'), (schma + '.POLYLINE') ] * TYPEOF(crv)) = 1 THEN
RETURN (TRUE);
ELSE
IF schma + '.CURVE_REPLICA' IN TYPEOF(crv) THEN
RETURN (valid_2d_wireframe_edge_curve(crv\curve_replica.parent_curve, schma));
ELSE
IF schma + '.OFFSET_CURVE_2D' IN TYPEOF(crv) THEN
RETURN (valid_2d_wireframe_edge_curve(crv\offset_curve_2d.basis_curve, schma));
END_IF;
END_IF;
END_IF;
RETURN (FALSE);
END_FUNCTION;




FUNCTION valid_basis_curve_in_2d_wireframe
(
crv : curve;
 
schma : STRING ) : BOOLEAN;
IF schma + '.TRIMMED_CURVE' IN TYPEOF(crv) THEN
RETURN (valid_basis_curve_in_2d_wireframe(crv\trimmed_curve.basis_curve, schma));
ELSE
IF schma + '.COMPOSITE_CURVE' IN TYPEOF(crv) THEN
RETURN (SIZEOF(
QUERY (ccs <* crv\composite_curve.segments| NOT valid_basis_curve_in_2d_wireframe(ccs.parent_curve, schma))) = 0);
ELSE
IF schma + '.OFFSET_CURVE_2D' IN TYPEOF(crv) THEN
RETURN (valid_basis_curve_in_2d_wireframe(crv\offset_curve_2d.basis_curve, schma));
ELSE
IF SIZEOF([ (schma + '.LINE'), (schma + '.B_SPLINE_CURVE'), (schma + '.CIRCLE'), (schma + '.ELLIPSE'), (schma + '.HYPERBOLA'), (schma + '.PARABOLA'), (schma + '.POLYLINE') ] * TYPEOF(crv)) = 1 THEN
RETURN (TRUE);
END_IF;
END_IF;
END_IF;
END_IF;
RETURN (FALSE);
END_FUNCTION;




FUNCTION valid_calendar_date
(
date : calendar_date ) : LOGICAL;
IF NOT ((1 <= date.day_component) AND (date.day_component <= 31)) THEN
RETURN (FALSE);
END_IF;
CASE date.month_component OF
4 :
RETURN ((1 <= date.day_component) AND (date.day_component <= 30));
6 :
RETURN ((1 <= date.day_component) AND (date.day_component <= 30));
9 :
RETURN ((1 <= date.day_component) AND (date.day_component <= 30));
11 :
RETURN ((1 <= date.day_component) AND (date.day_component <= 30));
2 :
BEGIN
IF leap_year(date.year_component) THEN
RETURN ((1 <= date.day_component) AND (date.day_component <= 29));
ELSE
RETURN ((1 <= date.day_component) AND (date.day_component <= 28));
END_IF;
END;
OTHERWISE :
RETURN (TRUE);
END_CASE;
END_FUNCTION;




FUNCTION valid_geometrically_bounded_wf_curve
(
crv : curve ) : BOOLEAN;
IF SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POLYLINE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.B_SPLINE_CURVE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ELLIPSE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CIRCLE' ] * TYPEOF(crv)) = 1 THEN
RETURN (TRUE);
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.TRIMMED_CURVE' IN TYPEOF(crv) THEN
IF SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.LINE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PARABOLA', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.HYPERBOLA' ] * TYPEOF(crv\trimmed_curve.basis_curve)) = 1 THEN
RETURN (TRUE);
ELSE
RETURN (valid_geometrically_bounded_wf_curve(crv\trimmed_curve.basis_curve));
END_IF;
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.OFFSET_CURVE_3D' IN TYPEOF(crv) THEN
RETURN (valid_geometrically_bounded_wf_curve(crv\offset_curve_3d.basis_curve));
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CURVE_REPLICA' IN TYPEOF(crv) THEN
RETURN (valid_geometrically_bounded_wf_curve(crv\curve_replica.parent_curve));
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.COMPOSITE_CURVE' IN TYPEOF(crv) THEN
RETURN (SIZEOF(
QUERY (ccs <* crv\composite_curve.segments| NOT valid_geometrically_bounded_wf_curve(ccs.parent_curve))) = 0);
END_IF;
END_IF;
END_IF;
END_IF;
END_IF;
RETURN (FALSE);
END_FUNCTION;




FUNCTION valid_geometrically_bounded_wf_point
(
pnt : point ) : BOOLEAN;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CARTESIAN_POINT' IN TYPEOF(pnt) THEN
RETURN (TRUE);
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POINT_ON_CURVE' IN TYPEOF(pnt) THEN
RETURN (valid_geometrically_bounded_wf_curve(pnt\point_on_curve.basis_curve));
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POINT_REPLICA' IN TYPEOF(pnt) THEN
RETURN (valid_geometrically_bounded_wf_point(pnt\point_replica.parent_pt));
END_IF;
END_IF;
END_IF;
RETURN (FALSE);
END_FUNCTION;




FUNCTION valid_time
(
time : local_time ) : BOOLEAN;
IF EXISTS(time.second_component) THEN
RETURN (EXISTS(time.minute_component));
ELSE
RETURN (TRUE);
END_IF;
END_FUNCTION;




FUNCTION valid_units
(
m : measure_with_unit ) : BOOLEAN;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.LENGTH_MEASURE' IN TYPEOF(m.value_component) THEN
IF derive_dimensional_exponents(m.unit_component) <> dimensional_exponents(1, 0, 0, 0, 0, 0, 0) THEN
RETURN (FALSE);
END_IF;
END_IF;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.MASS_MEASURE' IN TYPEOF(m.value_component) THEN
IF derive_dimensional_exponents(m.unit_component) <> dimensional_exponents(0, 1, 0, 0, 0, 0, 0) THEN
RETURN (FALSE);
END_IF;
END_IF;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.TIME_MEASURE' IN TYPEOF(m.value_component) THEN
IF derive_dimensional_exponents(m.unit_component) <> dimensional_exponents(0, 0, 1, 0, 0, 0, 0) THEN
RETURN (FALSE);
END_IF;
END_IF;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.ELECTRIC_CURRENT_MEASURE' IN TYPEOF(m.value_component) THEN
IF derive_dimensional_exponents(m.unit_component) <> dimensional_exponents(0, 0, 0, 1, 0, 0, 0) THEN
RETURN (FALSE);
END_IF;
END_IF;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.THERMODYNAMIC_TEMPERATURE_MEASURE' IN TYPEOF(m.value_component) THEN
IF derive_dimensional_exponents(m.unit_component) <> dimensional_exponents(0, 0, 0, 0, 1, 0, 0) THEN
RETURN (FALSE);
END_IF;
END_IF;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AMOUNT_OF_SUBSTANCE_MEASURE' IN TYPEOF(m.value_component) THEN
IF derive_dimensional_exponents(m.unit_component) <> dimensional_exponents(0, 0, 0, 0, 0, 1, 0) THEN
RETURN (FALSE);
END_IF;
END_IF;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.LUMINOUS_INTENSITY_MEASURE' IN TYPEOF(m.value_component) THEN
IF derive_dimensional_exponents(m.unit_component) <> dimensional_exponents(0, 0, 0, 0, 0, 0, 1) THEN
RETURN (FALSE);
END_IF;
END_IF;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PLANE_ANGLE_MEASURE' IN TYPEOF(m.value_component) THEN
IF derive_dimensional_exponents(m.unit_component) <> dimensional_exponents(0, 0, 0, 0, 0, 0, 0) THEN
RETURN (FALSE);
END_IF;
END_IF;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SOLID_ANGLE_MEASURE' IN TYPEOF(m.value_component) THEN
IF derive_dimensional_exponents(m.unit_component) <> dimensional_exponents(0, 0, 0, 0, 0, 0, 0) THEN
RETURN (FALSE);
END_IF;
END_IF;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.AREA_MEASURE' IN TYPEOF(m.value_component) THEN
IF derive_dimensional_exponents(m.unit_component) <> dimensional_exponents(2, 0, 0, 0, 0, 0, 0) THEN
RETURN (FALSE);
END_IF;
END_IF;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VOLUME_MEASURE' IN TYPEOF(m.value_component) THEN
IF derive_dimensional_exponents(m.unit_component) <> dimensional_exponents(3, 0, 0, 0, 0, 0, 0) THEN
RETURN (FALSE);
END_IF;
END_IF;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.RATIO_MEASURE' IN TYPEOF(m.value_component) THEN
IF derive_dimensional_exponents(m.unit_component) <> dimensional_exponents(0, 0, 0, 0, 0, 0, 0) THEN
RETURN (FALSE);
END_IF;
END_IF;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POSITIVE_LENGTH_MEASURE' IN TYPEOF(m.value_component) THEN
IF derive_dimensional_exponents(m.unit_component) <> dimensional_exponents(1, 0, 0, 0, 0, 0, 0) THEN
RETURN (FALSE);
END_IF;
END_IF;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POSITIVE_PLANE_ANGLE_MEASURE' IN TYPEOF(m.value_component) THEN
IF derive_dimensional_exponents(m.unit_component) <> dimensional_exponents(0, 0, 0, 0, 0, 0, 0) THEN
RETURN (FALSE);
END_IF;
END_IF;
RETURN (TRUE);
END_FUNCTION;




FUNCTION valid_wireframe_edge_curve
(
crv : curve ) : BOOLEAN;
IF SIZEOF([ 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.LINE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CONIC', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.B_SPLINE_CURVE', 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POLYLINE' ] * TYPEOF(crv)) = 1 THEN
RETURN (TRUE);
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CURVE_REPLICA' IN TYPEOF(crv) THEN
RETURN (valid_wireframe_edge_curve(crv\curve_replica.parent_curve));
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.OFFSET_CURVE_3D' IN TYPEOF(crv) THEN
RETURN (valid_wireframe_edge_curve(crv\offset_curve_3d.basis_curve));
END_IF;
END_IF;
END_IF;
RETURN (FALSE);
END_FUNCTION;




FUNCTION valid_wireframe_vertex_point
(
pnt : point;
 
schma : STRING ) : BOOLEAN;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CARTESIAN_POINT' IN TYPEOF(pnt) THEN
RETURN (TRUE);
ELSE
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.POINT_REPLICA' IN TYPEOF(pnt) THEN
RETURN (valid_wireframe_vertex_point(pnt\point_replica.parent_pt, schma));
END_IF;
END_IF;
RETURN (FALSE);
END_FUNCTION;




FUNCTION vector_difference
(
arg1 : vector_or_direction;
 
arg2 : vector_or_direction ) : vector;
LOCAL

ndim : INTEGER;

mag2 : REAL;

mag1 : REAL;

mag : REAL;

res : direction;

vec1 : direction;

vec2 : direction;

result : vector;
END_LOCAL;
IF (NOT EXISTS(arg1) OR NOT EXISTS(arg2)) OR (arg1.dim <> arg2.dim) THEN
RETURN (?);
ELSE
BEGIN
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VECTOR' IN TYPEOF(arg1) THEN
mag1 := arg1.magnitude;
vec1 := arg1.orientation;
ELSE
mag1 := 1;
vec1 := arg1;
END_IF;
IF 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.VECTOR' IN TYPEOF(arg2) THEN
mag2 := arg2.magnitude;
vec2 := arg2.orientation;
ELSE
mag2 := 1;
vec2 := arg2;
END_IF;
vec1 := normalise(vec1);
vec2 := normalise(vec2);
ndim := SIZEOF(vec1.direction_ratios);
mag := 0;
REPEAT
 i := 1 TO ndim BY 1;
res.direction_ratios[i] := mag1 * vec1.direction_ratios[i] - mag2 * vec2.direction_ratios[i];
mag := mag + res.direction_ratios[i] * res.direction_ratios[i];
END_REPEAT;
IF mag > 0 THEN
result.magnitude := SQRT(mag);
result.orientation := res;
ELSE
result.magnitude := 0;
result.orientation := vec1;
END_IF;
END;
END_IF;
result.name := '';
RETURN (result);
END_FUNCTION;





***********************************



RULE acu_requires_security_classification FOR (
assembly_component_usage, 
applied_security_classification_assignment );
WHERE

wr1:
SIZEOF(
QUERY (acu <* assembly_component_usage| NOT (SIZEOF(
QUERY (asca <* applied_security_classification_assignment| (acu IN asca.items))) = 1))) = 0;
END_RULE;




RULE adjacent_stratum_surface_definition_constraint FOR (
shape_aspect_relationship );
WHERE

wr1:
SIZEOF(
QUERY (sar <* shape_aspect_relationship| (sar.name = 'adjacent stratum surface definition') AND NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_SURFACE' IN TYPEOF(sar.relating_shape_aspect)) AND (sar.relating_shape_aspect.description IN [ 'primary surface', 'secondary surface' ])))) = 0;

wr2:
SIZEOF(
QUERY (sar <* shape_aspect_relationship| (sar.name = 'adjacent stratum surface definition') AND NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_SURFACE' IN TYPEOF(sar.related_shape_aspect)) AND (sar.relating_shape_aspect.description IN [ 'primary surface', 'secondary surface' ])))) = 0;
END_RULE;




RULE application_context_requires_ap_definition FOR (
application_context, 
application_protocol_definition );
WHERE

wr1:
SIZEOF(
QUERY (ac <* application_context| NOT (SIZEOF(
QUERY (apd <* application_protocol_definition| (ac :=: apd.application) AND (apd.application_interpreted_model_schema_name = 'electronic_assembly_interconnect_and_packaging_design'))) = 1))) = 0;
END_RULE;




RULE approval_requires_approval_date_time FOR (
approval, 
approval_date_time );
WHERE

wr1:
SIZEOF(
QUERY (app <* approval| NOT (SIZEOF(
QUERY (adt <* approval_date_time| (app :=: adt.dated_approval))) = 1))) = 0;
END_RULE;




RULE approval_requires_approval_person_organization FOR (
approval, 
approval_person_organization );
WHERE

wr1:
SIZEOF(
QUERY (app <* approval| NOT (SIZEOF(
QUERY (apo <* approval_person_organization| (app :=: apo.authorized_approval))) >= 1))) = 0;
END_RULE;




RULE approvals_are_assigned FOR (
approval, 
approval_assignment );
WHERE

wr1:
SIZEOF(
QUERY (app <* approval| NOT (SIZEOF(
QUERY (aa <* approval_assignment| (app :=: aa.assigned_approval))) >= 1))) = 0;
END_RULE;




RULE cartesian_coordinate_system_constraint FOR (
global_unit_assigned_context, 
geometric_representation_context, 
global_uncertainty_assigned_context );
WHERE

wr1:
SIZEOF(
QUERY (guac <* global_unit_assigned_context| NOT (SIZEOF(guac.units) <= 3))) = 0;

wr2:
SIZEOF(
QUERY (guac <* global_unit_assigned_context| NOT (((SIZEOF(
QUERY (u <* guac.units| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.LENGTH_UNIT' IN TYPEOF(u)))) = 1) AND (SIZEOF(
QUERY (u <* guac.units| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PLANE_ANGLE_UNIT' IN TYPEOF(u)) AND ((u.name = radian) OR ((('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.CONVERSION_BASED_UNIT' IN TYPEOF(u)) AND (u\conversion_based_unit.name = 'degree')) AND (u\conversion_based_unit.conversion_factor.value_component = 57.2958)) AND ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.PLANE_ANGLE_MEASURE_WITH_UNIT' IN TYPEOF(u\conversion_based_unit.conversion_factor))))) = 1)) AND (SIZEOF(
QUERY (u <* guac.units| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.SOLID_ANGLE_UNIT' IN TYPEOF(u)))) <= 1)))) = 0;

wr3:
SIZEOF(
QUERY (grc <* geometric_representation_context| NOT ((grc.coordinate_space_dimension = 2) OR (grc.coordinate_space_dimension = 3)))) = 0;

wr4:
SIZEOF(
QUERY (guac <* global_uncertainty_assigned_context| NOT (SIZEOF(
QUERY (u <* guac.uncertainty| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LENGTH_MEASURE_WITH_UNIT' IN TYPEOF(u)))) = 1))) = 0;
END_RULE;




RULE certification_requires_date_or_date_and_time FOR (
certification, 
applied_date_and_time_assignment, 
applied_date_assignment );
WHERE

wr1:
SIZEOF(
QUERY (cert <* certification| NOT ((SIZEOF(
QUERY (adata <* applied_date_and_time_assignment| (cert IN adata.items))) = 1) OR (SIZEOF(
QUERY (ada <* applied_date_assignment| (cert IN ada.items))) = 1)))) = 0;
END_RULE;




RULE compatible_dimension FOR (
cartesian_point, 
direction, 
representation_context, 
geometric_representation_context );
WHERE

wr1:
SIZEOF(
QUERY (x <* cartesian_point| (SIZEOF(
QUERY (y <* geometric_representation_context| item_in_context(x, y) AND (HIINDEX(x.coordinates) <> y.coordinate_space_dimension))) > 0))) = 0;

wr2:
SIZEOF(
QUERY (x <* direction| (SIZEOF(
QUERY (y <* geometric_representation_context| item_in_context(x, y) AND (HIINDEX(x.direction_ratios) <> y.coordinate_space_dimension))) > 0))) = 0;
END_RULE;




RULE component_external_reference_constraint FOR (
representation );
WHERE

wr1:
SIZEOF(
QUERY (rep <* representation| (rep.name = 'component external reference') AND (SIZEOF(
QUERY (dri <* rep.items| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(dri)) AND (dri.name = 'design owner')))) = 1))) = 0;

wr2:
SIZEOF(
QUERY (rep <* representation| (rep.name = 'component external reference') AND (SIZEOF(
QUERY (dri <* rep.items| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(dri)) AND (dri.name = 'part number')))) = 1))) = 0;

wr3:
SIZEOF(
QUERY (rep <* representation| (rep.name = 'component external reference') AND (SIZEOF(
QUERY (dri <* rep.items| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(dri)) AND (dri.name = 'revision code')))) = 1))) = 0;

wr4:
SIZEOF(
QUERY (rep <* representation| (rep.name = 'component external reference') AND (SIZEOF(
QUERY (dri <* rep.items| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(dri)) AND (dri.name = 'product definition id')))) = 1))) = 0;

wr5:
SIZEOF(
QUERY (rep <* representation| (rep.name = 'component external reference') AND (SIZEOF(
QUERY (dri <* rep.items| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(dri)) AND (dri.name = 'reference designation')))) = 1))) = 0;
END_RULE;




RULE component_part_2d_geometric_representation_relationship_constraint FOR (
shape_representation_relationship );
LOCAL

rr : SET OF representation_relationship := 
QUERY (srr <* shape_representation_relationship| srr\representation_relationship.name = 'component part planar shape');
END_LOCAL;
WHERE

wr1:
SIZEOF(
QUERY (srr_t <* rr| NOT (srr_t.rep_1 :=: srr_t.rep_2))) = 0;
END_RULE;




RULE component_part_3d_geometric_representation_relationship_constraint FOR (
shape_representation_relationship );
LOCAL

rr : SET OF representation_relationship := 
QUERY (srr <* shape_representation_relationship| srr\representation_relationship.name = 'component part 3d shape');
END_LOCAL;
WHERE

wr1:
SIZEOF(
QUERY (srr_t <* rr| NOT (srr_t.rep_1 :=: srr_t.rep_2))) = 0;
END_RULE;




RULE configuration_item_requires_person_organization FOR (
configuration_item, 
applied_person_and_organization_assignment, 
applied_organization_assignment );
WHERE

wr1:
SIZEOF(
QUERY (ci <* configuration_item| NOT ((SIZEOF(
QUERY (apaoa <* applied_person_and_organization_assignment| (ci IN apaoa.items))) = 1) OR (SIZEOF(
QUERY (aoa <* applied_organization_assignment| (ci IN aoa.items))) = 1)))) = 0;
END_RULE;




RULE connection_zone_constraint FOR (
shape_aspect );
WHERE

wr1:
SIZEOF(
QUERY (sa <* shape_aspect| (sa.description = 'connection zone') AND (SIZEOF(
QUERY (pd <* USEDIN(sa, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| NOT (SIZEOF(
QUERY (sdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_DEFINITION_REPRESENTATION' IN TYPEOF(sdr)) AND (sdr.used_representation.context_of_items.context_type = 'connection zone colour'))) = 1))) = 0))) = 0;

wr2:
SIZEOF(
QUERY (sa <* shape_aspect| (sa.description = 'connection zone') AND (SIZEOF(
QUERY (pd <* USEDIN(sa, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| (SIZEOF(
QUERY (sdr <* USEDIN(pd, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_REPRESENTATION' IN TYPEOF(sdr.used_representation)) AND (sdr.used_representation.name = 'zone shape'))) = 1))) = 0))) = 0;

wr3:
SIZEOF(
QUERY (sa <* shape_aspect| (sa.description = 'connection zone') AND NOT (SIZEOF(
QUERY (sar <* USEDIN(sa, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_RELATIONSHIP.RELATED_SHAPE_ASPECT')| (sar.name IN [ 'terminal connection zone', 'internal connection zone', 'external connection zone', 'external connection area', 'minimum attachment region size' ]))) <= 1))) = 0;
END_RULE;




RULE coordinated_assembly_and_shape FOR (
next_assembly_usage_occurrence );
WHERE

wr1:
SIZEOF(
QUERY (nauo <* next_assembly_usage_occurrence| NOT assembly_shape_is_defined(nauo, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN'))) = 0;
END_RULE;




RULE date_constraint FOR (
date );
WHERE

wr1:
SIZEOF(
QUERY (d <* date| (d.year_component < 1856))) = 0;
END_RULE;




RULE dependent_instantiable_action_directive FOR (
action_directive );
WHERE

wr1:
SIZEOF(
QUERY (ad <* action_directive| NOT (SIZEOF(USEDIN(ad, '')) >= 1))) = 0;
END_RULE;




RULE dependent_instantiable_address FOR (
address );
WHERE

wr1:
SIZEOF(
QUERY (add <* address| NOT (SIZEOF(USEDIN(add, '')) >= 1))) = 0;
END_RULE;




RULE dependent_instantiable_approval_status FOR (
approval_status );
WHERE

wr1:
SIZEOF(
QUERY (ast <* approval_status| NOT (SIZEOF(USEDIN(ast, '')) >= 1))) = 0;
END_RULE;




RULE dependent_instantiable_certification_type FOR (
certification_type );
WHERE

wr1:
SIZEOF(
QUERY (ct <* certification_type| NOT (SIZEOF(USEDIN(ct, '')) >= 1))) = 0;
END_RULE;




RULE dependent_instantiable_contract_type FOR (
contract_type );
WHERE

wr1:
SIZEOF(
QUERY (ct <* contract_type| NOT (SIZEOF(USEDIN(ct, '')) >= 1))) = 0;
END_RULE;




RULE dependent_instantiable_date FOR (
date );
WHERE

wr1:
SIZEOF(
QUERY (dt <* date| NOT (SIZEOF(USEDIN(dt, '')) >= 1))) = 0;
END_RULE;




RULE dependent_instantiable_date_role FOR (
date_role );
WHERE

wr1:
SIZEOF(
QUERY (dr <* date_role| NOT (SIZEOF(USEDIN(dr, '')) >= 1))) = 0;
END_RULE;




RULE dependent_instantiable_date_time_role FOR (
date_time_role );
WHERE

wr1:
SIZEOF(
QUERY (dtr <* date_time_role| NOT (SIZEOF(USEDIN(dtr, '')) >= 1))) = 0;
END_RULE;




RULE dependent_instantiable_document_type FOR (
document_type );
WHERE

wr1:
SIZEOF(
QUERY (dt <* document_type| NOT (SIZEOF(USEDIN(dt, '')) >= 1))) = 0;
END_RULE;




RULE dependent_instantiable_named_unit FOR (
named_unit );
WHERE

wr1:
SIZEOF(
QUERY (nu <* named_unit| NOT (SIZEOF(USEDIN(nu, '')) >= 1))) = 0;
END_RULE;




RULE dependent_instantiable_organization_role FOR (
organization_role );
WHERE

wr1:
SIZEOF(
QUERY (org <* organization_role| NOT (SIZEOF(USEDIN(org, '')) >= 1))) = 0;
END_RULE;




RULE dependent_instantiable_parametric_representation_context FOR (
parametric_representation_context );
WHERE

wr1:
SIZEOF(
QUERY (prc <* parametric_representation_context| NOT (SIZEOF(USEDIN(prc, '')) >= 1))) = 0;
END_RULE;




RULE dependent_instantiable_person_and_organization_role FOR (
person_and_organization_role );
WHERE

wr1:
SIZEOF(
QUERY (poar <* person_and_organization_role| NOT (SIZEOF(USEDIN(poar, '')) >= 1))) = 0;
END_RULE;




RULE dependent_instantiable_representation_item FOR (
representation_item );
WHERE

wr1:
SIZEOF(
QUERY (ri <* representation_item| NOT (SIZEOF(USEDIN(ri, '')) >= 1))) = 0;
END_RULE;




RULE dependent_instantiable_security_classification_level FOR (
security_classification_level );
WHERE

wr1:
SIZEOF(
QUERY (scl <* security_classification_level| NOT (SIZEOF(USEDIN(scl, '')) >= 1))) = 0;
END_RULE;




RULE dependent_instantiable_shape_representation FOR (
shape_representation );
WHERE

wr1:
SIZEOF(
QUERY (sr <* shape_representation| NOT (SIZEOF(USEDIN(sr, '')) >= 1))) = 0;
END_RULE;




RULE dependent_instantiable_tolerance_value FOR (
tolerance_value );
WHERE

wr1:
SIZEOF(
QUERY (tv <* tolerance_value| NOT (SIZEOF(USEDIN(tv, '')) >= 1))) = 0;
END_RULE;




RULE design_functional_unit_allocation_to_assembly_component_constraint FOR (
product_definition_relationship );
WHERE

wr1:
SIZEOF(
QUERY (pdr <* product_definition_relationship| (pdr.name = 'design functional unit allocation to assembly component') AND NOT ((pdr.relating_product_definition.description = 'design definition path') AND (pdr.relating_product_definition.id = 'design composition path')))) = 0;

wr2:
SIZEOF(
QUERY (pdr <* product_definition_relationship| (pdr.name = 'design functional unit allocation to assembly component') AND NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_DEFINITION' IN TYPEOF(pdr.related_product_definition)))) = 0;
END_RULE;




RULE design_intent_modification_sequence_constraint FOR (
shape_aspect_relationship );
WHERE

wr1:
SIZEOF(
QUERY (sar <* shape_aspect_relationship| (sar.name = 'shape modification sequence') AND NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_MODIFICATION' IN TYPEOF(sar.relating_shape_aspect)))) = 0;

wr2:
SIZEOF(
QUERY (sar <* shape_aspect_relationship| (sar.name = 'shape modification sequence') AND NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_MODIFICATION' IN TYPEOF(sar.related_shape_aspect)))) = 0;
END_RULE;




RULE device_terminal_map_relationship_constraint FOR (
shape_aspect_relationship );
WHERE

wr1:
SIZEOF(
QUERY (sar <* shape_aspect_relationship| (sar.name = 'device terminal map relationship') AND NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DEVICE_TERMINAL_MAP' IN TYPEOF(sar.relating_shape_aspect)))) = 0;

wr2:
SIZEOF(
QUERY (sar <* shape_aspect_relationship| (sar.name = 'device terminal map relationship') AND NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DEVICE_TERMINAL_MAP' IN TYPEOF(sar.related_shape_aspect)))) = 0;
END_RULE;




RULE directed_action_requires_approval FOR (
directed_action, 
applied_approval_assignment );
WHERE

wr1:
SIZEOF(
QUERY (da <* directed_action| NOT (SIZEOF(
QUERY (aaa <* applied_approval_assignment| (da IN aaa.items))) = 1))) = 0;
END_RULE;




RULE directed_action_requires_date_or_date_and_time FOR (
directed_action, 
applied_date_and_time_assignment, 
applied_date_assignment );
WHERE

wr1:
SIZEOF(
QUERY (da <* directed_action| NOT ((SIZEOF(
QUERY (adata <* applied_date_and_time_assignment| (da IN adata.items) AND (adata.role.name = 'start date'))) = 1) OR (SIZEOF(
QUERY (ada <* applied_date_assignment| (da IN ada.items) AND (ada.role.name = 'start date'))) = 1)))) = 0;
END_RULE;




RULE ee_rule_definition_constraint FOR (
representation );
WHERE

wr1:
(SIZEOF(
QUERY (rep <* representation| (rep.name = 'rule definition'))) = 0) OR (SIZEOF(
QUERY (rep <* representation| (SIZEOF(
QUERY (dri <* rep.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(dri)) AND (dri.name = 'identifier'))) = 1))) = 1);
END_RULE;




RULE interface_component_allocation_constraint FOR (
product_definition_relationship );
WHERE

wr1:
SIZEOF(
QUERY (pdr <* product_definition_relationship| (pdr.name = 'interface component allocation') AND NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_DEFINITION' IN TYPEOF(pdr.relating_product_definition)) AND (pdr.relating_product_definition.description = 'mating connector')))) = 0;
END_RULE;




RULE mandatory_product_category_value FOR (
product_category );
WHERE

wr1:
SIZEOF(
QUERY (pc <* product_category| (pc\product_category.name IN [ 'assembly', 'material', 'detail', 'piece part', 'bare die', 'package', 'packaged part', 'printed part', 'customer furnished equipment', 'inseparable assembly', 'interconnect', 'technology specific land pattern', 'technology specific padstack', 'assembly module', 'interconnect module', 'design layer', 'documentation layer', 'functionality', 'simulation model', 'requirements model' ]))) >= 1;
END_RULE;




RULE no_shape_for_make_from FOR (
make_from_usage_option );
WHERE

wr1:
SIZEOF(
QUERY (mfuo <* make_from_usage_option| NOT (SIZEOF(
QUERY (pd <* USEDIN(mfuo, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION.DEFINITION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_SHAPE' IN TYPEOF(pd)))) = 0))) = 0;
END_RULE;




RULE package_external_reference_constraint FOR (
representation );
WHERE

wr1:
SIZEOF(
QUERY (rep <* representation| (rep.name = 'package external reference') AND (SIZEOF(
QUERY (dri <* rep.items| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(dri)) AND (dri.name = 'design owner')))) = 1))) = 0;

wr2:
SIZEOF(
QUERY (rep <* representation| (rep.name = 'package external reference') AND (SIZEOF(
QUERY (dri <* rep.items| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(dri)) AND (dri.name = 'part number')))) = 1))) = 0;

wr3:
SIZEOF(
QUERY (rep <* representation| (rep.name = 'package external reference') AND (SIZEOF(
QUERY (dri <* rep.items| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(dri)) AND (dri.name = 'revision code')))) = 1))) = 0;

wr4:
SIZEOF(
QUERY (rep <* representation| (rep.name = 'package external reference') AND (SIZEOF(
QUERY (dri <* rep.items| NOT (('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(dri)) AND (dri.name = 'product definition id')))) = 1))) = 0;
END_RULE;




RULE pdf_requires_security_classification FOR (
product_definition_formation, 
applied_security_classification_assignment );
WHERE

wr1:
SIZEOF(
QUERY (pdf <* product_definition_formation| NOT (SIZEOF(
QUERY (asca <* applied_security_classification_assignment| (pdf IN asca.items))) = 1))) = 0;
END_RULE;




RULE product_concept_requires_configuration_item FOR (
product_concept, 
configuration_item );
WHERE

wr1:
SIZEOF(
QUERY (pc <* product_concept| NOT (SIZEOF(
QUERY (ci <* configuration_item| (pc :=: ci.item_concept))) >= 1))) = 0;
END_RULE;




RULE product_definition_formation_requires_approval FOR (
product_definition_formation, 
applied_approval_assignment );
WHERE

wr1:
SIZEOF(
QUERY (pdf <* product_definition_formation| NOT (SIZEOF(
QUERY (aaa <* applied_approval_assignment| (pdf IN aaa.items))) = 1))) = 0;
END_RULE;




RULE product_definition_formation_requires_person_organization FOR (
product_definition_formation, 
applied_person_and_organization_assignment, 
applied_organization_assignment );
WHERE

wr1:
SIZEOF(
QUERY (pdf <* product_definition_formation| NOT ((SIZEOF(
QUERY (apaoa <* applied_person_and_organization_assignment| (pdf IN apaoa.items) AND (apaoa.role.name = 'creator'))) = 1) OR (SIZEOF(
QUERY (aoa <* applied_organization_assignment| (pdf IN aoa.items) AND (aoa.role.name = 'creator'))) = 1)))) = 0;

wr2:
SIZEOF(
QUERY (pdf <* product_definition_formation| NOT ((SIZEOF(
QUERY (apaoa <* applied_person_and_organization_assignment| (pdf IN apaoa.items) AND (apaoa.role.name IN [ 'design supplier', 'product supplier' ]))) >= 1) OR (SIZEOF(
QUERY (aoa <* applied_organization_assignment| (pdf IN aoa.items) AND (aoa.role.name IN [ 'design supplier', 'product supplier' ]))) >= 1)))) = 0;
END_RULE;




RULE product_definition_requires_date_or_date_and_time FOR (
product_definition, 
applied_date_and_time_assignment, 
applied_date_assignment );
WHERE

wr1:
SIZEOF(
QUERY (pd <* product_definition| NOT ((SIZEOF(
QUERY (adata <* applied_date_and_time_assignment| (pd IN adata.items))) = 1) OR (SIZEOF(
QUERY (ada <* applied_date_assignment| (pd IN ada.items))) = 1)))) = 0;
END_RULE;




RULE product_definition_requires_person_organization FOR (
product_definition, 
applied_person_and_organization_assignment, 
applied_organization_assignment );
WHERE

wr1:
SIZEOF(
QUERY (pd <* product_definition| NOT ((SIZEOF(
QUERY (apaoa <* applied_person_and_organization_assignment| (pd IN apaoa.items))) = 1) OR (SIZEOF(
QUERY (aoa <* applied_organization_assignment| (pd IN aoa.items))) = 1)))) = 0;
END_RULE;




RULE product_requires_person_organization FOR (
product, 
applied_person_and_organization_assignment, 
applied_organization_assignment );
WHERE

wr1:
SIZEOF(
QUERY (prod <* product| NOT ((SIZEOF(
QUERY (apaoa <* applied_person_and_organization_assignment| (prod IN apaoa.items))) = 1) OR (SIZEOF(
QUERY (aoa <* applied_organization_assignment| (prod IN aoa.items))) = 1)))) = 0;
END_RULE;




RULE product_requires_product_definition_formation FOR (
product, 
product_definition_formation );
WHERE

wr1:
SIZEOF(
QUERY (prod <* product| NOT (SIZEOF(
QUERY (pdf <* product_definition_formation| (prod :=: pdf.of_product))) >= 1))) = 0;
END_RULE;




RULE restrict_action_request_status FOR (
action_request_status );
WHERE

wr1:
SIZEOF(
QUERY (ars <* action_request_status| NOT (ars.status IN [ 'proposed', 'in work', 'issued', 'hold' ]))) = 0;
END_RULE;




RULE restrict_approval_status FOR (
approval_status );
WHERE

wr1:
SIZEOF(
QUERY (ast <* approval_status| NOT (ast.name IN [ 'approved', 'not yet approved', 'disapproved', 'withdrawn' ]))) = 0;
END_RULE;




RULE restrict_date_role FOR (
date_role );
WHERE

wr1:
SIZEOF(
QUERY (dr <* date_role| NOT (dr.name IN [ 'creation date', 'request date', 'release date', 'start date', 'contract date', 'certification date', 'sign off date', 'classification date', 'declassification date' ]))) = 0;
END_RULE;




RULE restrict_manifold_surface_shape_representation FOR (
manifold_surface_shape_representation );
WHERE

wr1:
SIZEOF(
QUERY (mssr <* manifold_surface_shape_representation| (mssr.name IN [ 'stratum feature non planar 2d shape', 'open shell based surface', 'design intent modification non planar 2d shape', 'part template non planar 2d shape' ]) AND NOT (SIZEOF(
QUERY (sbsm <* mssr.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHELL_BASED_SURFACE_MODEL' IN TYPEOF(sbsm)) AND (SIZEOF(
QUERY (os <* sbsm\shell_based_surface_model.sbsm_boundary| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'OPEN_SHELL' IN TYPEOF(os)))) = 1))) = 1))) = 0;
END_RULE;




RULE rule_priority_constraint FOR (
representation );
LOCAL

rpc_group_1 : SET OF representation := 
QUERY (rule_group_1 <* representation| rule_group_1.name = 'rule property');
END_LOCAL;
WHERE

wr1:
SIZEOF(
QUERY (x <* rpc_group_1| (NOT SIZEOF(
QUERY (y <* x.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESCRIPTIVE_REPRESENTATION_ITEM' IN TYPEOF(y)))) = 1))) = 0;

wr2:
SIZEOF(
QUERY (x <* rpc_group_1| NOT (SIZEOF(
QUERY (y <* USEDIN(x, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PROPERTY_DEFINITION_REPRESENTATION.' + 'USED_REPRESENTATION')| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'RULE_DEFINITION' IN TYPEOF(y.definition.definition)))) >= 1))) = 0;
END_RULE;




RULE security_classification_constraint FOR (
security_classification, 
applied_date_and_time_assignment, 
applied_date_assignment );
WHERE

wr1:
SIZEOF(
QUERY (sc <* security_classification| NOT ((SIZEOF(
QUERY (adata <* applied_date_and_time_assignment| (sc IN adata.items) AND ('classification date' = adata.role.name))) = 1) OR (SIZEOF(
QUERY (ada <* applied_date_assignment| (sc IN ada.items) AND ('classification date' = ada.role.name))) = 1)))) = 0;
END_RULE;




RULE shape_dimension_representation_constraint FOR (
shape_dimension_representation );
WHERE

wr1:
SIZEOF(
QUERY (sdr <* shape_dimension_representation| NOT (SIZEOF(
QUERY (i <* sdr.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_WITH_UNIT' IN TYPEOF(i)) AND (SIZEOF(
QUERY (mq <* USEDIN(i, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_QUALIFICATION.QUALIFIED_MEASURE')| (mq.name = 'dimension value qualifier'))) <= 1))) >= 1))) = 0;

wr2:
SIZEOF(
QUERY (sdr <* shape_dimension_representation| (SIZEOF(
QUERY (i <* sdr.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_WITH_UNIT' IN TYPEOF(i)) AND (SIZEOF(
QUERY (mq <* USEDIN(i, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_QUALIFICATION.QUALIFIED_MEASURE')| (mq.name = 'dimension value qualifier') AND (SIZEOF(
QUERY (q <* mq.qualifiers| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'TYPE_QUALIFIER' IN TYPEOF(q)))) <> 1))) > 0))) > 0))) = 0;

wr3:
SIZEOF(
QUERY (sdr <* shape_dimension_representation| (SIZEOF(
QUERY (i <* sdr.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_WITH_UNIT' IN TYPEOF(i)) AND (SIZEOF(
QUERY (mq <* USEDIN(i, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_QUALIFICATION.QUALIFIED_MEASURE')| (mq.name = 'dimension value qualifier') AND (SIZEOF(
QUERY (q <* mq.qualifiers| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'TYPE_QUALIFIER' IN TYPEOF(q)) AND NOT (q.name IN [ 'theoretically exact', 'maximum dimension', 'minumum dimersion', 'lower value', 'upper value', 'basic value' ]))) > 0))) > 0))) > 0))) = 0;

wr4:
SIZEOF(
QUERY (sdr <* shape_dimension_representation| (SIZEOF(
QUERY (i <* sdr.items| ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_WITH_UNIT' IN TYPEOF(i)) AND (SIZEOF(
QUERY (mq <* USEDIN(i, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MEASURE_QUALIFICATION.QUALIFIED_MEASURE')| NOT (mq.name IN [ 'dimension value qualifier', 'predefined dimension qualifier', 'user defined dimension qualifier' ]))) > 0))) > 0))) = 0;

wr5:
SIZEOF(
QUERY (sdr <* shape_dimension_representation| NOT (SIZEOF(USEDIN(sdr, 'ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DIMENSIONAL_CHARACTERISTIC_REPRESENTATION.' + 'REPRESENTATION')) >= 1))) = 0;
END_RULE;




RULE shape_representation_requires_origin FOR (
shape_representation, 
axis2_placement_2d, 
axis2_placement_3d );
WHERE

wr1:
SIZEOF(
QUERY (sr <* shape_representation| NOT (SIZEOF(
QUERY (ax <* axis2_placement_2d| (ax IN sr.items) AND (ax\representation_item.name = 'origin'))) + SIZEOF(
QUERY (ax <* axis2_placement_3d| (ax IN sr.items) AND (ax\representation_item.name = 'origin'))) = 1))) = 0;
END_RULE;




RULE subtype_combination_shape_aspect FOR (
shape_aspect );
WHERE

wr1:
SIZEOF(
QUERY (sa <* shape_aspect| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_BOND_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_JOINT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_MODULE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MINIMALLY_DEFINED_BARE_DIE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_FUNCTIONAL_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_INTERFACE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_SHAPE_ASPECT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CONNECTIVITY_SUB_STRUCTURE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DATUM_REFERENCE_FRAME'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DATUM_SYSTEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DERIVED_SHAPE_ASPECT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESIGN_OBJECT_SHAPE_ASPECT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DEVICE_TERMINAL_MAP'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FABRICATION_JOINT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FUNCTIONAL_UNIT_TERMINAL_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GROUP_SHAPE_ASPECT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTERCONNECT_MODULE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTERFACE_MOUNTED_JOIN'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'JOIN_SHAPE_ASPECT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND_TEMPLATE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAYER'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAYER_CONNECTION_POINT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MOUNTING_RESTRICTION_AREA'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE_BODY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_CONNECTOR_TERMINAL_RELATIONSHIP'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_CONNECTED_TERMINALS_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_TEMPLATE_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PASSAGE_TECHNOLOGY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_CONNECTIVITY_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_CONNECTIVITY_ELEMENT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_NETWORK'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'POSITIONAL_BOUNDARY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'POSITIONAL_BOUNDARY_MEMBER'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRINTED_PART_CROSS_SECTION_TEMPLATE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRINTED_PART_TEMPLATE_CONNECTED_TERMINALS_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRINTED_PART_TEMPLATE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SEQUENTIAL_LAMINATE_ASSEMBLY_JOINT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_MODIFICATION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_CONCEPT_RELATIONSHIP'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_FEATURE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_SURFACE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'TOLERANCE_ZONE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'TOLERANCE_ZONE_BOUNDARY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'VIEWING_PLANE') ] * TYPEOF(sa)) <= 1))) = 0;

wr2:
SIZEOF(
QUERY (sa <* shape_aspect| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_BOND_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_JOINT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_MODULE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MINIMALLY_DEFINED_BARE_DIE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_FUNCTIONAL_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_INTERFACE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_SHAPE_ASPECT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CONNECTIVITY_SUB_STRUCTURE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DATUM_REFERENCE_FRAME'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DATUM_SYSTEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESIGN_OBJECT_SHAPE_ASPECT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DEVICE_TERMINAL_MAP'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FABRICATION_JOINT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FUNCTIONAL_UNIT_TERMINAL_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GROUP_SHAPE_ASPECT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTERCONNECT_MODULE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTERFACE_MOUNTED_JOIN'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'JOIN_SHAPE_ASPECT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND_TEMPLATE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAYER'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAYER_CONNECTION_POINT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MOUNTING_RESTRICTION_AREA'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE_BODY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_CONNECTOR_TERMINAL_RELATIONSHIP'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_PART_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_CONNECTED_TERMINALS_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_TEMPLATE_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PASSAGE_TECHNOLOGY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_CONNECTIVITY_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_CONNECTIVITY_ELEMENT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_NETWORK'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_UNIT_DATUM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'POSITIONAL_BOUNDARY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'POSITIONAL_BOUNDARY_MEMBER'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRINTED_PART_CROSS_SECTION_TEMPLATE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRINTED_PART_TEMPLATE_CONNECTED_TERMINALS_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRINTED_PART_TEMPLATE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SEQUENTIAL_LAMINATE_ASSEMBLY_JOINT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_MODIFICATION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_CONCEPT_RELATIONSHIP'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_FEATURE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_SURFACE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'TOLERANCE_ZONE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'TOLERANCE_ZONE_BOUNDARY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'VIEWING_PLANE') ] * TYPEOF(sa)) <= 1))) = 0;

wr3:
SIZEOF(
QUERY (sa <* shape_aspect| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_BOND_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_JOINT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_FUNCTIONAL_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_INTERFACE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_SHAPE_ASPECT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CONNECTIVITY_SUB_STRUCTURE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DATUM_REFERENCE_FRAME'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DATUM_SYSTEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DERIVED_SHAPE_ASPECT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DEVICE_TERMINAL_MAP'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FABRICATION_JOINT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FUNCTIONAL_UNIT_TERMINAL_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GROUP_SHAPE_ASPECT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTERFACE_MOUNTED_JOIN'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'JOIN_SHAPE_ASPECT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAND_TEMPLATE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAYER'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LAYER_CONNECTION_POINT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MOUNTING_RESTRICTION_AREA'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGE_BODY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_CONNECTED_TERMINALS_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_TEMPLATE_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PASSAGE_TECHNOLOGY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_CONNECTIVITY_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_CONNECTIVITY_ELEMENT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_NETWORK'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_UNIT_DATUM_FEATURE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_UNIT_DATUM_TARGET'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'POSITIONAL_BOUNDARY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'POSITIONAL_BOUNDARY_MEMBER'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRINTED_PART_CROSS_SECTION_TEMPLATE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRINTED_PART_TEMPLATE_CONNECTED_TERMINALS_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRINTED_PART_TEMPLATE_TERMINAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SEQUENTIAL_LAMINATE_ASSEMBLY_JOINT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_MODIFICATION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_CONCEPT_RELATIONSHIP'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_FEATURE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_SURFACE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'TOLERANCE_ZONE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'TOLERANCE_ZONE_BOUNDARY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'VIEWING_PLANE') ] * TYPEOF(sa)) <= 1))) = 0;

wr4:
SIZEOF(
QUERY (sa <* shape_aspect| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_UNIT_DATUM_FEATURE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_UNIT_DATUM_TARGET'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_UNIT_DATUM') ] * TYPEOF(sa)) <= 1))) = 0;
END_RULE;




RULE subtype_exclusive_action_request_assignment FOR (
action_request_assignment );
WHERE

wr1:
SIZEOF(
QUERY (ara <* action_request_assignment| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CHANGE_REQUEST'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'START_REQUEST') ] * TYPEOF(ara)) <= 1))) = 0;
END_RULE;




RULE subtype_exclusive_dimensional_location FOR (
dimensional_location );
WHERE

wr1:
SIZEOF(
QUERY (dl <* dimensional_location| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ANGULAR_DIMENSION_WITH_ORIENTATION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DIMENSIONAL_LOCATION_WITH_DIRECTION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DIMENSIONAL_LOCATION_WITH_PATH') ] * TYPEOF(dl)) <= 1))) = 0;
END_RULE;




RULE subtype_exclusive_dimensional_size FOR (
dimensional_size );
WHERE

wr1:
SIZEOF(
QUERY (ds <* dimensional_size| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CURVE_DIMENSION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ANGULAR_SIZE') ] * TYPEOF(ds)) <= 1) OR NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CURVE_DIMENSION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'OPPOSING_BOUNDARY_DIMENSIONAL_SIZE') ] * TYPEOF(ds)) <= 1))) = 0;
END_RULE;




RULE subtype_exclusive_mapped_item FOR (
mapped_item );
WHERE

wr1:
SIZEOF(
QUERY (mi <* mapped_item| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ANNOTATION_TEXT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ANNOTATION_SYMBOL') ] * TYPEOF(mi)) <= 1))) = 0;
END_RULE;




RULE subtype_exclusive_product_definition FOR (
product_definition );
WHERE

wr1:
SIZEOF(
QUERY (pd <* product_definition| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'BUS_STRUCTURAL_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_FUNCTIONAL_UNIT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FUNCTIONAL_UNIT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'NETWORK_NODE_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_UNIT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM') ] * TYPEOF(pd)) <= 1))) = 0;
END_RULE;




RULE subtype_exclusive_product_definition_relationship FOR (
product_definition_relationship );
WHERE

wr1:
SIZEOF(
QUERY (pdr <* product_definition_relationship| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_USAGE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_MATERIAL_COMPOSITION_RELATIONSHIP'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SUPPLIED_PART_RELATIONSHIP') ] * TYPEOF(pdr)) <= 1))) = 0;
END_RULE;




RULE subtype_exclusive_property_definition FOR (
property_definition );
WHERE

wr1:
SIZEOF(
QUERY (pd <* property_definition| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DIMENSIONAL_SIZE_PROPERTY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GEOMETRIC_TOLERANCE_GROUP'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MATERIAL_PROPERTY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_UNIT_GEOMETRIC_TOLERANCE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRODUCT_DEFINITION_SHAPE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REQUIREMENTS_PROPERTY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SIGNAL') ] * TYPEOF(pd)) <= 1))) = 0;
END_RULE;




RULE subtype_exclusive_property_definition_representation FOR (
property_definition_representation );
WHERE

wr1:
SIZEOF(
QUERY (pdr <* property_definition_representation| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_DEFINITION_REPRESENTATION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MATERIAL_PROPERTY_REPRESENTATION') ] * TYPEOF(pdr)) <= 1))) = 0;
END_RULE;




RULE subtype_exclusive_representation FOR (
representation );
WHERE

wr1:
SIZEOF(
QUERY (rep <* representation| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ANALYTICAL_MODEL_PORT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPONENT_LOCATION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'RULE_FUNCTION_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'TEXT_STRING_REPRESENTATION') ] * TYPEOF(rep)) <= 1))) = 0;
END_RULE;




RULE subtype_exclusive_representation_context FOR (
representation_context );
WHERE

wr1:
SIZEOF(
QUERY (rc <* representation_context| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GEOMETRIC_REPRESENTATION_CONTEXT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PARAMETRIC_REPRESENTATION_CONTEXT') ] * TYPEOF(rc)) <= 1))) = 0;
END_RULE;




RULE subtype_exclusive_shape_aspect_relationship FOR (
shape_aspect_relationship );
WHERE

wr1:
SIZEOF(
QUERY (sar <* shape_aspect_relationship| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_JOINT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DEVICE_TERMINAL_MAP'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DIMENSIONAL_LOCATION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTERFACE_MOUNTED_JOIN'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MAKE_FROM_CONNECTIVITY_RELATIONSHIP'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MAKE_FROM_FEATURE_RELATIONSHIP'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PACKAGED_CONNECTOR_TERMINAL_RELATIONSHIP'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_CONNECTIVITY_ELEMENT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_ASPECT_DERIVING_RELATIONSHIP'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_CONCEPT_RELATIONSHIP') ] * TYPEOF(sar)) <= 1))) = 0;
END_RULE;




RULE subtype_mandatory_action FOR (
action );
WHERE

wr1:
SIZEOF(
QUERY (act <* action| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DIRECTED_ACTION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXECUTED_ACTION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'RULE_ACTION') ] * TYPEOF(act)) = 1))) = 0;
END_RULE;




RULE subtype_mandatory_address FOR (
address );
WHERE

wr1:
SIZEOF(
QUERY (add <* address| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PERSONAL_ADDRESS'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ORGANIZATIONAL_ADDRESS') ] * TYPEOF(add)) = 1))) = 0;
END_RULE;




RULE subtype_mandatory_characterized_object FOR (
characterized_object );
WHERE

wr1:
SIZEOF(
QUERY (co <* characterized_object| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CHARACTERIZED_PRODUCT_CATEGORY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'DESIGN_OBJECT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNAL_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'INTERCONNECT_MODULE_DESIGN_OBJECT_CATEGORY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_TEMPLATE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'RULE_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SIGNAL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'STRATUM_TECHNOLOGY') ] * TYPEOF(co)) = 1))) = 0;
END_RULE;




RULE subtype_mandatory_colour FOR (
colour );
WHERE

wr1:
SIZEOF(
QUERY (c <* colour| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COLOUR_RGB' IN TYPEOF(c)))) = 0;
END_RULE;




RULE subtype_mandatory_composite_shape_aspect FOR (
composite_shape_aspect );
WHERE

wr1:
SIZEOF(
QUERY (csa <* composite_shape_aspect| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPOSITE_GROUP_SHAPE_ASPECT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'COMPOSITE_UNIT_SHAPE_ASPECT') ] * TYPEOF(csa)) = 1))) = 0;
END_RULE;




RULE subtype_mandatory_date FOR (
date );
WHERE

wr1:
SIZEOF(
QUERY (d <* date| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CALENDAR_DATE' IN TYPEOF(d)))) = 0;
END_RULE;




RULE subtype_mandatory_externally_defined_item FOR (
externally_defined_item );
WHERE

wr1:
SIZEOF(
QUERY (edi <* externally_defined_item| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'BOND_CATEGORY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNAL_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_FUNCTIONAL_UNIT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_PHYSICAL_UNIT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EXTERNALLY_DEFINED_REPRESENTATION_ITEM'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'LIBRARY_DEFINED_MODEL'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PART_TEMPLATE_DEFINITION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SIGNAL_CATEGORY') ] * TYPEOF(edi)) = 1))) = 0;
END_RULE;




RULE subtype_mandatory_geometric_tolerance FOR (
geometric_tolerance );
WHERE

wr1:
SIZEOF(
QUERY (gt <* geometric_tolerance| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PHYSICAL_UNIT_GEOMETRIC_TOLERANCE') ] * TYPEOF(gt)) = 1))) = 0;
END_RULE;




RULE subtype_mandatory_group FOR (
group );
WHERE

wr1:
SIZEOF(
QUERY (grp <* group| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'BOND_CATEGORY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FUNCTIONAL_TERMINAL_GROUP'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GROUPED_REQUIREMENTS_PROPERTY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MATERIAL_ELECTRICAL_CONDUCTIVITY_CATEGORY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PARAMETER_TYPE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRINTED_PART_TEMPLATE_TERMINAL_CONNECTION_ZONE_CATEGORY'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REQUIREMENT_ALLOCATION_GROUP'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'REQUIREMENTS_PROPERTY_GROUP'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'RULE_SET'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SIGNAL_CATEGORY') ] * TYPEOF(grp)) = 1))) = 0;
END_RULE;




RULE subtype_mandatory_pre_defined_item FOR (
pre_defined_item );
WHERE

wr1:
SIZEOF(
QUERY (pdi <* pre_defined_item| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRE_DEFINED_TEXT_FONT'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'PRE_DEFINED_CURVE_FONT') ] * TYPEOF(pdi)) = 1))) = 0;
END_RULE;




RULE subtype_mandatory_product_definition_usage FOR (
product_definition_usage );
WHERE

wr1:
SIZEOF(
QUERY (pdu <* product_definition_usage| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ASSEMBLY_COMPONENT_USAGE'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MAKE_FROM_USAGE_OPTION') ] * TYPEOF(pdu)) = 1))) = 0;
END_RULE;




RULE subtype_mandatory_runout_zone_orientation FOR (
runout_zone_orientation );
WHERE

wr1:
SIZEOF(
QUERY (rzo <* runout_zone_orientation| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'RUNOUT_ZONE_ORIENTATION_REFERENCE_DIRECTION') ] * TYPEOF(rzo)) = 1))) = 0;
END_RULE;




RULE subtype_mandatory_shape_representation FOR (
shape_representation );
WHERE

wr1:
SIZEOF(
QUERY (sr <* shape_representation| NOT (SIZEOF([ ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'ADVANCED_BREP_SHAPE_REPRESENTATION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'CSG_SHAPE_REPRESENTATION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EDGE_BASED_2D_WIREFRAME_SHAPE_REPRESENTATION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'EDGE_BASED_WIREFRAME_SHAPE_REPRESENTATION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'FACETED_BREP_SHAPE_REPRESENTATION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GEOMETRICALLY_BOUNDED_2D_WIREFRAME_SHAPE_REPRESENTATION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GEOMETRICALLY_BOUNDED_WIREFRAME_SHAPE_REPRESENTATION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'GEOMETRICALLY_BOUNDED_SURFACE_SHAPE_REPRESENTATION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'MANIFOLD_SURFACE_SHAPE_REPRESENTATION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHAPE_DIMENSION_REPRESENTATION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHELL_BASED_2D_WIREFRAME_SHAPE_REPRESENTATION'), ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'SHELL_BASED_WIREFRAME_SHAPE_REPRESENTATION') ] * TYPEOF(sr)) = 1))) = 0;
END_RULE;




RULE subtype_mandatory_text_literal FOR (
text_literal );
WHERE

wr1:
SIZEOF(
QUERY (tl <* text_literal| NOT ('ELECTRONIC_ASSEMBLY_INTERCONNECT_AND_PACKAGING_DESIGN.' + 'TEXT_LITERAL_WITH_EXTENT' IN TYPEOF(tl)))) = 0;
END_RULE;




RULE versioned_action_request_requires_approval FOR (
versioned_action_request, 
applied_approval_assignment );
WHERE

wr1:
SIZEOF(
QUERY (varq <* versioned_action_request| NOT (SIZEOF(
QUERY (aaa <* applied_approval_assignment| (varq IN aaa.items))) = 1))) = 0;
END_RULE;




RULE versioned_action_request_requires_date_or_date_and_time FOR (
versioned_action_request, 
applied_date_and_time_assignment, 
applied_date_assignment );
WHERE

wr1:
SIZEOF(
QUERY (varq <* versioned_action_request| NOT ((SIZEOF(
QUERY (adata <* applied_date_and_time_assignment| (varq IN adata.items))) = 1) OR (SIZEOF(
QUERY (ada <* applied_date_assignment| (varq IN ada.items))) = 1)))) = 0;
END_RULE;




RULE versioned_action_request_requires_person_organization FOR (
versioned_action_request, 
applied_person_and_organization_assignment, 
applied_organization_assignment );
WHERE

wr1:
SIZEOF(
QUERY (varq <* versioned_action_request| NOT ((SIZEOF(
QUERY (apaoa <* applied_person_and_organization_assignment| (varq IN apaoa.items))) >= 1) OR (SIZEOF(
QUERY (aoa <* applied_organization_assignment| (varq IN aoa.items))) >= 1)))) = 0;
END_RULE;




RULE versioned_action_request_requires_status FOR (
versioned_action_request, 
action_request_status );
WHERE

wr1:
SIZEOF(
QUERY (ar <* versioned_action_request| NOT (SIZEOF(
QUERY (ars <* action_request_status| (ar :=: ars.assigned_request))) = 1))) = 0;
END_RULE;



(* *********************************** *)


END_SCHEMA;
(* ************************************************************************** *)